ATMEL ATA8202-PXQW

Features
• Transparent RF Receiver ICs for 315 MHz (ATA8201) and 433.92 MHz (ATA8202) With
High Receiving Sensitivity
• Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter
• High FSK/ASK Sensitivity:–105 dBm (ATA8201, FSK, 9.6 Kbits/s, Manchester, BER 10-3)
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–114 dBm (ATA8201, ASK, 2.4 Kbits/s, Manchester, BER 10-3)
–104 dBm (ATA8202, FSK, 9.6 Kbits/s, Manchester, BER 10-3)
–113 dBm (ATA8202, ASK, 2.4 Kbits/s, Manchester, BER 10-3)
Supply Current: 6.5 mA in Active Mode (3V, 25°C, ASK Mode)
Data Rate: 1 Kbit/s to 10 Kbits/s Manchester ASK, 1 Kbit/s to 20 Kbits/s Manchester
FSK With Four Programmable Bit Rate Ranges
Switching Between Modulation Types ASK/FSK and Different Data Rates Possible in
≤ 1 ms Typically, Without Hardware Modification on Board to Allow Different
Modulation Schemes
Low Standby Current: 50 µA at 3V, 25°C
ASK/FSK Receiver Uses a Low-IF Architecture With High Selectivity, Blocking, and
Low Intermodulation (Typical 3-dB Blocking 68.0 dBC at ±3 MHz/74.0 dBC at
±20.0 MHz, System I1dBCP = –31 dBm/System IIP3 = –24 dBm)
Telegram Pause Up to 52 ms Supported in ASK Mode
Wide Bandwidth AGC to Handle Large Out-of-band Blockers above the System I1dBCP
440-kHz IF Frequency With 30-dB Image Rejection and 420-kHz IF Bandwidth to
Support PLL Transmitters With Standard Crystals or SAW-based Transmitters
RSSI (Received Signal Strength Indicator) With Output Signal Dynamic Range of 65 dB
Low In-band Sensitivity Change of Typically ±2.0 dB Within ±160-kHz Center
Frequency Change in the Complete Temperature and Supply Voltage Range
Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer
Fast and Stable XTO Start-up Circuit (> –1.4 kΩ Worst-case Start Impedance)
Clock Generation for Microcontroller
ESD Protection at all Pins (±4 kV HBM, ±200V MM, ±500V FCDM)
Dual Supply Voltage Range: 2.7V to 3.3V or 4.5V to 5.5V
Temperature Range: –40°C to +85°C
Small 5 mm × 5 mm QFN24 Package
UHF ASK/FSK
Receiver
ATA8201
ATA8202
Applications
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Industrial/Aftermarket Keyless Entry and Tire Pressure Monitoring Systems
Alarm, Telemetering and Energy Metering Systems
Remote Control Systems for Consumer and Industrial Markets
Access Control Systems
Home Automation
Home Entertainment
Toys
4971C–INDCO–04/09
Benefits
• Supports Header and Blanking Periods of Protocols Common in RKE and TPM Systems
(Up to 52 ms in ASK Mode)
• All RF Relevant Functions are Integrated. The Single-ended RF Input is Suited for Easy
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2
Adaptation to λ / 4 or Printed-loop Antennas
Allows a Low-cost Application With Only 8 Passive Components
Optimal Bandwidth Maximizes Sensitivity while Maintaining SAW Transmitter Compatibility
Clock Output Provides an External Microcontroller Crystal-precision Time Reference
Well Suited for Use With PLL Transmitter ATA8401/ATA8402/ATA8403/ATA8404/ATA8405
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
1. General Description
The ATA8201/ATA8202 is a UHF ASK/FSK transparent receiver IC with low power consumption
supplied in a small QFN24 package (body 5 mm × 5 mm, pitch 0.65 mm). ATA8202 is used in
the 433 MHz to 435 MHz band of operation, and ATA8201 in 313 MHz to 317 MHz.
For improved image rejection and selectivity, the IF frequency is fixed to 440 kHz. The IF block
uses an 8th-order band pass yielding a receive bandwidth of 420 kHz. This enables the use of
the receiver in both SAW- and PLL-based transmitter systems utilizing various types of data-bit
encoding such as pulse width modulation, Manchester modulation, variable pulse modulation,
pulse position modulation, and NRZ. Prevailing encryption protocols such as Keeloq® are easily
supported due to the receiver’s ability to hold the current data slicer threshold for up to 52 ms
when incoming RF telegrams contain a blanking interval. This feature eliminates erroneous
noise from appearing on the demodulated data output pin, and simplifies software decoding
algorithms. The decoding of the data stream must be carried out by a connected microcontroller
device. Because of the highly integrated design, the only required RF components are for the
purpose of receiver antenna matching.
ATA8201 and ATA8202 support Manchester bit rates of 1 Kbit/s to 10 Kbits/s in ASK and 1 Kbit/s
to 20 Kbits/s in FSK mode. The four discrete bit rate passbands are selectable and cover
1.0 Kbit/s to 2.5 Kbits/s, 2.0 Kbits/s to 5.0 Kbits/s, 4.0 Kbits/s to 10.0 Kbits/s, and 8.0 Kbits/s to
10.0 Kbits/s or 20.0 Kbits/s (for ASK or FSK, respectively). The receiver contains an RSSI output
to provide an indication of received signal strength and a SENSE input to allow the customer to
select a threshold below which the DATA signal is gated off. ASK/FSK and bit rate ranges are
selected by the connected microcontroller device via pins ASK_NFSK, BR0, and BR1.
Figure 1-1.
System Block Diagram
ATA8201/ATA8202
Digital Control
Logic
Antenna
Power
Supply
RF Receiver
Microcontroller
4 ... 8
(LNA, Mixer,
VCO, PLL,
IF Filter,
RSSI Amp.,
Demodulator)
Microcontroller
Interface
XTO
3
4971C–INDCO–04/09
Table 1-1.
RX
BR0
BR1
ASK_NFSK
TEST1
2
17
RSSI
CLK_OUT
3
16
SENSE_CTRL
CLK_OUT_CTRL1
4
15
SENSE
CLK_OUT_CTRL0
5
14
LNA_IN
ENABLE
6
TEST3
LNA_GND
GND
VS3V_AVCC
8
VS5V
7
13
9 10 11 12
DVCC
24 23 22 21 20 19
18
XTAL1
1
XTAL2
TEST2
Pin Description
Pin
Symbol
Function
1
TEST2
Test pin, during operation at GND
2
TEST1
Test pin, during operation at GND
3
CLK_OUT
4
CLK_OUT_CTRL1
Input to control CLK_OUT (MSB)
5
CLK_OUT_CTRL0
Input to control CLK_OUT (LSB)
6
ENABLE
7
XTAL2
Reference crystal
8
XTAL1
Reference crystal
Output to clock a connected microcontroller
Input to enable the XTO
9
DVCC
Digital voltage supply blocking
10
VS5V
Power supply input for voltage range 4.5V to 5.5V
11
VS3V_AVCC
Power supply input for voltage range 2.7V to 3.3V
12
GND
13
LNA_GND
14
LNA_IN
15
SENSE
16
SENSE_CTRL
17
RSSI
18
TEST3
Ground
RF ground
RF input
Sensitivity control resistor
Sensitivity selection
Low: Normal sensitivity, High: Reduced sensitivity
Output of the RSSI amplifier
Test pin, during operation at GND
19
RX
Input to activate the receiver
20
BR0
Bit rate selection, LSB
21
BR1
Bit rate selection, MSB
22
ASK_NFSK
23
CDEM
24
DATA_OUT
GND
4
CDEM
Pinning QFN24
DATA_OUT
Figure 1-2.
FSK/ASK selection
Low: FSK, High: ASK
Capacitor to adjust the lower cut-off frequency data filter
Data output
Ground/backplane (exposed die pad)
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
Figure 1-3.
Block Diagram
ASK/FSK
Demodulator
CDEM
ASK
Power
Supply
FSK
VS3V_AVCC
VS5V
ASK/FSK
Control
ASK_NFSK
Data
Slicer
DATA_OUT
IF Amp
SENSE
SENSE_CTRL
BR0
IF Filter
BR1
GND
Standby
Logic Control
LPF
XTO
Div. by 3, 6, 12
DVCC
IF Amp
RX
CLK_OUT_CTRL1
CLK_OUT_CTRL0
CLK_OUT
RSSI
LPF
LNA_IN
PLL
(/24, /32)
XTO
ENABLE
TEST1
LNA
VCO
TEST2
LNA_GND
TEST3
XTAL2
XTAL1
5
4971C–INDCO–04/09
2. RF Receiver
As seen in Figure 1-3 on page 5, the RF receiver consists of a low-noise amplifier (LNA), a local
oscillator, and the signal processing part with mixer, IF filter, IF amplifier with analog RSSI,
FSK/ASK demodulator, data filter, and data slicer.
In receive mode, the LNA pre-amplifies the received signal which is converted down to a
440-kHz intermediate frequency (IF), then filtered and amplified before it is fed into an FSK/ASK
demodulator, data filter, and data slicer. The received signal strength indicator (RSSI) signal is
available at the pin RSSI.
2.1
Low-IF Receiver
The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking,
selectivity, supply voltage, and supply current specification needed to design, e.g., an industrial/
aftermarket integrated receiver for RKE and TPM systems. A benefit of the integrated receive filter is that no external components needed.
At 315 MHz, the ATA8201 receiver (433.92 MHz for the ATA8202 receiver) has a typical system
noise figure of 6.0 dB (7.0 dB), a system I1dBCP of –31 dBm (–30 dBm), and a system IIP3 of
–24 dBm (–23 dBm). The signal path is linear for out-of-band disturbers up to the I1dBCP and
hence there is no AGC or switching of the LNA needed, and a better blocking performance is
achieved. This receiver uses an IF (intermediate frequency) of 440 kHz, the typical image rejection is 30 dB and the typical 3-dB IF filter bandwidth is 420 kHz (f IF = 440 kHz ± 210 kHz,
flo_IF = 230 kHz and fhi_IF = 650 kHz). The demodulator needs a signal-to-noise ratio of 8.5 dB for
10 Kbits/s Manchester with ±38 kHz frequency deviation in FSK mode, thus, the resulting sensitivity at 315 MHz (433.92 MHz) is typically –105 dBm (–104 dBm).
Due to the low phase noise and spurs of the synthesizer together with the 8th-order integrated IF
filter, the receiver has a better selectivity and blocking performance than more complex double
superhet receivers, without using external components and without numerous spurious receiving frequencies.
A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct
conversion receivers where every pulse or amplitude modulated signal (especially the signals
from TDMA systems like GSM) demodulates to the receiving signal band at second-order
non-linearities.
6
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
2.2
Input Matching at LNA_IN
The measured input impedances as well as the values of a parallel equivalent circuit of these
impedances can be seen in Table 2-1. The highest sensitivity is achieved with power matching
of these impedances to the source impedance.
Table 2-1.
Measured Input Impedances of the LNA_IN Pin
fRF [MHz]
ZIn(RF_IN) [Ω]
RIn_p//CIn_p [pF]
315
(72.4 – j298)
1300Ω//1.60
433.92
(55 – j216)
900Ω//1.60
The matching of the LNA input to 50Ω is done using the circuit shown in Figure 2-1 and the values of the matching elements given in Table 2-2. The reflection coefficients were always
≤ –10 dB. Note that value changes of C1 and L1 may be necessary to compensate individual
board layout parasitics. The measured typical FSK and ASK Manchester-code sensitivities with
a bit error rate (BER) of 10–3 are shown in Table 2-3 and Table 2-4 on page 8. These measurements were done with wire-wound inductors having quality factors reported in Table 2-2,
resulting in estimated matching losses of 0.8 dB at 315 MHz and 433.92 MHz. These losses can
be estimated when calculating the parallel equivalent resistance of the inductor with
Rloss = 2 × π × f × L × QL and the matching loss with 10 log(1+RIn_p / Rloss).
Figure 2-1.
Input Matching to 50Ω
RFIN
ATA8201/ATA8202
C1
14
LNA_IN
L1
Table 2-2.
Input Matching to 50Ω
fRF [MHz]
C1 [pF]
L1 [nH]
QL1
315
2.2
68
20
433.92
2.2
36
15
7
4971C–INDCO–04/09
Table 2-3.
Measured Typical Sensitivity FSK, ±38 kHz, Manchester, BER = 10–3
RF Frequency
BR_Range_0
1.0 Kbit/s
BR_Range_0
2.5 Kbits/s
BR_Range_1
5 Kbits/s
BR_Range_2
10 Kbits/s
BR_Range_3
10 Kbits/s
BR_Range_3
20 Kbits/s
315 MHz
–108 dBm
–108 dBm
–107 dBm
–105 dBm
–104 dBm
–104 dBm
433.92 MHz
–107 dBm
–107 dBm
–106 dBm
–104 dBm
–103 dBm
–103 dBm
Table 2-4.
Measured Typical Sensitivity 100% ASK, Manchester, BER = 10–3
RF Frequency
BR_Range_0
1.0 Kbit/s
BR_Range_0
2.5 Kbits/s
BR_Range_1
5 Kbits/s
BR_Range_2
10 Kbits/s
BR_Range_3
10 Kbits/s
315 MHz
–114 dBm
–114 dBm
–113 dBm
–111 dBm
–109 dBm
433.92 MHz
–113 dBm
–113 dBm
–112 dBm
–110 dBm
–108 dBm
Conditions for the sensitivity measurement:
The given sensitivity values are valid for Manchester-modulated signals. For the sensitivity measurement the distance from edge to edge must be evaluated. As can be seen in Figure 6-1 on
page 25, in a Manchester-modulated data stream, the time segments TEE and 2 × TEE occur.
To reach the specified sensitivity for the evaluation of TEE and 2 × TEE in the data stream, the
following limits should be used (TEE min, TEE max, 2 × TEE min, 2 × TEE max).
Table 2-5.
2.3
Limits for Sensitivity Measurements
Bit Rate
TEE Min
TEE Typ
TEE Max
2 × TEE Min
2 × TEE Typ
2 × TEE Max
1.0 Kbit/s
260 µs
500 µs
790 µs
800 µs
1000 µs
1340 µs
2.4 Kbits/s
110 µs
208 µs
310 µs
320 µs
416 µs
525 µs
5.0 Kbits/s
55 µs
100 µs
155 µs
160 µs
200 µs
260 µs
9.6 Kbits/s
27 µs
52 µs
78 µs
81 µs
104 µs
131 µs
Sensitivity Versus Supply Voltage, Temperature and Frequency Offset
To calculate the behavior of a transmission system, it is important to know the reduction of the
sensitivity due to several influences. The most important are frequency offset due to crystal
oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage dependency of the noise figure, and IF-filter bandwidth of the receiver. Figure 2-2 and Figure 2-3 on
page 9 show the typical sensitivity at 315 MHz, ASK, 2.4 Kbits/s and 9.6 Kbits/s, Manchester,
Figure 2-4 and Figure 2-5 on page 10 show a typical sensitivity at 315 MHz, FSK, 2.4 Kbits/s
and 9.6 Kbits/s, ±38 kHz, Manchester versus the frequency offset between transmitter and
receiver at Tamb = +25°C and supply voltage VS = VS3V_AVCC = VS5V = 3.0V.
8
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
Figure 2-2.
Measured Sensitivity (315 MHz, ASK, 2.4 Kbits/s, Manchester) Versus
Frequency Offset
Input Sensitivity (dBm) at BER < 1e-3, ATA8201, ASK, 2.4 kB/s (Manchester),
BR = 0
Input Sensitivity (dBm)
-118.00
-117.00
-116.00
3.0V/25˚C
-115.00
-114.00
-113.00
-112.00
-111.00
-110.00
-109.00
-108.00
-107.00
-106.00
-105.00
-104.00
-103.00
-300
-200
0
-100
200
100
300
delta RF (kHz) at 315 MHz
Figure 2-3.
Measured Sensitivity (315 MHz, ASK, 9.6 Kbits/s, Manchester) Versus
Frequency Offset
Input Sensitivity (dBm) at BER < 1e-3, ATA8201, ASK, 9.6 Kbits/s (Manchester),
BR = 2
Input Sensitivity (dBm)
-115.0 0
-114.0 0
-113.0 0
-112.0 0
-111.0 0
3.0V/25˚C
-110.0 0
-10 9.0 0
-10 8.0 0
-10 7.0 0
-10 6.0 0
-10 5.0 0
-10 4.0 0
-10 3.0 0
-10 2.00
-10 1.0 0
-10 0.0 0
-300
-200
-100
0
100
200
300
delta RF (kHz) at 315 MHz
9
4971C–INDCO–04/09
Figure 2-4.
Measured Sensitivity (315 MHz, FSK, 2.4 Kbits/s, ±38 kHz, Manchester) Versus
Frequency Offset
Input Sensitivity (dBm) at BER < 1e-3, ATA8201, FSK, 2.4 Kbits/s
(Manchester), BR0
Input Sensitivity (dBm)
-112.00
-111.00
-110.00
3.0V/25˚C
-109.00
-108.00
-107.00
-106.00
-105.00
-104.00
-103.00
-102.00
-101.00
-100.00
-99.00
-98.00
-300
-200
200
100
0
-100
300
delta RF (kHz) at 315 MHz
Figure 2-5.
Measured Sensitivity (315 MHz, FSK, 9.6 Kbits/s, ±38 kHz, Manchester) Versus
Frequency Offset
Input Sensitivity (dBm)
Input Sensitivity (dBm) at BER < 1e-3, ATA8201, FSK, 9.6 Kbits/s (Manchester),
BR = 2
-110.00
-109.00
-108.00
-107.00
3.0V/25˚C
-106.00
-105.00
-104.00
-103.00
-102.00
-101.00
-100.00
-99.00
-98.00
-97.00
-96.00
-95.00
-300
-200
-100
0
100
200
300
delta RF (kHz) at 315 MHz
10
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
As can be seen in Figure 2-5 on page 10, the supply voltage has almost no influence. The temperature has an influence of about ±1.0 dB, and a frequency offset of ±160 kHz also influences
by about ±1 dB. All these influences, combined with the sensitivity of a typical IC (–105 dB), are
then within a range of –103.0 dBm and –107.0 dBm over temperature, supply voltage, and frequency offset. The integrated IF filter has an additional production tolerance of ±10 kHz, hence,
a frequency offset between the receiver and the transmitter of ±160 kHz can be accepted for
XTAL and XTO tolerances.
Note:
For the demodulator used in the ATA8201/ATA8202, the tolerable frequency offset does not
change with the data frequency. Hence, the value of ±160 kHz is valid for 1 Kbit/s to 10 Kbits/s.
This small sensitivity change over supply voltage, frequency offset, and temperature is very
unusual in such a receiver. It is achieved by an internal, very fast, and automatic frequency correction in the FSK demodulator after the IF filter, which leads to a higher system margin. This
frequency correction tracks the input frequency very quickly. If, however, the input frequency
makes a larger step (for example, if the system changes between different communication partners), the receiver has to be restarted. This can be done by switching back to Standby mode
and then again to Active mode (pin RX 1 →0 →1) or by generating a positive pulse on pin
ASK_NFSK (0 →1 →0).
2.4
RX Supply Current Versus Temperature and Supply Voltage
Table 2-7 shows the typical supply current of the receiver in Active mode versus supply voltage
and temperature with VS = VS3V_AVCC = VS5V.
Table 2-6.
Table 2-7.
Measured Current in Active Mode ASK
VS = VS3V_AVCC = VS5V
3.0V
Tamb = 25°C
6.5 mA
Measured Current in Active Mode FSK
VS = VS3V_AVCC = VS5V
3.0V
Tamb = 25°C
6.7 mA
11
4971C–INDCO–04/09
2.5
Blocking, Selectivity
As can be seen in Figure 2-6 on page 12, and Figure 2-7 and Figure 2-8 on page 13, the
receiver can receive signals 3 dB higher than the sensitivity level in the presence of large blockers of –34.5 dBm or –28 dBm with small frequency offsets of ±3 MHz or ±20 MHz.
Figure 2-6, and Figure 2-7 on page 12 show the narrow-band blocking, and Figure 2-8 on page
13 shows the wide-band blocking characteristic. The measurements were done with a useful
signal of 315 MHz, FSK, 10 Kbits/s, ±38 kHz, Manchester, BR_Range2 with a level of
–105 dBm + 3 dB = –102 dBm, which is 3 dB above the sensitivity level. The figures show how
much larger than –102 dBm a continuous wave signal can be, until the BER is higher than 10–3.
The measurements were done at the 50Ω input shown in Figure 2-1 on page 7. At 3 MHz, for
example, the blocker can be 67.5 dBC higher than –102 dBm, or
–102 dBm + 67.5 dBC = –34.5 dBm.
Figure 2-6.
Close-in 3-dB Blocking Characteristic and Image Response at 315 MHz
70.0
Blocking Level (dBC)
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
Distance from Interfering to Receiving Signal (MHz)
Figure 2-7.
Narrow-band 3-dB Blocking Characteristic at 315 MHz
80.0
Blocking Level (dBC)
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
Distance from Interfering to Receiving Signal (MHz)
12
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
Figure 2-8.
Wide-band 3-dB Blocking Characteristic at 315 MHz
80.0
Blocking Level (dBC)
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
Distance from Interfering to Receiving Signal (MHz)
Table 2-8 shows the blocking performance measured relative to –102 dBm for some frequencies. Note that sometimes the blocking is measured relative to the sensitivity level 104 dBm
(denoted dBS), instead of the carrier –102 dBm (denoted dBC).
Table 2-8.
Blocking 3 dB Above Sensitivity Level With BER < 10–3
Frequency Offset
Blocking Level
Blocking
+1.5 MHz
–44.5 dBm
57.5 dBC, 60.5 dBS
–1.5 MHz
–44.5 dBm
57.5 dBC, 60.5 dBS
+2 MHz
–39.0 dBm
63 dBC, 66 dBS
–2 MHz
–36.0 dBm
66 dBC, 69 dBS
+3 MHz
–34.5 dBm
67.5 dBC, 70.5 dBS
–3 MHz
–34.5 dBm
67.5 dBC, 70.5 dBS
+20 MHz
–28.0 dBm
74 dBC, 77 dBS
–20 MHz
–28.0 dBm
74 dBC, 77 dBS
The ATA8201/ATA8202 can also receive FSK and ASK modulated signals if they are much
higher than the I1dBCP. It can typically receive useful signals at –10 dBm. This is often referred
to as the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and is
95 dB for 10 Kbits/s Manchester (FSK). This value is useful if the transmitter and receiver are
very close to each other.
13
4971C–INDCO–04/09
2.6
In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer
If a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the
performance of a receiver strongly depends on the circuits after the IF filter. Hence, the demodulator, data filter, and data slicer are important.
The data filter of the ATA8201/ATA8202 functions also as a quasi-peak detector. This results in a
good suppression of above mentioned disturbers and exhibits a good carrier-to-noise performance. The required useful-signal-to-disturbing-signal ratio, at a BER of 10–3, is less than 14 dB
in ASK mode and less than 3 dB (BR_Range_0 to BR_Range_2) and 6 dB (BR_Range_3) in
FSK mode. Due to the many different possible waveforms, these numbers are measured for the
signal, as well as for disturbers, with peak amplitude values. Note that these values are
worst-case values and are valid for any type of modulation and modulating frequency of the disturbing signal, as well as for the receiving signal. For many combinations, lower
carrier-to-disturbing-signal ratios are needed.
2.7
RSSI Output
The output voltage of the pin RSSI is an analog voltage, proportional to the input power level.
Using the RSSI output signal, the signal strength of different transmitters can be distinguished.
The usable dynamic range of the RSSI amplifier is 65 dB, the input power range P(RFIN) is
–110 dBm to –45 dBm, and the gain is 15 mV/dB. Figure 2-9 shows the RSSI characteristic of a
typical device at 315 MHz with VS3V_AVCC = VS5V = 3V and Tamb = 25°C with a matched
input as shown in Table 2-2 and Figure 2-1 on page 7. At 433.92 MHz, 1 dB more signal level is
needed for the same RSSI results.
Figure 2-9.
Typical RSSI Characteristic at 315 MHz Versus Temperature and Supply Voltage
1.7
1.6
3V, 25˚C
1.5
1.4
V_RSSI (V)
1.3
1.2
max: +9 dBm
1.1
1.0
0.9
0.8
min: -9 dBm
0.7
0.6
0.5
0.4
-13 0 -12 0 -110 -10 0 -9 0
-8 0
-70
-6 0
-50
-4 0
-3 0
-2 0
-10
Pin (dBm)
As can be seen in Figure 2-9 on page 14, for single devices there is a variance over temperature
and supply voltage range of ±3 dB. The total variance over production, temperature, and supply
voltage range is ±9 dB.
14
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
2.8
Frequency Synthesizer
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is divided by the factor 24 (ATA8201) or
32 (ATA8202). The divided frequency is compared to fXTO by the phase frequency detector. The
current output of the phase frequency detector is connected to the fully integrated loop filter, and
thereby generates the control voltage for the VCO. By means of that configuration, the VCO is
controlled in a way, such that fLO / 24 (fLO / 32) is equal to fXTO. If fLO is determined, fXTO can be
calculated using the following formula: fXTO = fLO / 24 (fXTO = fLO / 32). The synthesizer has a
phase noise of –130 dBC/Hz at 3 MHz and spurs of –75 dBC.
Care must be taken with the harmonics of the CLK output signal, as well as with the harmonics
produced by a microprocessor clocked using the signal, as these harmonics can disturb the
reception of signals.
3. XTO
The XTO is an amplitude-regulated Pierce oscillator type with external load capacitances
(2 × 16 pF). Due to additional internal and board parasitics (CP) of approximately 2 pF on each
side, the load capacitance amounts to 2 × 18 pF (9 pF total).
The XTO oscillation frequency fXTO is the reference frequency for the integer-N synthesizer.
When designing the system in terms of receiving and transmitting frequency offset, the accuracy
of the crystal and XTO have to be considered.
The XTO’s additional pulling (including the RM tolerance) is only ±5 ppm. The XTAL versus temperature, aging, and tolerances is then the main source of frequency error in the local oscillator.
The XTO frequency depends on XTAL properties and the load capacitances CL1,2 at pin XTAL1
and XTAL2. The pulling (p) of fXTO from the nominal fXTAL is calculated using the following formula:
Cm
C LN – C L
-6
p = -------- × --------------------------------------------------------------- × 10 ppm
2
( C O + C LN ) × ( C O + C L )
Cm, the crystal’s motional capacitance; C0, the shunt capacitance; and CLN, the nominal load
capacitance of the XTAL, are found in the datasheet. CL is the total actual load capacitance of
the crystal in the circuit, and consists of CL1 and CL2 connected in series.
Figure 3-1.
Crystal Equivalent Circuit
Crystal Equivalent Circuit
C0
XTAL
Lm
CL1
CL2
Cm
Rm
CL = CL1 × CL2/ (CL1 + CL2)
15
4971C–INDCO–04/09
With C m ≤ 10 fF, C 0 ≥ 1.0 pF, C LN = 9 pF and C L1,2 = 16 pF ±1%, the pulling amounts to
P ≤ ±1 ppm.
The C0 of the XTAL has to be lower than CLmin / 2 = 7.9 pF for a Pierce oscillator type in order to
not enter the steep region of pulling versus load capacitance where there is risk of an unstable
oscillation.
To ensure proper start-up behavior, the small signal gain and the negative resistance provided
by this XTO at start is very large. For example, oscillation starts up even in the worst case with a
crystal series resistance of 1.5 kΩ at C0 ≤ 2.2 pF with this XTO. The negative resistance is
approximately given by
⎧ Z 1 × Z 3 + Z 2 × Z 3 + Z 1 × Z 3 × gm ⎫
Re {Zxtocore } = Re ⎨ ----------------------------------------------------------------------------------------- ⎬
⎩ Z 1 + Z 2 + Z 3 + Z 1 × Z 2 × gm ⎭
with Z1 and Z2 as complex impedances at pins XTAL1 and XTAL2, hence
Z1 = –j / (2 × p × fXTO × CL1) + 5Ω and Z2 = –j / (2 × p × fXTO × CL2) + 5Ω.
Z3 consists of crystal C0 in parallel with an internal 110-kΩ resistor, hence
Z3 = –j / (2 × p × fXTO × C0) / 110 kΩ, gm is the internal transconductance between XTAL1 and
XTAL2, with typically 20 mS at 25°C.
With fXTO = 13.5 MHz, gm = 20 mS, CL = 9 pF, and C0 = 2.2 pF, this results in a negative resistance of about 2 kΩ. The worst case for technology, supply voltage, and temperature variations
is then always higher than 1.4 kΩ for C0 ≤ 2.2 pF.
Due to the large gain at start, the XTO is able to meet a very low start-up time. The oscillation
start-up time can be estimated with the time constant τ .
2
τ = -----------------------------------------------------------------------------------------------------------------2
2
4 × π × f XTAL × C m × ( Re ( Z xtocore ) + R m )
After 10τ to 20τ , an amplitude detector detects the oscillation amplitude and sets XTO_OK to
High if the amplitude is large enough; this activates the CLK_OUT output if it is enabled via the
pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that the necessary conditions of the
DVCC voltage also have to be fulfilled.
It is recommended to use a crystal with C m = 3.0 fF to 10 fF, C LN = 9 pF, R m < 120Ω and
C0 = 1.0 pF to 2.2 pF.
Lower values of Cm can be used, slightly increasing the start-up time. Lower values of C0 or
higher values of Cm (up to 15 fF) can also be used, with only little influence on pulling.
16
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
Figure 3-2.
XTO Block Diagram
CL1
XTAL1
CL2
XTAL2
CLK_OUT_CTRL0
CLK_OUT_CTRL1
CLK_OUT
&
fFXTO
Divider
/3, /6, /12
XTO_OK
Amplitude
Detector
Divider
/16
fDCLK
The relationship between fXTO and the fRF is shown in Table 3-1.
Table 3-1.
Calculation of fRF
Frequency [MHz]
fXTO [MHz]
fRF
433.92 (ATA8202)
13.57375
fXTO × 32 – 440 kHz
315.0 (ATA8201)
13.1433
fXTO × 24 – 440 kHz
Attention must be paid to the harmonics of the CLK_OUT output signal fCLK_OUT as well as to the
harmonics produced by an microprocessor clocked with it, since these harmonics can disturb
the reception of signals if they get to the RF input. If the CLK_OUT signal is used, it must be
carefully laid out on the application PCB. The supply voltage of the microcontroller must also be
carefully blocked.
17
4971C–INDCO–04/09
3.1
Pin CLK_OUT
Pin CLK_OUT is an output to clock a connected microcontroller. The clock is available in
Standby and Active modes. The frequency f C L K _ O U T can be adjusted via the pins
CLK_OUT_CTRL0 and CLK_OUT_CTRL1, and is calculated as follows:
Table 3-2.
Setting of fCLK_OUT
CLK_OUT_CTRL1
CLK_OUT_CTRL0
Function
0
0
Clock on pin CLK_OUT is switched off
(Low level on pin CLK_OUT)
0
1
fCLK_OUT = fXTO / 3
1
0
fCLK_OUT = fXTO / 6
1
1
fCLK_OUT = fXTO / 12
The signal at CLK_OUT output has a nominal 50% duty cycle. To save current, it is recommended that CLK_OUT be switched off during Standby mode.
3.2
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry is derived from one clock. As seen in Figure 3-2 on
page 17, this clock cycle, TDCLK, is derived from the crystal oscillator (XTO) in combination with a
divider.
f XTO
f DCLK = ---------16
TDCLK controls the following application relevant parameters:
- Debouncing of the data signal stream
- Start-up time of the RX signal path
The start-up time and the debounce characteristic depend on the selected bit rate range
(BR_Range) which is defined by pins BR0 and BR1. The clock cycle TXDCLK is defined by the following formulas for further reference:
BR_Range ⇒
18
BR_Range 0: TXDCLK = 8 ×
BR_Range 1: TXDCLK = 4 ×
BR_Range 2: TXDCLK = 2 ×
BR_Range 3: TXDCLK = 1 ×
TDCLK
TDCLK
TDCLK
TDCLK
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
4. Sensitivity Reduction
The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red.
VTh_red is determined by the value of the external resistor RSense. RSense is connected between
the pins SENSE and VS3V_AVCC (see Figure 10-1 on page 29). The output of the comparator
is fed into the digital control logic. By this means, it is possible to operate the receiver at a lower
sensitivity.
If the level on input pin SENSE_CTRL is low, the receiver operates at full sensitivity.
If the level on input pin SENSE_CTRL is high, the receiver operates at a lower sensitivity. The
reduced sensitivity is defined by the value of R Sense , the maximum sensitivity by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the
output of the RSSI amplifier.
Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This
matching is illustrated in Figure 2-1 on page 7 and exhibits the best possible sensitivity.
If the sensitivity reduction feature is not used, pin SENSE can be left open, pin SENSE_CTRL
must be set to GND.
To operate with reduced sensitivity, pin SENSE_CTRL must be set to high before the RX signal
path will be enabled by setting pin RX to high (see Figure 4-1 on page 20). As long as the RSSI
level is lower than VTh_red (defined by the external resistor RSense) no data stream is available on
pin DATA_OUT (low level on pin DATA_OUT). An internal RS flip-flop will be set to high the first
time the RSSI voltage crosses VTh_red, and from then on the data stream will be available on pin
DATA_OUT. From then on the receiver also works with full sensitivity. This makes sure that a
telegram will not be interrupted if the RSSI level varies during the transmission. The RS flip-flop
can be set back, and thus the receiver switched back to reduced sensitivity, by generating a positive pulse on pin ASK_NFSK (see Figure 4-2 on page 20). In FSK mode, operating with reduced
sensitivity follows the same way.
19
4971C–INDCO–04/09
Figure 4-1.
Reduced Sensitivity Active
ENABLE
ASK_NFSK
SENSE_CTRL
RX
VTh_red
RSSI
tStartup_PLL tStartup_Sig_Proc
DATA_OUT
Figure 4-2.
Restart Reduced Sensitivity
ENABLE
ASK_NFSK
SENSE_CTRL
RX
VTh_red
RSSI
tStartup_Sig_Proc
DATA_OUT
20
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
5. Power Supply
Figure 5-1.
Power Supply
VS3V_AVCC
SW_DVCC
IN
VS5V
V_REG
3.0V typ.
OUT
DVCC
EN
RX
The supply voltage range of the ATA8201/ATA8202 is 2.7V to 3.3V or 4.5V to 5.5V.
Pin VS3V_AVCC is the supply voltage input for the range 2.7V to 3.3V, and is used in battery
applications using a single lithium 3V cell. Pin VS5V is the voltage input for the range 4.5V to
5.5V (car applications) in this case the voltage regulator V_REG regulates VS3V_AVCC to typically 3.0V. If the voltage regulator is active, a blocking capacitor of 2.2 µF has to be connected to
VS3V_AVCC (see Figure 10-1 on page 29).
DVCC is the internal operating voltage of the digital control logic and is fed via the switch
SW_DVCC by VS3V_AVCC. DVCC must be blocked on pin DVCC with 68 nF (see Figure 9-1
on page 28 and Figure 10-1 on page 29).
Pin RX is the input to activate the RX signal processing and set the receiver to Active mode.
5.1
OFF Mode
A low level on pin RX and ENABLE will set the receiver to OFF mode (low power mode). In this
mode, the crystal oscillator is shut down and no clock is available on pin CLK_OUT. The
receiver is not sensitive to a transmitter signal in this mode.
Table 5-1.
5.2
Standby Mode
RX
ENABLE
Function
0
0
OFF mode
Standby Mode
The receiver activates the Standby mode if pin ENABLE is set to “1”.
In Standby mode, the XTO is running and the clock on pin CLK_OUT is available after the
start-up time of the XTO ha s elapsed (dependent on pin CLK_OUT_CTRL0 an d
CLK_OUT_CTRL1). During Standby mode, the receiver is not sensitive to a transmitter signal.
In Standby mode, the RX signal path is disabled and the power consumption IStandby is typically
50 µA (CLK_OUT output off, VS3V_AVCC = VS5V = 3V). The exact value of this current is
strongly dependent on the application and the exact operation mode, therefore check the section “Electrical Characteristics: General” on page 30 for the appropriate application case.
21
4971C–INDCO–04/09
Table 5-2.
Figure 5-2.
Standby Mode
RX
ENABLE
Function
0
1
Standby mode
Standby Mode (CLK_OUT_CTRL0 or CLK_OUT_CTRL1 = 1)
CLK_OUT
tXTO_Startup
ENABLE
Standby Mode
5.3
Active Mode
The Active mode is enabled by setting the level on pin RX to high. In Active mode, the RX signal
path is enabled and if a valid signal is present it will be transferred to the connected
microcontroller.
Table 5-3.
Active Mode
RX
ENABLE
Function
1
1
Active mode
During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing
circuit starts up (TStartup_Sig_Proc). After the start-up time, all circuits are in stable condition and
ready to receive. The duration of the start-up sequence depends on the selected bit rate range.
Figure 5-3.
Active Mode
CLK_OUT
ENABLE
RX
DATA_OUT
DATA_OUT valid
IStandby
Standby Mode
22
tStartup_PLL
tStartup_Sig_Proc
IStartup_PLL
IActive
Startup
IActive
Active Mode
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
Table 5-4.
Start-up Time
ATA8202 (433.92 MHz)
BR1
BR0
0
0
0
1
1
0
1
1
Table 5-5.
ASK_NFSK
0
1
TStartup_PLL
TStartup_Sig_Proc
ATA8201 (315 MHz)
TStartup_PLL
TStartup_Sig_Proc
1096 µs
644 µs
261 µs
417 µs
1132 µs
665 µs
269 µs
431 µs
304 µs
324 µs
Modulation Scheme
RFIN at Pin LNA_IN
Level at Pin DATA_OUT
fFSK_H
1
fFSK_L
0
fASK on
1
fASK off
0
23
4971C–INDCO–04/09
6. Bit Rate Ranges
Configuration of the bit rate ranges is carried out via the two pins BR0 and BR1. The microcontroller uses these two interface lines to set the corner frequencies of the band-pass data filter.
Switching the bit rate ranges while the RF front end is in Active mode can be done on the fly and
will not take longer than 100 µs if done while remaining in either ASK or FSK mode. If the modulation scheme is changed at the same time, the switching time is (TStartup_Sig_Proc, see Figure 7-1
on page 26). Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sensitivity of the receiver, edge-to-edge transition times of incoming data should not be less than the
minimum for the selected BR_Range.
Table 6-1.
BR Ranges ASK
Minimum Edge-to-edge
Edge-to-edge Time Period TEE of
Time Period TEE of the Data the Data Signal During the Start-up
Period(3)
Signal(2)
BR1
BR0
BR_Range
Recommended Bit Rate
(Manchester)(1)
0
0
BR_Range0
1.0 Kbit/s to 2.5 Kbits/s
200 µs
200 µs to 500 µs
0
1
BR_Range1
2.0 Kbits/s to 5.0 Kbits/s
100 µs
100 µs to 250 µs
1
0
BR_Range2
4.0 Kbits/s to 10.0 Kbits/s
50 µs
50 µs to 125 µs
1
1
BR_Range3
8.0 Kbits/s to 10.0 Kbits/s
50 µs
50 µs to 62.5 µs
Table 6-2.
BR Ranges FSK
Recommended Bit Rate
(Manchester)(1)
Minimum Edge-to-edge
Edge-to-edge Time Period TEE of
Time Period TEE of the Data the Data Signal During the Start-up
Signal(2)
Period(3)
BR1
BR0
BR_Range
0
0
BR_Range0
1.0 Kbit/s to 2.5 Kbits/s
200 µs
200 µs to 500 µs
0
1
BR_Range1
2.0 Kbits/s to 5.0 Kbits/s
100 µs
100 µs to 250 µs
1
0
BR_Range2
4.0 Kbits/s to 10.0 Kbits/s
50 µs
50 µs to 125 µs
1
1
BR_Range3
8.0 Kbits/s to 20.0 Kbits/s
25 µs
25 µs to 62.5 µs
Note:
If during the start-up period (TStartup_PLL + TStartup_Sig_Proc) there is no RF signal, the data filter settles to the noise floor, leading
to noise on pin DATA_OUT.
Notes:
1. As can be seen, a bit stream of, for example, 2.5 Kbits/s can be received in BR_Range0 and BR_Range1 (overlapping
BR_Ranges). To get the full sensitivity, always use the lowest possible BR_Range (here, BR_Range0). The advantage in
the next higher BR_Range (BR_Range1) is the shorter start-up period, meaning lower current consumption during Polling
mode. Thus, it is a decision between sensitivity and current consumption.
2. The receiver is also capable of receiving non-Manchester-modulated signals, such as PWM, PPM, VPWM, NRZ. In ASK
mode, the header and blanking periods occurring in Keeloq-like protocols (up to 52 ms) are supported.
3. To ensure an accurate settling of the data filter during the start-up period (TStartup_PLL + TStartup_Sig_Proc), the edge-to-edge
time TEE of the data signal (preamble) must be inside the given limits during this period.
24
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
Figure 6-1.
Examples of Supported Modulation Formats
TEE
MAN:
TEE
Logic 0
TEE
TEE
TEE
Logic 1
TEE
PWM:
TEE
TEE
TEE
Logic 0
TEE
Logic 1
Logic 0
TEE
VPWM:
Logic 1
TEE
TEE
On Transition Low to High
Logic 0
Logic 1
TEE
TEE
TEE
On Transition High to Low
TEE
PPM:
TEE
TEE
Logic 0
TEE
Figure 6-2.
TEE
Logic 1
TEE
NRZ:
TEE
TEE
Logic 0
Logic 1
Supported Header and Blanking Periods
Preamble
Header
Data Burst
Guard Time
Data Burst
25
4971C–INDCO–04/09
7. ASK_NFSK
The ASK_NFSK pin allows the microcontroller to rapidly switch the RF front end between
demodulation modes. A logic 1 on this pin selects ASK mode, and a logic 0 FSK mode. The time
to change modes (TStartup_Sig_Proc) depends on the bit rate range being selected (not current bit
rate range) and is given in Table 5-4 on page 23. This response time is specified for applications
that require an ASK preamble followed by FSK data (for typical TPM applications). During
TStartup_Sig_Proc, the level on pin DATA_OUT is low.
Figure 7-1.
ASK Preamble 2.4 Kbits/s followed by FSK Data 9.6 Kbits/s
ENABLE
RX
BR1
BR0
ASK_NFSK
DATA_OUT
Data valid BR0
Data valid BR3
TStartup_Sig_Proc
26
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
8. Polling Current Calculation
Figure 8-1.
Polling Cycle
ENABLE
ISupply
IStartup_PLL
IStartup_PLL
RX
IActive
IStandby
IActive
IStandby
TBitcheck (= 1 / Signal_Bitrate (average)
TStartup_Sig_Proc (Startup Signal Processing)
TStartup_PLL (Startup RF-PLL)
In an industrial or aftermarket RKE and TPM system, the average chip current in Polling mode,
IPolling, is an important parameter. The polling period must be controlled by the connected microcontroller via the pins ENABLE and RX. The polling current can be calculated as follows:
I Polling = (T Startup_PLL / T Polling_Period ) × I Startup_PLL + (T Startup_Sig_Proc / T Polling_Period ) × I Active +
(T Bitcheck / T Polling_Period ) × I Active + (T Polling_Period – T Startup_PLL – T Startup_Sig_Proc – T Bitcheck ) /
TPolling_Period × IStandby
TStartup_PLL:
TStartup_Sig_Proc:
TBitcheck:
TPolling_Period:
IStartup_PLL:
IActive:
IStandby:
Example:-
depends on 315 MHz/433.92 MHz application.
depends on 315 MHz/433.92 MHz application and the selected bit
rate range.
depends on the signal bit rate (1 / Signal_Bit_Rate).
depends on the transmitter telegram (preburst).
depends on 3V or 5V application and the setting of pin CLK_OUT.
depends on 3V or 5V application, ASK or FSK mode and the setting of
pin CLK_OUT.
depends on 3V or 5V application and the setting of pin CLK_OUT.
315-MHz application (ATA8201), bit rate: 9.6 Kbits/s, TPolling_Period = 8 ms
--> TStartup_PLL
=
269 µs
=
324 µs
(Bit Rate Range 3)
--> TStartup_Sig_Proc
--> TBitcheck
=
104 µs
3V application; ASK mode, CLK_OUT disabled
--> IStartup_PLL
=
4.5 mA
--> IActive
=
6.5 mA
--> IStandby
=
0.05 mA
--> IPolling = 0.545 mA
27
4971C–INDCO–04/09
9. 3V Application
Figure 9-1.
3V Application
RX
BR0
BR1
ASK_NFSK
CDEM
TEST2
output
TEST1
output
CLK_OUT
output
CLK_OUT_CTRL1
SENSE
input
CLK_OUT_CTRL0
LNA_IN
TEST3
RSSI
ATA8201/
ATA8202
SENSE_CTRL
LNA_GND
GND
VS5V
XTAL2
VCC
DVCC
ENABLE
VS3V_AVCC
2.2 pF
output
VSS
DATA_OUT
output
XTAL1
Microcontroller
15 nF
RFIN
68 nH/36 nH
315 MHz/433.92 MHz
68 nF
18 pF
18 pF
68 nF
VCC = 2.7V to 3.3V
Note:
28
Paddle (backplane) must be connected to GND
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
10. 5V Application
Figure 10-1. 5V Application With Reduced/Full Sensitivity
RX
BR0
BR1
ASK_NFSK
TEST2
output
TEST1
output
CLK_OUT
output
CLK_OUT_CTRL1
SENSE
input
CLK_OUT_CTRL0
LNA_IN
TEST3
RSSI
ATA8201/
ATA8202
SENSE_CTRL
RSense
LNA_GND
68 nH/36 nH
315 MHz/433.92 MHz
68 nF
18 pF
RFIN
GND
VS5V
XTAL2
VCC
DVCC
ENABLE
VS3V_AVCC
2.2 pF
output
VSS
CDEM
output
XTAL1
Microcontroller
output
DATA_OUT
15 nF
18 pF
2.2 µF
68 nF
VCC = 4.5V to 5.5V
Note:
Paddle (backplane) must be connected to GND
29
4971C–INDCO–04/09
11. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Junction temperature
Tj
Storage temperature
Tstg
Ambient temperature
Tamb
Supply voltage VS5V
VS
Min.
Max.
Unit
+150
°C
–55
+125
°C
–40
+85
°C
+6
V
ESD (Human Body Model ESD S 5.1)
every pin
HBM
–4
+4
kV
ESD (Machine Model JEDEC A115A)
every pin
MM
–200
+200
V
ESD (Field Induced Charge Device Model ESD
STM 5.3.1-1999) every pin
FCDM
–500
+500
V
Maximum input level, input matched to 50Ω
Pin_max
0
dBm
12. Thermal Resistance
Parameters
Symbol
Value
Unit
RthJA
25
K/W
Junction ambient
13. Electrical Characteristics: General
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No. Parameters
1
1.1
2
2.1
2.2
2.3
Test Conditions
Pin(1)
Symbol
VVS3V_AVCC = VVS5V ≤ 3V
VVS5V = 5V
CLK_OUT disabled
10, 11
10
ISOFF
ATA8201
14
fRF
ATA8202
14
fRF
XTO running
VVS3V_AVCC = VVS5V ≤ 3V
CLK_OUT disabled
10,11
IStandby
XTO running
VVS5V = 5V
CLK_OUT disabled
10,11
Min.
Typ.
Max.
Unit
Type*
4
4
µA
µA
A
A
313
317
MHz
A
433
435
MHz
A
50
100
µA
A
IStandby
50
100
µA
A
TXTO_Startup
0.3
ms
A
OFF Mode
Supply current in OFF
mode
Standby Mode
RF operating frequency
range
Supply current
Standby mode
System start-up time
XTO startup
XTAL: Cm = 5 fF,
C0 = 1.8 pF, Rm = 15Ω
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
30
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component
values as in Table 2-2 on page 7 (RFIN).
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No. Parameters
2.4
3
3.1
3.2
Test Conditions
Pin(1)
From Standby mode to
Active mode
Active mode start-up time BR_Range_3
ATA5745
ATA5746
Symbol
Min.
Typ.
TStartup_PLL +
TStartup_Sig_Proc
Max.
Unit
565
593
µs
µs
Type*
A
Active Mode
Supply current Active
mode
Supply current Polling
mode
VVS3V_AVCC = VVS5V = 3V
ASK mode
CLK_OUT disabled
SENSE_CTRL = 0
10,11
IActive
6.5
mA
A
VVS3V_AVCC = VVS5V = 3V
FSK mode
CLK_OUT disabled
SENSE_CTRL = 0
10,11
IActive
6.7
mA
A
VVS5V = 5V
ASK mode
CLK_OUT disabled
SENSE_CTRL = 0
10
IActive
6.7
mA
A
VVS5V = 5V
FSK mode
CLK_OUT disabled
SENSE_CTRL = 0
10
IActive
6.9
mA
A
10,11
IPolling
545
µA
C
VVS3V_AVCC = VVS5V = 3V
TPolling_Period = 8 ms
BR_Range_3, ASK mode,
CLK_OUT disabled
Data rate = 9.6 Kbits/s
FSK deviation
fDEV = ±38 kHz
BER = 10–3
Tamb = 25°C
3.3
Input sensitivity FSK
fRF = 315 MHz
Bit rate 9.6 Kbits/s BR2
(14)
PREF_FSK
–103
–105
–106.5
dBm
B
Bit rate 2.4 Kbits/s BR0
(14)
PREF_FSK
–106
–108
–109.5
dBm
B
Bit rate 9.6 Kbits/s BR2
(14)
PREF_FSK
–101
dBm
B
Bit rate 2.4 Kbits/s BR0
(14)
PREF_FSK
–104
dBm
B
Bit rate 9.6 Kbits/s BR2
(14)
PREF_ASK
–109
–111
–112.5
dBm
B
Bit rate 2.4 Kbits/s BR0
(14)
PREF_ASK
–112
–114
–115.5
dBm
B
FSK deviation ±18 kHz to
±50 kHz
3.4
Input sensitivity ASK
fRF = 315 MHz
ASK 100% level of carrier,
BER = 10–3
Tamb = 25°C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component
values as in Table 2-2 on page 7 (RFIN).
31
4971C–INDCO–04/09
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
fRF = 315 MHz to
fRF = 433.92 MHz
P = PREF_ASK + ΔPREF1
P = PREF_FSK + ΔPREF1
3.5
Sensitivity change at
fRF = 433.92 MHz
compared to
fRF = 315 MHz
3.6
FSK fDEV = ±38 kHz
ΔfOFFSET ≤ ±160 kHz
Sensitivity change versus ASK 100%
ΔfOFFSET ≤ ±160 kHz
temperature, supply
P = PREF_ASK + ΔPREF1 +
voltage and frequency
ΔPREF2
offset
P = PREF_FSK + ΔPREF1 +
ΔPREF2
Pin(1)
Symbol
(14)
ΔPREF1
(14)
ΔPREF2
RSense connected from
pin SENSE to
pin VS3V_AVCC
Reduced sensitivity
3.7
3.8
3.9
Typ.
Max.
+1
+4.5
Unit
Type*
dB
B
–1.5
B
dBm
(peak
level)
PRef_Red
RSense = 62 kΩ
fin = 433.92 MHz
–76
dBm
C
RSense = 82 kΩ
fin = 433.92 MHz
–88
dBm
C
RSense = 62 kΩ
fin = 315 MHz
–76
dBm
C
RSense = 82 kΩ
fin = 315 MHz
–88
dBm
C
Reduced sensitivity
variation over full
operating range
RSense = 62 kΩ
RSense = 82 kΩ
PRed = PRef_Red + PΔRed
Maximum frequency
offset in FSK mode
Maximum frequency
difference of fRF between
receiver and transmitter in
FSK mode (fRF is the
center frequency of the
FSK signal with
fBIT = 10 Kbits/s
fDEV = ±38 kHz
Supported FSK
frequency deviation
3.10 System noise figure
Min.
ΔPRed
–10
+10
dB
(14)
ΔfOFFSET
–160
+160
kHz
B
With up to 2 dB
loss of sensitivity.
Note that the tolerable
frequency offset is 12 kHz
lower for fDEV = ±50 kHz
than for fDEV = ±38 kHz,
hence,
ΔfOFFSET ≤ ±148 kHz
(14)
fDEV
±18
±38
±50
kHz
B
fRF = 315 MHz
(14)
NF
6.0
9
dB
B
fRF = 433.92 MHz
(14)
NF
7.0
10
dB
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
32
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component
values as in Table 2-2 on page 7 (RFIN).
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No. Parameters
3.11 Intermediate frequency
3.12 System bandwidth
System out-band
3.13 3rd-order input intercept
point
3.14
System outband input
1-dB compression point
3.15 LNA input impedance
3.16
Maximum peak RF input
level, ASK and FSK
3.17 LO spurs at LNA_IN
3.18 Image rejection
Pin(1)
Unit
Type*
fRF = 433.92 MHz
fIF
440
kHz
A
fRF = 315 MHz
fIF
440
kHz
A
Test Conditions
Symbol
Min.
Typ.
Max.
3 dB bandwidth
This value is for
information only!
Note that for crystal and
system frequency offset
calculations, ΔfOFFSET
must be used.
(14)
SBW
435
kHz
A
Δfmeas1 = 1.8 MHz
Δfmeas2 = 3.6 MHz
fRF = 315 MHz
(14)
IIP3
–24
dBm
C
fRF = 433.92 MHz
(14)
IIP3
–23
dBm
C
Δfmeas1 = 1 MHz
fRF = 315 MHz
(14)
I1dBCP
–31
–36
dBm
C
fRF = 433.92 MHz
–35
(14)
I1dBCP
–30
dBm
C
fRF = 315 MHz
14
Zin_LNA
(72.4 – j298)
Ω
C
fRF = 433.92 MHz
14
Zin_LNA
(55 – j216)
Ω
C
BER < 10 , ASK: 100%
(14)
PIN_max
+5
–10
dBm
C
FSK: fDEV = ±38 kHz
(14)
PIN_max
+5
–10
dBm
C
–3
f < 1 GHz
(14)
–57
dBm
C
f >1 GHz
(14)
–47
dBm
C
fLO = 315.44 MHz
2 × fLO
4 × fLO
(14)
–90
–94
–68
dBm
C
fLO = 434.36 MHz
2 × fLO
4 × fLO
(14)
–92
–88
–58
dBm
C
With the complete image
band
fRF = 315 MHz
(14)
24
30
dB
fRF = 433.92 MHz
(14)
24
30
dB
A
Peak level of useful signal
to peak level of interferer
for BER < 10–3 with any
modulation scheme of
Useful signal to interferer
interferer
3.19
ratio
FSK BR_Ranges 0, 1, 2
A
(14)
SNRFSK0-2
2
3
dB
B
FSK BR_Range_3
(14)
SNRFSK3
4
6
dB
B
ASK (PRF < PRFIN_High)
(14)
SNRASK
10
14
dB
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component
values as in Table 2-2 on page 7 (RFIN).
33
4971C–INDCO–04/09
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No. Parameters
3.20 RSSI output
3.21
Pin(1)
Symbol
Unit
Type*
Dynamic range
(14),17
DRSSI
65
dB
A
Lower level of range
fRF = 315 MHz
fRF = 433.92 MHz
(14),17
PRFIN_Low
–110
dBm
A
Upper level of range
fRF = 315 MHz
fRF = 433.92 MHz
(14),17
PRFIN_High
–45
dBm
A
Test Conditions
Min.
Gain
(14),17
Output voltage range
(14),17
VRSSI
350
17
RRSSI
8
Output resistance
RSSI pin
Typ.
Max.
15
10
mV/dB
A
1600
mV
A
12.5
kΩ
C
dBC
C
dBC
C
nF
D
Sensitivity (BER = 10–3) is
reduced by 3 dB if a
continuous wave blocking
signal at ±Δf is ΔPBlock
higher than the useful
signal level
(Bit rate = 10 Kbits/s,
FSK, fDEV ± 38 kHz,
Manchester code,
BR_Range2)
3.22 Blocking
fRF = 315 MHz
Δf ± 1.5 MHz
Δf ± 2 MHz
Δf ± 3 MHz
Δf ± 10 MHz
Δf ± 20 MHz
fRF = 433.92 MHz
Δf ± 1.5 MHz
Δf ± 2 MHz
Δf ± 3 MHz
Δf ± 10 MHz
Δf ± 20 MHz
3.23 CDEM
Capacitor connected to
pin 23 (CDEM)
(14)
(14)
23
57.5
63.0
67.5
72.0
74.0
ΔPBlock
56.5
62.0
66.5
71.0
73.0
ΔPBlock
–5%
15
+5%
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
34
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component
values as in Table 2-2 on page 7 (RFIN).
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
Pin(1)
Symbol
7,8
gm, XTO
7,8
TXTO_Startup
7,8
C0max
3
ΔfXTO
V(XTAL1, XTAL2)
peak-to-peak value
7,8
VPPXTAL
V(XTAL1)
peak-to-peak value
7,8
VPPXTAL
4.6
C0 ≤ 2.2 pF, small signal
Maximum series
start impedance, this
resistance Rm of XTAL at
value is important for
startup
crystal oscillator startup
7,8
ZXTAL12_START
4.7
Maximum series
resistance Rm of XTAL
after startup
C0 ≤ 2.2 pF
Cm < 14 fF
7,8
Rm_max
15
4.8
Nominal XTAL load
resonant frequency
fRF = 433.92 MHz
fRF = 315 MHz
7,8
fXTAL
13.57375
13.1433
No. Parameters
4
Test Conditions
Min.
Typ.
Max.
Unit
Type*
20
mS
B
300
µs
A
3.8
pF
D
+5
ppm
C
700
mVpp
C
350
mVpp
C
–2000
Ω
B
Ω
B
MHz
D
MHz
A
XTO
4.1
At startup; after startup
Transconductance XTO at
the amplitude is regulated
start
to VPPXTAL
4.2
XTO start-up time
4.3
Maximum C0 of XTAL
4.4
Pulling of LO frequency
fLO due to XTO, CL1 and
CL2 versus temperature
and supply changes
C0 ≤ 2.2 pF
Cm < 14 fF
Rm ≤ 120Ω
1.0 pF ≤ C0 ≤ 2.2 pF
Cm = 4.0 fF to 7.0 fF
Rm ≤ 120Ω
–5
Cm = 5 fF, C0 = 1.8 pF
Rm = 15Ω
4.5
4.9
Amplitude XTAL after
startup
External CLK_OUT
frequency
–1400
120
CLK_OUT_CRTL1 = 0
CLK_OUT_CTRL0 = 0
--> CLK_OUT disabled
fCLK disabled (low level on pin
CLK_OUT)
CLK_OUT_CRTL1 = 0
CLK_OUT_CTRL0 = 1
--> division ratio = 3
f XTO
f CLK = ---------3
CLK_OUT_CRTL1 = 1
CLK_OUT_CTRL0 = 0
--> division ratio = 6
CLK_OUT_CRTL1 = 1
CLK_OUT_CTRL0 = 1
--> division ratio = 12
3
fCLK_OUT
f CLK
f XTO
= ---------6
f XTO
f CLK = ---------12
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component
values as in Table 2-2 on page 7 (RFIN).
35
4971C–INDCO–04/09
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 315 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No. Parameters
4.10 DC voltage after startup
5
5.1
Pin(1)
Symbol
fRF = 433.92 MHz
CLK_OUT division ratio
=3
=6
= 12
CLK_OUT has nominal
50% duty cycle
3
fCLK_OUT
fRF = 315 MHz
CLK_OUT division ratio
=3
=6
= 12
CLK_OUT has nominal
50% duty cycle
3
fCLK_OUT
VDC (XTAL1, XTAL2)
XTO running (Standby
mode, Active mode)
7,8
VDCXTO
Test Conditions
Min.
–250
Typ.
Max.
Unit
Type*
4.52458
2.26229
1.13114
MHz
D
4.3811
2.190
1.0952
MHz
D
–45
mV
C
Synthesizer
Spurs in Active mode
At ±fCLK_OUT,
CLK_OUT enabled
(division ratio = 3)
fRF = 315 MHz
fRF = 433.92 MHz
SPRX
–75
–70
dBC
C
at ±fXTO
fRF = 315 MHz
fRF = 433.92 MHz
SPRX
–75
–70
dBC
A
5.2
Phase noise at 3 MHz
Active mode
fRF = 315 MHz
fRF = 433.92 MHz
LRX3M
–130
–127
dBC/Hz
A
5.3
Phase noise at 20 MHz
Active mode
Noise floor
LRX20M
–135
–132
dBC/Hz
B
trise
20
30
ns
tfall
20
30
ns
CCLK_OUT
8
6
Microcontroller Interface
6.1
fCLK_OUT < 4.5 MHz
CL = 10 pF
CL = Load capacitance on
CLK_OUT output rise and
pin CLK_OUT
fall time
2.7V ≤ VVS5V ≤ 3.3V or
4.5V ≤ VVS5V ≤ 5.5V
20% to 80% VVS5V
3
6.2
Internal equivalent
capacitance
3
Used for current
calculation
pF
B
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
36
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 7 with component
values as in Table 2-2 on page 7 (RFIN).
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
14. Electrical Characteristic: 3V Application
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V and VVS5V = 5V. Typical values are given at
fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No.
7
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
2
µA
A
3.3
V
A
3V Application
7.1
Supply current in OFF
mode
VVS3V_AVCC = VVS5V ≤ 3V
CLK_OUT disabled
10, 11
ISOFF
7.2
Supported voltage
range
3V application
10, 11
VVS3V_AVCC,
VVS5V
7.3
VVS3V_AVCC = VVS5V ≤3V
external load C on pin
CLK_OUT = 12 pF
CLK enabled
(division ratio 3)
Current in Standby
mode (XTO is running) CLK enabled
(division ratio 6)
CLK enabled
(division ratio 12)
CLK disabled
10, 11
2.7
420
IStandby
290
C
µA
C
220
C
50
A
7.4
Current during
TStartup_PLL
VVS3V_AVCC = VVS5V ≤3V
CLK disabled
10, 11
IStartup_PLL
4.5
mA
C
7.5
VVS3V_AVCC = VVS5V ≤3V
Current in Active mode
CLK disabled
ASK
SENSE_CTRL = 0
10, 11
IActive
6.5
mA
A
7.6
VVS3V_AVCC = VVS5V ≤3V
Current in Active mode
CLK disabled
FSK
SENSE_CTRL = 0
10, 11
IActive
6.7
mA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
37
4971C–INDCO–04/09
15. Electrical Characteristics: 5V Application
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V and VVS5V = 5V. Typical values are given at
fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”.
No.
8
Parameters
Test Conditions
Pin
Symbol
8.1
Supply current in OFF
mode
VVS5V = 5V
CLK_OUT disabled
10
ISOFF
8.2
Supported voltage
range
5V application
10
VVS5V
Current in Standby
mode (XTO is
running)
VVS5V ≤5V
external load C on pin
CLK_OUT = 12 pF
CLK enabled
(division ratio 3)
CLK enabled
(division ratio 6)
CLK enabled
(division ratio 12)
CLK disabled
10
8.3
Min.
Typ.
Max.
Unit
Type*
2
µA
A
5.5
V
A
5V Application
4.5
700
IStandby
490
C
µA
C
370
C
50
A
8.4
Current during
TStartup_PLL
VVS5V = 5V
CLK disabled
10
IStartup_PLL
4.7
mA
C
8.5
Current in Active
mode ASK
VVS5V = 5V
CLK disabled
SENSE_CTRL = 0
10
IActive
6.7
mA
A
8.6
Current in Active
mode FSK
VVS5V = 5V
CLK disabled
SENSE_CTRL = 0
10
IActive
6.9
mA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
38
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
16. Digital Timing Characteristics
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”
No.
9
9.1
Parameters
Extended basic clock
cycle
10
Active Mode
10.1
Startup PLL
10.3
Pin
Basic clock cycle
9.2
10.2
Test Conditions
Symbol
Min.
TDCLK
TXDCLK
Typ.
Max.
Unit
Type*
16 / fXTO
16 / fXTO
µs
A
8
4
2
1
× TDCLK
8
4
2
1
× TDCLK
µs
A
15 µs +
208 ×
TDCLK
µs
A
Basic Clock Cycle of the Digital Circuitry
Startup signal
processing
Bit rate range
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
TStartup_PLL
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
TStartup_Sig_Proc
ASK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
FSK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
10.4
Minimum time period
between edges at pin
DATA_OUT
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
10.5
Edge-to-edge time
period of the data signal
for full sensitivity in
Active mode
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
BR_Range
24
929.5
545.5
353.5
257.5
× TDCLK
929.5
545.5
353.5
257.5
× TDCLK
1.0
2.0
4.0
8.0
2.5
5.0
10.0
10.0
1.0
2.0
4.0
8.0
2.5
5.0
10.0
20.0
TDATA_OUT_min
10 ×
TXDCLK
TDATA_OUT
200
100
50
25
A
Kbits/s
A
µs
A
µs
B
500
250
125
62.5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
39
4971C–INDCO–04/09
17. Digital Port Characteristics
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”
No.
Parameters
11
Digital Ports
11.1
11.2
11.3
11.4
11.5
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
V
A
V
A
V
A
V
A
V
A
V
A
V
A
V
A
V
A
V
A
0.2 × VS
VS = VVS3V_AVCC =
V
ENABLE input
VS5V = 2.7V to 3.3V
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
6
VIl
VS = VVS3V_AVCC =
V
= 2.7V to 3.3V
- High level input voltage VS5V
VS = VVS5V = 4.5V to
5.5V
6
VIh
0.12 ×
VS
0.8 × VS
0.2 × VS
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
RX input
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
19
VIl
VS = VVS3V_AVCC =
V
= 2.7V to 3.3V
- High level input voltage VS5V
VS = VVS5V =
4.5V to 5.5V
19
VIh
0.12 ×
VS
0.8 × VS
0.2 × VS
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
BR0 input
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
20
VIl
VS = VVS3V_AVCC =
V
= 2.7V to 3.3V
- High level input voltage VS5V
VS = VVS5V =
4.5V to 5.5V
20
VIh
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
BR1 input
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
21
VIl
VS = VVS3V_AVCC =
= 2.7V to 3.3V
V
- High level input voltage VS5V
VS = VVS5V =
4.5V to 5.5V
21
VIh
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
ASK_NFSK input
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
22
VIl
VS = VVS3V_AVCC =
= 2.7V to 3.3V
V
- High level input voltage VS5V
VS = VVS5V =
4.5V to 5.5V
22
VIh
0.12 ×
VS
0.8 × VS
0.2 × VS
0.12 ×
VS
0.8 × VS
0.2 × VS
0.12 ×
VS
0.8 × VS
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
40
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
17. Digital Port Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”
No.
11.6
11.7
11.8
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
V
A
V
A
V
A
V
A
V
A
V
A
0.2 × VS
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
SENSE_CTRL input
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
16
VIl
VS = VVS3V_AVCC =
V
= 2.7V to 3.3V
- High level input voltage VS5V
VS = VVS5V =
4.5V to 5.5V
16
VIh
0.12 ×
VS
0.8 × VS
0.2 × VS
VS = VVS3V_AVCC =
CLK_OUT_CTRL0 input VVS5V = 2.7V to 3.3V
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
5
VIl
VS = VVS3V_AVCC =
= 2.7V to 3.3V
V
- High level input voltage VS5V
VS = VVS5V =
4.5V to 5.5V
5
VIh
0.12 ×
VS
0.8 × VS
0.2 × VS
VS = VVS3V_AVCC =
CLK_OUT_CTRL1 input VVS5V = 2.7V to 3.3V
- Low level input voltage VS = VVS5V =
4.5V to 5.5V
4
VIl
VS = VVS3V_AVCC =
= 2.7V to 3.3V
V
- High level input voltage VS5V
VS = VVS5V =
4.5V to 5.5V
4
VIh
0.12 ×
VS
0.8 × VS
11.9
TEST1 input
TEST1 input must
always be connected
directly to GND
2
0
0
V
D
11.10
TEST2 output
TEST2 output must
always be connected
directly to GND
1
0
0
V
D
11.11
TEST3 input
TEST3 input must
always be connected
directly to GND
18
0
0
V
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
41
4971C–INDCO–04/09
17. Digital Port Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS3V_AVCC = VVS5V = 3V, and VVS5V = 5V. Typical values are given at
fRF = 433.92 MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the
specific sections of the “Electrical Characteristics”
No.
11.12
11.13
Parameters
Pin
Symbol
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
DATA_OUT output
VS = VVS5V =
- Saturation voltage low
4.5V to 5.5V
IDATA_OUT = 250 µA
Test Conditions
24
Vol
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
- Saturation voltage high VS = VVS5V =
4.5V to 5.5V
IDATA_OUT = –250 µA
24
Voh
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
CLK_OUT output
VS = VVS5V =
- Saturation voltage low
4.5V to 5.5V
IDATA_OUT = 100 µA
3
Vol
VS = VVS3V_AVCC =
VVS5V = 2.7V to 3.3V
- Saturation voltage high VS = VVS5V =
4.5V to 5.5V
IDATA_OUT = –100 µA
3
Voh
Min.
VVS – 0.4
Typ.
Max.
Unit
Type*
0.15
0.4
V
B
V
B
V
B
V
B
VVS –
0.15
0.15
VVS – 0.4
0.4
VVS –
0.15
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
42
ATA8201/ATA8202
4971C–INDCO–04/09
ATA8201/ATA8202
18. Ordering Information
Extended Type Number
Package
MOQ
Remarks
ATA8202-PXQW
QFN24
6000 pcs
5 mm × 5 mm, Pb-free, 433.92 MHz
ATA8201-PXQW
QFN24
6000 pcs
5 mm × 5 mm, Pb-free, 315 MHz
19. Package Information
Package: QFN 24 - 5 x 5
Exposed pad 3.6 x 3.6
(acc. JEDEC OUTLINE No. MO-220)
Dimensions in mm
Not indicated tolerances ±0.05
5
0.9±0.1
+0
3.6
0.05-0.05
24
19
1
24
0.4
18
0.3
6
1
technical drawings
according to DIN
specifications
13
6
12
7
0.65 nom.
Drawing-No.: 6.543-5122.01-4
3.25
Issue: 1; 15.11.05
20. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4971C-INDCO-04/09
• Put datasheet in the newest template
• Benefits changed (page 2)
4971B-INDCO-10/07
• Put datasheet in the newest template
43
4971C–INDCO–04/09
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4971C–INDCO–04/09