24VL024/24VL025
2K I2C™ Serial EEPROM
Device Selection Table
Description:
Part Number
VCC Range
Max Clock
24VL024
1.5 to 3.6V
400 kHz(1)
24VL025
1.5 to 3.6V
400 kHz(1)
Note 1: 100 kHz for VCC < 1.8V
Features:
• Single-Supply with Operation down to 1.5V
• Low-Power CMOS Technology:
- 400 μA active current, maximum
- 1 μA standby current, maximum
• 2-Wire Serial Interface Bus, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Compatibility
• Page Write Buffer for up to 16 Bytes
• Self-Timed Write Cycle (including Auto-Erase)
• Hardware Write Protection for the Entire Array
(24VL024 only)
• Cascadable up to Eight Devices
• More than 1 Million Erase/Write Cycles
• ESD Protection > 4,000V
• Data Retention > 200 Years
• Factory Programming (QTP) Available
• 8-pin PDIP, SOIC, TSSOP, TDFN and MSOP
Packages
• 6-lead SOT-23 package (24VL025 only)
• Temperature Range:
- -20°C to +85°C
The Microchip Technology Inc. 24VL024/24VL025 is a
2 Kbit Serial Electrically Erasable PROM with
operation down to 1.5V. The device is organized as a
single block of 256 x 8-bit memory with a 2-wire serial
interface. Low-current design permits operation with
maximum standby and active currents of only 1 μA and
400 μA, respectively. The device has a page write
capability for up to 16 bytes of data. Functional address
lines allow the connection of up to eight 24VL024/
24VL025 devices on the same bus for up to 16 Kbits of
contiguous EEPROM memory. The device is
available in the standard 8-pin PDIP, 8-pin SOIC (150
mil), TSSOP, 2x3 TDFN and MSOP packages. The
24VL025 is also available in the 6-lead, SOT-23
package.
Block Diagram
WP
A0 A1 A2
HV Generator
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
SDA SCL
Write-Protect
Circuitry
YDEC
VCC
VSS
Sense Amp.
R/W Control
Package Types
SOIC, TSSOP
PDIP, MSOP
• Pb-Free and RoHS Compliant
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
VSS
4
5
SDA
VSS
4
5
SDA
SOT-23
TDFN
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SCL
1
6
VCC
VSS
2
5
A0
SDA
3
4
A1
(24VL025 only)
Note:
© 2009 Microchip Technology Inc.
WP pin is not internally connected on the 24VL025
DS22130A-page 1
24VL024/24VL025
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ..................................................................................................-20°C to +85°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Electrical Characteristics:
VCC = +1.5V to 3.6V TA = -20°C to +85°C
Min.
Max.
Units
Conditions
—
—
—
D1
—
A0, A1, A2, SCL, SDA
and WP pins:
—
D2
VIH
High-level input voltage
0.7 VCC
—
V
—
D3
VIL
Low-level input voltage
—
0.3 VCC
V
—
D4
VHYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC
—
V
(Note)
D5
VOL
Low-level output voltage
—
0.40
V
IOL = 3.0 mA @ VCC = 3.6V
IOL = 2.1 mA @ VCC = 2.5V
D6
ILI
Input leakage current
—
±1
μA
VIN = VSS or VCC, WP = VSS
D7
ILO
Output leakage current
—
±1
μA
VOUT = VSS or VCC
D8
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
10
pF
VCC = 3.6V (Note)
TA = 25°C, f = 1 MHz
D9
ICC Read Operating current
—
400
μA
VCC = 3.6V, SCL = 400 kHz
—
3
mA
VCC = 3.6V
D10
ICCS
—
1
μA
VCC = 3.6V, SCL = SDA = VCC
WP = VSS, A0, A1, A2 = VSS
ICC Write
Note:
Standby current
This parameter is periodically sampled and not 100% tested.
DS22130A-page 2
© 2009 Microchip Technology Inc.
24VL024/24VL025
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
VCC = +1.5V to 3.6V TA = -20°C to +85°C
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Conditions
1
FCLK
Clock frequency
—
—
100
400
kHz
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
2
THIGH
Clock high time
4000
600
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
3
TLOW
Clock low time
4700
1300
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
4
TR
SDA and SCL rise time
(Note 1)
—
—
1000
300
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
5
TF
SDA and SCL fall time
(Note 1)
—
—
1000
300
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
6
THD:STA
Start condition hold time
4000
600
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
7
TSU:STA
Start condition setup time
4700
600
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
8
THD:DAT
Data input hold time
0
—
ns
(Note 2)
9
TSU:DAT
Data input setup time
250
100
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
10
TSU:STO
Stop condition setup time
4000
600
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
11
TSU:WP
WP setup time (Note 5)
4000
600
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
12
THD:WP
WP hold time (Note 5)
4700
600
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
13
TAA
Output valid from clock
(Note 2)
—
—
3500
900
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
14
TBUF
Bus free time: Time the bus must
be free before a new transmission can start
4700
1300
—
—
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
15
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Note 1 and Note 3)
16
TWC
Write cycle time (byte or page)
—
5
ms
—
17
—
Endurance
1M
—
cycles 25°C, VCC = 3.6V, per page
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at
www.microchip.com.
5: 24VL024 only.
© 2009 Microchip Technology Inc.
DS22130A-page 3
24VL024/24VL025
FIGURE 1-1:
BUS TIMING DATA
5
SCL
7
SDA
In
3
4
D4
2
8
10
9
6
15
14
13
SDA
Out
WP
DS22130A-page 4
(protected)
(unprotected)
11
12
© 2009 Microchip Technology Inc.
24VL024/24VL025
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
8-pin
PDIP
8-pin
SOIC
8-pin
TSSOP
8-pin
MSOP
8-pin
TDFN
6-pin
SOT-23
A0
1
1
1
1
1
5
User Configurable Chip Select
A1
2
2
2
2
2
4
User Configurable Chip Select
A2
3
3
3
3
3
—
User Configurable Chip Select
VSS
4
4
4
4
4
2
Ground
Name
Function
SDA
5
5
5
5
5
3
Serial Data
SCL
6
6
6
6
6
1
Serial Clock
WP
7
7
7
7
7
—
Write-Protect Input
VCC
8
8
8
8
8
6
+1.5V to 3.6V
2.1
SDA Serial Data
2.4
WP (24VL024 only)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
WP is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to VCC, the hardware write protection
is enabled and will protect the entire array (00h-FFh). If
the WP pin is tied to VSS the hardware write protection
is disabled.
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.5
2.2
SCL Serial Clock
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
Noise Protection
The 24VL024/24VL025 employs a VCC threshold
detector circuit that disables the internal erase/write
logic if the VCC is below 1.0 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits that suppress noise spikes to assure
proper device operation even on a noisy bus.
A0, A1, A2
The A0, A1 and A2 inputs are used by the 24VL024/
24VL025 for multiple device operations. The levels on
these inputs are compared with the corresponding bits
in the slave address. The chip is selected if the
compare is true.
Up to eight 24VL024/24VL025 devices (four for the
SOT-23 package) may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
© 2009 Microchip Technology Inc.
DS22130A-page 5
24VL024/24VL025
3.0
FUNCTIONAL DESCRIPTION
The 24VL024/24VL025 supports a bidirectional, 2-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device that generates the Serial
Clock (SCL), controls the bus access and generates
the Start and Stop conditions, while the 24VL024/
24VL025 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
DS22130A-page 6
© 2009 Microchip Technology Inc.
24VL024/24VL025
4.0
BUS CHARACTERISTICS
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited, though only the last sixteen will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.1
4.5
Bus Not Busy (A)
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Note:
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
FIGURE 4-1:
SCL
(A)
The 24VL024/24VL025 does not generate
any Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the
master to generate the Stop condition (Figure 4-2).
Stop Data Transfer (C)
4.4
Acknowledge
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(B)
(C)
(D)
(C)
(A)
SDA
Start
Condition
FIGURE 4-2:
Address or
Acknowledge
Valid
Stop
Condition
Data
Allowed
to Change
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
SDA
1
2
3
4
5
6
7
Data from transmitter
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
© 2009 Microchip Technology Inc.
8
9
1
2
3
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
DS22130A-page 7
24VL024/24VL025
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code; for
the 24VL024/24VL025 this is set as ‘1010’ binary for
read and write operations. The next three bits of the
control byte are the Chip Select bits (A2, A1, A0). The
Chip Select bits allow the use of up to eight 24VL024/
24VL025 devices on the same bus and are used to
select which device is accessed. The Chip Select bits
in the control byte must correspond to the logic levels
on the corresponding A2, A1 and A0 pins for the device
to respond. These bits are in effect the three Most
Significant bits of the word address.
For the SOT-23 package, the A2 pin is not connected.
During device addressing, the A2 chip select bit should
be set to logic ‘0’. Only four 24VL025 SOT-23 devices
can be connected to the same bus.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is
selected. Following the Start condition, the 24VL024/
24VL025 monitors the SDA bus, checking the control
byte being transmitted. Upon receiving a ‘1010’ code
and appropriate Chip Select bits, the slave device
outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24VL024/
24VL025 will select a read or write operation.
DS22130A-page 8
FIGURE 5-1:
CONTROL BYTE FORMAT
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
0
A2
A1
A0 R/W ACK
Slave Address
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24VL024/24VL025 devices on the
same bus. In this case, software can use A0 of the
control byte as address bit A8, A1 as address bit A9,
and A2 as address bit A10. It is not possible to
sequentially read across device boundaries.
For the SOT-23 package, up to four devices can be
added for up to 8K bits of address space. In this case,
software can use A0 of the control byte as address bit
A8, and A1 as address bit A9. Bit A2 of the control byte
must always be set to logic ‘0’ for the SOT-23 package.
© 2009 Microchip Technology Inc.
24VL024/24VL025
6.0
WRITE OPERATIONS
6.1
Byte Write
The higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if write protection is enabled.
Following the Start signal from the master, the device
code (4 bits), the Chip Select bits (3 bits) and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24VL024/
24VL025. After receiving another Acknowledge
signal from the 24VL024/24VL025, the master device
will transmit the data word to be written into the
addressed memory location. The 24VL024/24VL025
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and the
24VL024/24VL025 will not generate Acknowledge
signals during this time (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if write protection is enabled.
6.2
Note:
Page Write
The write-control byte, word address and the first data
byte are transmitted to the 24VL024/24VL025 in the
same way as in a byte write. But instead of generating
a Stop condition, the master transmits up to 15
additional data bytes to the 24VL024/24VL025 that are
temporarily stored in the on-chip page buffer and will be
written into the memory once the master has
transmitted a Stop condition. Upon receipt of each
word, the four lower order Address Pointer bits are
internally incremented by one.
FIGURE 6-1:
6.3
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary that the
application software prevent page write
operations that would attempt to cross a
page boundary.
Write Protection (24VL024 only)
The WP pin must be tied to VCC or VSS. If tied to VCC,
the entire array will be write-protected (00h-FFh). If the
WP pin is tied to VSS, write operations to all address
locations are allowed.
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
Word
Address
S
T
O
P
Data
P
A
C
K
Bus Activity
FIGURE 6-2:
A
C
K
A
C
K
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
Bus Activity
© 2009 Microchip Technology Inc.
Word
Address (n)
Data (n)
S
T
O
P
Data (n + 15)
Data (n +1)
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS22130A-page 9
24VL024/24VL025
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If no
ACK is returned, the Start bit and control byte must be
re-sent. If the cycle is complete, the device will return
the ACK and the master can then proceed with the next
Read or Write command. See Figure 7-1 for a flow
diagram of this operation.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS22130A-page 10
© 2009 Microchip Technology Inc.
24VL024/24VL025
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24VL024/24VL025 contains an address
counter that maintains the address of the last word
accessed, internally incremented by one. Therefore, if
the previous read access was to address n, the next
current address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/W bit set to ‘1’, the 24VL024/24VL025 issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 24VL024/24VL025
discontinues transmission (Figure 8-1).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24VL024/24VL025 as part of a write operation.
FIGURE 8-1:
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again but with the R/W bit set to a ‘1’.
The 24VL024/24VL025 will then issue an
acknowledge and transmits the eight-bit data word.
The master will not acknowledge the transfer, but does
generate a Stop condition and the 24VL024/24VL025
discontinues transmission (Figure 8-2). After this
command, the internal address counter will point to the
address location following the one that was just read.
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24VL024/24VL025
transmits the first data byte, the master issues an
acknowledge as opposed to a Stop condition in a
random read. This directs the 24VL024 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24VL024/24VL025
contains an internal Address Pointer which is
incremented by one at the completion of each
operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation. The
internal
Address
Pointer
will
automatically roll over from address FFh to address
00h.
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Bus Activity
© 2009 Microchip Technology Inc.
Control
Byte
S
T
O
P
Data
P
A
C
K
N
O
A
C
K
DS22130A-page 11
24VL024/24VL025
FIGURE 8-2:
Bus Activity
Master
SDA Line
RANDOM READ
S
T
A
R
T
Control
Byte
S
Bus Activity
Master
Control
Byte
S
T
O
P
Data (n)
P
S
A
C
K
A
C
K
Bus Activity
FIGURE 8-3:
S
T
A
R
T
Word
Address (n)
N
O
A
C
K
A
C
K
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + X)
P
SDA Line
Bus Activity
DS22130A-page 12
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2009 Microchip Technology Inc.
24VL024/24VL025
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example:
24VL024
P e3112F
0821
XXXXXXXX
T/XXXNNN
YYWW
8-Lead SOIC (3.90 mm)
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP
Example:
24VL024
SN e3 0821
12F
Example:
XXXX
4V24
TYWW
821
NNN
12F
8-Lead MSOP
Example:
XXXXXT
4V24
YWWNNN
82112F
8-Lead 2x3 TDFN
XXX
YWW
NN
6-Lead SOT-23
XXNN
© 2009 Microchip Technology Inc.
Example:
AP9
821
12
Example:
HF12
DS22130A-page 13
24VL024/24VL025
1st Line Marking Codes
Part Number
TSSOP
MSOP
TDFN
SOT-23
24VL024
4V24
4V24
AP9
—
24VL025
4V25
4V25
AR6
HFNN
Legend: XX...X
T
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
DS22130A-page 14
© 2009 Microchip Technology Inc.
24VL024/24VL025
3
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© 2009 Microchip Technology Inc.
DS22130A-page 15
24VL024/24VL025
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1
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DS22130A-page 16
© 2009 Microchip Technology Inc.
24VL024/24VL025
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© 2009 Microchip Technology Inc.
DS22130A-page 17
24VL024/24VL025
() )"* !
(+%+(
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3
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1
2
b
e
c
A
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L
L1
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DS22130A-page 18
© 2009 Microchip Technology Inc.
24VL024/24VL025
," !
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b
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c
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© 2009 Microchip Technology Inc.
DS22130A-page 19
24VL024/24VL025
.
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DS22130A-page 20
© 2009 Microchip Technology Inc.
24VL024/24VL025
.
$*-,/00%12(.
3
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© 2009 Microchip Technology Inc.
DS22130A-page 21
24VL024/24VL025
3
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(""!( !(/
3
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b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
A
A2
c
φ
L
A1
L1
6&!
'!
9'&!
7"')
%!
99..
7
7
7:
;
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&
1,
:"&!#9#&
1,
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=
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9
=
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DS22130A-page 22
© 2009 Microchip Technology Inc.
24VL024/24VL025
REVISION HISTORY
Revision A (01/2009)
Original release.
© 2009 Microchip Technology Inc.
DS22130A-page 23
24VL024/24VL025
NOTES:
DS22130A-page 24
© 2009 Microchip Technology Inc.
24VL024/24VL025
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2009 Microchip Technology Inc.
DS22130A-page 25
24VL024/24VL025
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: 24VL024/24VL025
Y
N
Literature Number: DS22130A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22130A-page 26
© 2009 Microchip Technology Inc.
24VL024/24VL025
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Temperature
Range
Device:
24VL024:
24VL024T:
24VL025:
24VL025T:
Temperature Range:
=
Package
1.5V, 2 Kbit Addressable Serial EEPROM
1.5V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel)
1.5V, 2 Kbit Addressable Serial EEPROM,
with no WP pin
1.5V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel), with no WP pin
Examples:
a)
b)
c)
d)
e)
f)
g)
-20°C to +85°C
h)
Package:
Note
P
SN
ST
MS
MNY(1)
OT
1:
24VL024/P: 1.5V, PDIP Package.
24VL024/SN: 1.5V, SOIC Package.
24VL024T/ST: 1.5V, TSSOP Package,
Tape and Reel
24VL024T/MNY: 1.5V, TDFN Package,
Tape and Reel
24VL025/P: 1.5V, PDIP Package.
24VL025/SN: 1.5V, SOIC Package.
24VL025T/ST: 1.5V, TSSOP Package,
Tape and Reel
24VL025T/MNY: 1.5V, TDFN Package,
Tape and Reel
=
=
=
=
=
=
Plastic DIP, (300 mil Body), 8-lead
Plastic SOIC, (3.90 mm Body)
TSSOP, (4.4 mm Body), 8-lead
MSOP, (Plastic Micro Small Outline), 8-lead
TDFN, (2x3x0.75 mm Body), 8-lead
Plastic Small Outline (SOT-23), 6-lead (Tape
and Reel only)
“Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
© 2009 Microchip Technology Inc.
DS22130A-page 27
24VL024/24VL025
NOTES:
DS22130A-page 28
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS22130A-page 29
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
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Tel: 81-45-471- 6166
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Tel: 49-89-627-144-0
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Atlanta
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Tel: 678-957-9614
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Boston
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Fax: 774-760-0088
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Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/16/09
DS22130A-page 30
© 2009 Microchip Technology Inc.