merging Memory & Logic Solutions Inc. EM641FV8FT Series Low Power, 512Kx8 SRAM Document Title 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial Draft 0.1 2’nd Draft Draft Date May 25 , 2003 Add Pb-free part number Remark Preliminary February 13 , 2004 Emerging Memory & Logic Solutions Inc. IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM641FV8FT Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM FEATURES GENERAL DESCRIPTION • • • • • • The EM641FV8FT families are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. Process Technology : 0.18µm Full CMOS Organization : 512K x 8 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min) Three state output and TTL Compatible Package Type : 32-TSOP1 PRODUCT FAMILY Power Dissipation Product Family EM641FV8FT Operating Temperature Vcc Range Speed Standby (ISB1 , Typ) Industrial (-40 ~ 85oC) 2.7V~3.6V 551) / 70ns 1 µA2) Operating (I CC1.Max) 3 mA PKG Type 32- TSOP1 1. The parameter is measured with 30pF test load. 2. Typical values are measured at Vcc=3.3V, T A =25o C and not 100% tested. FUNCTIONAL BLOCK DIAGRAM A11 1 32 OE A9 2 31 A10 A8 3 30 CS A13 4 29 IO8 WE A17 5 6 28 27 IO7 IO6 A15 7 26 IO5 VCC A18 8 9 25 24 IO4 VSS A16 A14 A12 10 11 23 22 I/O3 I/O2 12 21 I/O1 A7 A6 13 20 A0 14 15 19 A1 A5 A4 16 18 17 A2 A3 32 - TSOP Type1 - Forward Pre-charge Circuit A0 A1 A2 VCC Row S elect PIN DESCRIPTION A3 A4 A5 A6 A7 I/O1 ~ I/O4 Function Name Chip select inputs WE Write Enable input OE Output Enable input Vcc Power Supply Address Inputs Vss Ground Data Inputs/outputs NC No Connection Data Cont I/O Circuit Column Select A11 A12 A13 A14 A15 A16 A17 A18 WE I/O1 ~I/O 8 Data Cont Function CS A 0 ~A18 2048 x 2048 A8 A9 A10 I/O5 ~ I/O8 Name VSS Memory Array OE CS 2 Control Logic EM641FV8FT Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Symbol Voltage on Any Pin Relative to Vss Ratings Unit VIN , VOUT -0.2 to Vcc+0.3(Max.4.0V) V VCC -0.2 to 4.0V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 oC Voltage on Vcc supply relative to Vss * Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS OE WE I/O Mode Power H X X High-Z Deselected Stand by L H H High-Z Output Disabled Active L L H Data Out Read Active L X L Data In Write Active Note: X means don’t care. (Must be low or high state) 3 EM641FV8FT Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter 1. 2. 3. 4. Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.3 3.6 V Ground VSS 0 0 0 V Input high voltage VIH 2.2 - VCC + 0.22) V Input low voltage VIL -0.2 3) - 0.6 V TA= -40 to 85oC, otherwise specified Overshoot: V CC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance C IN VIN=0V - 8 pF Input/Ouput capacitance CIO VIO =0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI V IN=V SS to V CC -1 - 1 µA Output leakage current ILO CS=VIH or OE = VIH or WE=V IL, VIO =VSS to V CC -1 - 1 µA Operating power supply ICC I IO=0mA, CS = VIL , VIN = VIH or V IL - - 3 mA - - 3 mA 55ns - - 25 70ns - - 20 I CC1 Cycle time=1µs, 100% duty, I IO=0mA, CS<0.2V, V I N<0.2V or V IN> V CC-0.2V Average operating current I CC2 Cycle time = Min, I IO =0mA, 100% duty, CS= VIL , V IN=V IL or V IH Output low voltage VOL I OL = 2.1mA - - 0.4 V Output high voltage VOH I O H = -1.0mA 2.4 - - V - - 0.3 mA - 11) 12 µA Standby Current (TTL) ISB CS=VIH , Other inputs=VIH or VIL CS>V CC -0.2V, Standby Current (CMOS) ISB1 Other inputs=0~VCC (Typ. condition : V C C=3.3V @ 25 oC) o (Max. condition : V CC=3.6V @ 85 C) NOTES 1. Typical values are measured at Vcc=3.3V, TA= 25o C and not 100% tested. 4 LL LF mA EM641FV8FT Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM VTM 3) AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) R12) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL = 100pF+ 1 TTL R22) CL1) CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R1 =3070Ω, R 2 =3150Ω 3. VTM=2.8V READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40oC to +85oC) Parameter 55ns Symbol 70ns Min Max Min Max Unit Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tco - 55 - 70 ns Output enable to valid output tO E - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter 55ns Symbol 70ns Unit Min Max Min Max Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address setup time tAs 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to ouput high-Z tWHZ 0 20 0 20 ns Data to write time overlap tDW 25 Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns 5 30 ns merging Memory & Logic Solutions Inc. EM641FV8FT Series Low Power, 512Kx8 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=V IL, WE=V IH ) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA tOH tCO CS tHZ tOE OE tOHZ tOLZ Data Out High-Z Data Valid tLZ NOTES (READ CYCLE) 1. t HZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ(Min.) both for a given device and from device to device interconnection. 6 EM641FV8FT Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW (2) tWR(4) CS tA W tWP (1) WE tAS(3) Data in tDW High-Z High-Z Data Valid tWHZ Data out tDH tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED) tWC Address tAS(3) tCW (2) tWR (4) CS tAW tWP (1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE goes low. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS going low to end of write. 3. t A S is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. 7 EM641FV8FT Series merging Memory & Logic Solutions Inc. Low Power, 512Kx8 SRAM DATA RETENTION CHARACTERISTICS Parameter Symbol VCC for Data Retention VDR Data Retention Current I DR Chip Deselect to Data Retention Time tSDR Operation Recovery Time Test Condition ISB1 Test Condition (Chip Disabled) 1) VCC =1.5V, ISB1 Test Condition (Chip Disabled) 1) Min Typ2) Max Unit 1.5 - 3.6 V - 0.5 - µA 0 - - t RC - - See data retention wave form tRDR ns NOTES 1. See the IS B 1 measurement condition of datasheet page 4. 2. Typical values are measured at T A= 25o C and not 100% tested. DATA RETENTION WAVE FORM CS Controlled tSDR Data Retention Mode Vcc 2.7V 2.2V VDR CS > Vcc-0.2V CS GND 8 tRDR merging Memory & Logic Solutions Inc. EM641FV8FT Series Low Power, 512Kx8 SRAM Unit : millimeters/Inches 9 merging Memory & Logic Solutions Inc. EM641FV8FT Series Low Power, 512Kx8 SRAM MEMORY FUNCTION GUIDE EM X XX X X X XX X X - XX XX 1. EMLSI Memory 11. Power 2. Device Type 10. Speed 3. Density 4. Option 9. Packages 5. Technology 8. Version 6. Operating Voltage 7. Orgainzation 1. Memory Component 7. Orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 8. Version Blank ----------------- Mother Die A ----------------------- First revision B ----------------------- Second revision C ----------------------- Third revision D ----------------------- Fourth revision E ----------------------- Fifth revision F ----------------------- Sixth revision 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 9. Package Blank ---------------------- FPBGA S ---------------------------- 32 sTSOP1 T ---------------------------- 32 TSOP1 U ---------------------------- 44 TSOP2 W ---------------------------- Wafer 4. Mode Option 0 -------- Dual CS 1 -------- Single CS 2 -------- Multiplexed Address 3 -------- Single CS with LB,UB (tBA=tOE) 4 -------- Single CS with LB,UB (tBA=tCO) 5 -------- Dual CS with LB,UB (tBA=tOE) 6 -------- Dual CS with LB,UB (tBA=tCO) 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 5. Technology Blank ------------------ CMOS F ------------------------ Full CMOS 6. Operating Voltage Blank ------------------- 5V V ------------------------- 2.7V~3.6V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power (Pb-free) L ---------------------- Low Power S ---------------------- Standard Power 10