LTC3865/LTC3865-1 Dual, 2-Phase Synchronous DC/DC Controller with Pin Selectable Outputs Description Features Dual, 180° Phased Controllers n 2-Pin VID Output Voltage Programming from 0.6V to 5V n High Efficiency: Up to 95% n R SENSE or DCR Current Sensing n Phase-Lockable Fixed Frequency 250kHz to 770kHz n Adjustable Current Limit n Dual N-Channel MOSFET Synchronous Drive n Wide V Range: 4.5V to 38V Operation IN n Adjustable Soft-Start Current Ramping or Tracking n Output OV Protection With Reverse Current Limit n Power Good Output Voltage Monitor n 32-Pin 5mm × 5mm QFN and 38-Lead TSSOP Packages The LTC®3865/LTC3865-1 are high performance dual synchronous step-down DC/DC switching regulator controllers that drive all N‑channel synchronous power MOSFET stages. A constant frequency current mode architecture allows a phase-lockable frequency of up to 770kHz. Power loss and noise are minimized by operating the two controller output stages out of phase. n OPTI-LOOP® compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. Independent track/soft-start pins for each controller ramp the output voltage during start-up. Current foldback limits MOSFET heat dissipation during short-circuit conditions. The MODE/PLLIN pin selects among Burst Mode® operation, pulse-skipping mode, and continuous inductor current mode. The output voltages can be precisely programmed by pin strapping or external resistors. Applications DC Power Distribution Systems n L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, µModule, Linear Technology and the Linear logo are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. The LTC3865/LTC3865-1 are available in low profile (5mm × 5mm) 32-pin QFN and 38-Lead thermally enhanced TSSOP packages. Typical Application High Efficiency 1.5V/15A, 1.2V/15A Step-Down Converter + 2.2Ω 22µF 50V VIN 4.5V TO 24V Efficiency and Power Loss vs Load Current 1µF 100 4.7µF TG2 BOOST1 SW1 BG1 100Ω SENSE1+ BOOST2 SW2 0.47µH BG2 PGND FREQ SENSE2+ 100Ω SENSE1– SENSE2– VID21 VID11 VID12 VID22 VOSENSE2 VOSENSE1 ITH2 ITH1 TK/SS1 SGND TK/SS2 100µF COUT2,3 1000pF 10k 100pF 0.1µF 0.1µF 2mΩ 162k 15k 60 1 EFFICIENCY POWER LOSS 50 40 0.1 30 10 0 0.01 100Ω 1000pF 70 20 1000pF 100Ω + 80 0.1µF 1000pF 2mΩ VOUT1 1.5V 15A LTC3865 10 VIN = 12V VOUT = 1.5V POWER LOSS (W) 0.47µH INTVCC EFFICIENCY (%) 0.1µF VIN TG1 90 + VOUT2 1.2V 15A 0.1 1 10 LOAD CURRENT (A) 0.01 100 3865 TA01b COUT5,6 100µF 100pF 3865 TA01a 3865f LTC3865/LTC3865-1 Absolute Maximum Ratings (Note 1) Input Supply Voltage (VIN).......................... –0.3V to 40V Topside Driver Voltages BOOST1, BOOST2................................... –0.3V to 46V Switch Voltage (SW1, SW2).......................... –5V to 40V INTVCC, RUN1, RUN2, PGOOD(s), EXTVCC, (BOOST1-SW1), (BOOST2-SW2).................. –0.3V to 6V SENSE1+, SENSE2+, SENSE1–, SENSE2– VOSENSE1, VOSENSE2 Voltages..................... –0.3V to 5.8V MODE/PLLIN, ILIM, TK/SS1, TK/SS2, VID11, VID12, VID21, VID22, FREQ Voltages.... –0.3V to INTVCC ITH1, ITH2 Voltages..................................... –0.3V to 2.7V INTVCC DC Output Current......................................80mA Operating Junction Temperature Range (Notes 2, 3) LTC3865/LTC3865-1........................... –40°C to 125°C Storage Temperature Range.................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) FE Package........................................................ 300°C Pin Configuration LTC3865 TOP VIEW RUN1 1 38 FREQ SENSE1+ 2 37 VID22 SENSE– 3 36 MODE/PLLIN NC 4 35 SW1 TG1 LTC3865 VOSENSE1 5 34 TG1 32 31 30 29 28 27 26 25 TK/SS1 6 33 BOOST1 SW1 MODE/PLLIN VID22 FREQ RUN1 SENSE1+ SENSE1– TOP VIEW ITH1 7 32 PGND1 23 BG1 SGND 8 31 BG1 22 VIN VID11 9 21 INTVCC VID12 10 24 BOOST1 VOSENSE1 1 TK/SS1 2 ITH1 3 VID11 4 33 SGND VID12 5 20 EXTVCC 19 BG2 ITH2 6 TK/SS2 7 18 PGND VOSENSE2 8 17 BOOST2 TG2 SW2 PGOOD ILIM RUN2 VID21 SENSE2+ SENSE2– 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD (5mm s 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W, θJC = 3°C/W EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB ITH2 11 TK/SS2 12 VOSENSE2 13 NC 14 SENSE2– 15 39 SGND 30 VIN 29 INTVCC 28 EXTVCC 27 BG2 26 PGND2 25 BOOST2 24 NC SENSE2+ 16 23 TG2 RUN2 17 22 SW2 VID21 18 21 PGOOD1 ILIM 19 20 PGOOD2 FE PACKAGE 38-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 28°C/W EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO PCB 3865f LTC3865/LTC3865-1 Pin Configuration LTC3865-1 TG1 SW1 MODE/PLLIN VID22 FREQ RUN1 SENSE1+ SENSE1– TOP VIEW 32 31 30 29 28 27 26 25 VOSENSE1 1 24 BOOST1 TK/SS1 2 23 BG1 ITH1 3 22 VIN VID11 4 21 INTVCC 33 SGND VID12 5 20 EXTVCC 19 BG2 ITH2 6 TK/SS2 7 18 PGND VOSENSE2 8 17 BOOST2 TG2 SW2 PGOOD1 PGOOD2 RUN2 VID21 SENSE2+ SENSE2– 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD (5mm s 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W, θJC = 3°C/W EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3865EUH#PBF LTC3865EUH#TRPBF 3865 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3865EUH-1#PBF LTC3865EUH-1#TRPBF 38651 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3865IUH#PBF LTC3865IUH#TRPBF 3865 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C LTC3865IUH-1#PBF LTC3865IUH-1#TRPBF 38651 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C LTC3865EFE#PBF LTC3865EFE#TRPBF LTC3865FE 38-Lead Plastic TSSOP –40°C to 85°C LTC3865IFE#PBF LTC3865IFE#TRPBF LTC3865FE 38-Lead Plastic TSSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3865f LTC3865/LTC3865-1 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VIN = 15V, VRUN1,2 = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops VIN Input Voltage VOSENSE1,2 Output Voltage Sensing (E-Grade) Output Voltage Sensing (I-Grade) 4.5 (Note 4) ITH1,2 Voltage = 1.2V VID11 = VID21 = GND, VID12 = VID22 = GND VID11 = VID21 = GND, VID12 = VID22 = Float VID11 = VID21 = GND, VID12 = VID22 = INTVCC VID11 = VID21 = Float, VID12 = VID22 = GND VID11 = VID21 = Float, VID12 = VID22 = Float VID11 = VID21 = Float, VID12 = VID22 = INTVCC VID11 = VID21 = INTVCC, VID12 = VID22 = GND VID11 = VID21 = INTVCC, VID12 = VID22 = Float VID11 = VID21 = INTVCC, VID12 = VID22 = INTVCC l l l l l l l l l 1.089 0.990 1.188 1.485 0.596 1.782 2.463 3.251 4.925 (Note 4) ITH1,2 Voltage = 1.2V VID11 = VID21 = GND, VID12 = VID22 = GND VID11 = VID21 = GND, VID12 = VID22 = Float VID11 = VID21 = GND, VID12 = VID22 = INTVCC VID11 = VID21 = Float, VID12 = VID22 = GND VID11 = VID21 = Float, VID12 = VID22 = Float VID11 = VID21 = Float, VID12 = VID22 = INTVCC VID11 = VID21 = INTVCC, VID12 = VID22 = GND VID11 = VID21 = INTVCC, VID12 = VID22 = Float VID11 = VID21 = INTVCC, VID12 = VID22 = INTVCC l l l l l l l l l 1.084 0.985 1.182 1.478 0.593 1.773 2.450 3.234 4.900 IOSENSE1,2 Feedback Current (Note 4) VID11 = VID21 = VID12 = VID22 = Float VREFLNREG Reference Voltage Line Regulation VIN = 4.5V to 38V (Note 4) VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V l l 38 V 1.100 1.000 1.200 1.500 0.602 1.800 2.500 3.300 5.000 1.111 1.010 1.212 1.515 0.608 1.818 2.538 3.350 5.075 V V V V V V V V V 1.100 1.000 1.200 1.500 0.602 1.800 2.500 3.300 5.000 1.117 1.015 1.218 1.523 0.611 1.827 2.550 3.366 5.100 V V V V V V V V V –10 –50 nA 0.002 0.02 %/V 0.01 –0.01 0.1 –0.1 % % gm1,2 Transconductance Amplifier gm ITH1,2 = 1.2V; Sink/Source 5µA; (Note 4) 2.2 IQ Input DC Supply Current Normal Mode Shutdown (Note 5) VIN = 15V VRUN1,2 = 0V 3 30 UVLO Undervoltage Lockout on INTVCC VINTVCC Ramping Down UVLOHYS UVLO Hysteresis VOVL Feedback Overvoltage Lockout Measured at VOSENSE1,2 with VID Pins Floating ISENSE Sense Pins Total Current (Each Channel); VSENSE1,2 = 3.3V DFMAX Maximum Duty Cycle In Dropout l 0.64 94 mmho 50 mA µA 3.3 V 0.55 V 0.66 0.68 V ±1 ±2 µA 95 % ITK/SS1,2 Soft-Start Charge Current VTK/SS1,2 = 0V VRUN1,2 RUN Pin On Threshold VRUN1, VRUN2 Rising VRUN1,2HYS RUN Pin On Hysteresis 80 mV IRUN1,2HYS RUN Pin Current Hysteresis 4.5 µA l 0.9 1.3 1.7 µA 1.1 1.22 1.35 V VSENSE(MAX) Maximum Current Sense Threshold (E-Grade) VITH1,2 = 3.3V, ILIM = 0V VITH1,2 = 3.3V, ILIM = Float VITH1,2 = 3.3V, ILIM = INTVCC In Overvoltage Condition l l l l 24 44 68 –63 30 50 75 –53 36 56 82 –43 mV mV mV mV Maximum Current Sense Threshold (I-Grade) VITH1,2 = 3.3V, ILIM = 0V VITH1,2 = 3.3V, ILIM = Float VITH1,2 = 3.3V, ILIM = INTVCC In Overvoltage Condition l l l l 22 42 66 –65 30 50 75 –53 38 58 84 –41 V V V V TG RUP TG Driver Pull-Up On-Resistance TG High 2.6 Ω TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.5 Ω BG RUP BG Driver Pull-Up On-Resistance BG High 3 Ω 3865f LTC3865/LTC3865-1 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VIN = 15V, VRUN1,2 = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS BG RDOWN BG Driver Pull-Down On-Resistance BG Low MIN TYP 1.4 MAX UNITS Ω TG1,2 tr TG1,2 tf TG Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 25 25 ns ns BG1,2 tr BG1,2 tf BG Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 25 25 ns ns TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 30 ns BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver 30 ns tON(MIN) Minimum On-Time (Note 7) 90 ns INTVCC Linear Regulator Internal VCC Voltage 6V < VIN < 38V VLDO INT INTVCC Load Regulation ICC = 0mA to 20mA VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V VLDOHYS EXTVCC Hysteresis VINTVCC 4.8 l 4.5 5.0 5.2 V 0.5 2 % 4.7 50 V 100 200 mV mV Oscillator and Phase-Locked Loop fNOM Nominal Frequency RFREQ = 162k 450 500 550 kHz fLOW Lowest Frequency RFREQ = 0Ω 210 250 290 kHz fHIGH Highest Frequency RFREQ ≥ 325k 650 770 880 kHz RMODE/PLLIN MODE/PLLIN Input Resistance IFREQ 250 Frequency Setting Current 6.5 kΩ 7.5 8.5 µA 0.1 0.3 V ±2 µA –12.5 12.5 % % PGOOD OUTPUT VPGL PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPG PGOOD Trip Level VOSENSE with Respect to Set Regulated Voltage VID11 = VID12 = VID21 = VID22 = Float VOSENSE Ramping Negative VOSENSE Ramping Postitive tPG PGOOD Bad Blanking Time Measured from VID Transitition Edge Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3865E/LTC3865E-1 are guaranteed to meet performance specifications over the 0°C to 85°C operating junction temperature range. Specifications over the –40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3865I/LTC3865I-1 are guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. –7 7 –10 10 100 µs Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3865UH: TJ = TA + (PD • 34°C/W) LTC3865FE: TJ = TA + (PD • 25°C/W) Note 4: The LTC3865/LTC3865-1 are tested in a feedback loop that servos VITH1,2 to a specified voltage and measures the resultant VOSENSE1,2. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peakto-peak ripple current 40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 8: VSENSE(MAX) defaults to 50mV for the LTC3865-1. 3865f LTC3865/LTC3865-1 Typical Performance Characteristics 90 80 80 70 70 BURST DCM 50 EFFICIENCY (%) EFFICIENCY (%) 100 90 CCM 40 30 20 0 0.01 0.1 1 10 LOAD CURRENT (A) BURST 50 DCM 40 CCM 30 70 3 60 POWER LOSS 50 0 0.01 0.1 1 10 LOAD CURRENT (A) 1 30 20 100 10 0 20 30 3865 G25 Load Step (Forced Continuous Mode) Load Step (Pulse-Skipping Mode) VOUT 100mV/DIV ACCOUPLED VOUT 100mV/DIV ACCOUPLED IL 5A/DIV IL 5A/DIV VOUT 100mV/DIV ACCOUPLED IL 5A/DIV ILOAD 5A/DIV 500mA TO 7A ILOAD 5A/DIV 500mA TO 7A ILOAD 5A/DIV 500mA TO 7A 3865 G01 40µs/DIV VIN = 12V VOUT = 1.5V FIGURE 16 CIRCUIT Inductor Current at Light Load 3865 G02 40µs/DIV VIN = 12V VOUT = 1.5V FIGURE 16 CIRCUIT RUN 2V/DIV RUN1 2V/DIV VOUT1 = 1.5V 1Ω LOAD 500mV/DIV VOUT = 1.5V 500mV/DIV Burst Mode OPERATION 5A/DIV VOUT2 = 1.2V 1Ω LOAD 500mV/DIV VTRACK/SS 1V/DIV PULSESKIPPING MODE 5A/DIV 3865 G04 3865 G03 Coincident Tracking Prebiased Output at 1V FORCED CONTINUOUS MODE 5A/DIV 0 INPUT VOLTAGE (V) 3865 G24 Load Step (Burst Mode Operation) VIN = 12V 2µs/DIV VOUT = 1.5V ILOAD = 100mA FIGURE 16 CIRCUIT 2 40 VIN = 12V VOUT = 1.2V FIGURE 16 CIRCUIT 3865 G23 VIN = 12V 40µs/DIV VOUT = 1.5V FIGURE 16 CIRCUIT 4 EFFICIENCY 80 10 100 5 FIGURE 16 CIRCUIT 90 20 VIN = 12V VOUT = 1.5V FIGURE 16 CIRCUIT 10 60 100 POWER LOSS (W) 100 60 Efficiency and Power Loss vs Input Voltage Efficiency vs Load Current EFFICIENCY (%) Efficiency vs Load Current 40ms/DIV 3865 G05 40ms/DIV 3865 G06 3865f LTC3865/LTC3865-1 Typical Performance Characteristics Tracking Up and Down with External Ramp (Forced Continuous Mode) 5 VOUT2 = 1.2V 1Ω LOAD 500mV/DIV 5.00 4.75 3 2 4.50 4.25 4.00 3.75 3.50 1 3865 G07 20ms/DIV VIN = 15V INTVCC VOLTAGE (V) VOUT1 = 1.5V 1Ω LOAD 500mV/DIV INTVCC Line Regulation 5.25 4 QUIESCENT CURRENT (mA) TK/SS1 TK/SS2 2V/DIV Quiescent Current vs Input Voltage without EXTVCC 3.25 0 5 10 25 15 30 20 INPUT VOLTAGE (V) 3.00 40 35 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 3865 G08 ILIM = FLOAT 40 20 ILIM = GND 0 –20 0.5 1 1.5 VITH (V) 70 60 ILIM = FLOAT 50 40 ILIM = GND 30 20 2 10 0 1 4 3 VSENSE COMMON MODE VOLTAGE (V) 0 3865 G10 2 Maximum Current Sense Voltage vs Feedback Voltage (Current Foldback) 80 ILIM = INTVCC 70 60 ILIM = FLOAT 50 40 ILIM = GND 30 20 10 0 5 0 20 40 60 DUTY CYCLE (%) 80 100 3865 G12 TK/SS Pull-Up Current vs Temperature 2.00 100 90 1.75 ILIM = INTVCC 80 70 60 ILIM = FLOAT 50 40 ILIM = GND 30 20 1.50 1.25 1.00 0.75 0.50 0.25 10 0 90 3865 G11 TK/SS CURRENT (µA) 0 MAXIMUM CURRENT SENSE VOLTAGE (mV) VSENSE (mV) 100 ILIM = INTVCC CURRENT SENSE THRESHOLD (mV) 60 –40 Maximum Current Sense Threshold vs Duty Cycle 80 ILIM = INTVCC CURRENT SENSE THRESHOLD (mV) 80 40 3865 G09 Maximum Current Sense Threshold vs Common Mode Voltage Current Sense Threshold vs ITH Voltage 35 0 0.1 0.3 0.4 0.5 0.2 FEEDBACK VOLTAGE (V) 0.6 3865 G13 0 –50 –25 75 50 25 TEMPERATURE (°C) 0 100 125 3865 G14 3865f LTC3865/LTC3865-1 Typical Performance Characteristics Shutdown (RUN) Threshold vs Temperature 1.5 1.3 ON 1.2 OFF 1.1 1.0 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 1000 900 0.606 OSCILLATOR FREQUENCY (kHz) REGULATED FEEDBACK VOLTAGE (V) 0.608 1.4 RUN PIN VOLTAGE (V) Oscillator Frequency vs Temperature Regulated Feedback Voltage vs Temperature 0.604 0.602 0.600 0.598 50 25 75 0 TEMPERATURE (°C) 100 3865 G15 5 700 600 VFREQ = 1.2V 500 400 VFREQ = 0V 300 200 0.596 –50 –25 125 VFREQ = INTVCC 800 100 –50 125 –25 0 25 50 75 TEMPERATURE (°C) 3865 G16 Undervoltage Lockout Threshold (INTVCC) vs Temperature 100 125 3865 G17 Oscillator Frequency vs Input Voltage Shutdown Current vs Input Voltage 50 550 540 RISING 40 3 2 1 INPUT CURRENT (µA) 530 FALLING FREQUENCY (kHz) INTVCC VOLTAGE (V) 4 520 510 500 490 480 30 20 10 470 460 0 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 450 10 4 22 28 16 INPUT VOLTAGE (V) 34 3865 G18 QUIESCENT CURRENT (mA) SHUTDOWN CURRENT (µA) 5 40 30 20 10 –25 50 0 75 25 TEMPERATURE (°C) 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 100 125 3865 G21 35 40 3865 G20 Quiescent Current vs Temperature without EXTVCC VIN = 15V 0 –50 0 3865 G19 Shutdown Current vs Temperature 50 40 VIN = 15V 4 3 2 1 0 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 3865 G22 3865f LTC3865/LTC3865-1 Pin Functions (QFN/TSSOP) VOSENSE1, VOSENSE2 (Pins 1, 8/Pins 5, 13): When the internal programmable resistive divider is used, these pins must be connected to their corresponding outputs. When an external resistive divider is used, these pins are used for error amplifier feedback inputs. They receive the remotely sensed feedback voltages for each channel directly from the outputs or from the external divider across the outputs. TK/SS1, TK/SS2 (Pins 2, 7/Pins 6, 12): Output Voltage Tracking and Soft-Start Inputs. When one channel is configured to be master of the two channels, a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When a channel is configured to be the slave of the two channels, the output voltage ramp of the master channel can be reproduced by a resistor divider and applied to this pin of the slave channel. Internal soft-start currents of 1.3µA charge the soft-start capacitors. ITH1, ITH2 (Pins 3, 6/Pins 7, 11): Current Control Thresholds and Error Amplifier Compensation Points. Each associated channels’ current comparator tripping threshold increases with its ITH control voltage. VID11, VID12, VID21, VID22 (Pins 4, 5, 12, 28/ Pins 9, 10, 18, 37): VID Inputs for Output Voltage Programming. Tie these pins to INTVCC, GND or leave them floating to set the output voltages. ILIM (Pin 13/Pin 19) (LTC3865 Only): Current Comparator Sense Voltage Range Inputs. This pin can be tied to SGND, FLOAT or INTVCC to set the maximum current sense threshold for each comparator. Current comparator sense voltage range of the LTC3865-1 is set to default value of 50mV. PGOOD (Pin 14 LTC3865/NA): Co-Bonded Power Good Indicator Output for LTC3865 in QFN Package. Open-drain logic output that is pulled to ground when either channel output exceeds ±10% regulation window, after the internal 20µs power bad mask timer expires. PGOOD1, PGOOD2 (Pins 14, 13 LTC3865-1/Pins 21, 20): Separate Power Good Indicator Outputs for LTC3865-1 in QFN package and LTC3865 in FE package. Open-drain logic output that is pulled to ground when the corresponding channel output exceeds ±10% regulation window, after the internal 20µs power bad mask timer expires. PGND (Pin 18/NA): Power Ground Pin. Connect this pin closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of CVCC and the (–) terminal of CIN. EXTVCC (Pin 20/Pin 28): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 4.7V. Do not exceed 6V on this pin. INTVCC (Pin 21/Pin 29): Internal 5V Regulator Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. VIN (Pin 22/Pin 30): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1µF to 1µF). BG1, BG2 (Pins 23, 19/Pin 31, 27): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-channel MOSFETs between PGND and INTVCC. BOOST1, BOOST2 (Pins 24, 17/Pins 33, 25): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. TG1, TG2 (Pins 25, 16/Pins 34, 23): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch nodes voltages. SW1, SW2 (Pins 26, 15/Pins 35, 22): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. 3865f LTC3865/LTC3865-1 Pin Functions (QFN/TSSOP) MODE/PLLIN (Pin 27/Pin 36): Force Continuous Mode, Burst Mode or Pulse-Skip Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels in continuous mode of operation. Connect to INTVCC to enable pulse-skip mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator with the clock on this pin. FREQ (Pin 29/Pin 38): This pin sets the frequency of the internal oscillator. A constant current of 7.5µA is flowing out of this pin and a resistor connected to this pin sets its DC voltage, which in turn, sets the frequency of the internal oscillator. RUN1, RUN2 (Pins 30, 11/Pins 1, 17): Run Control Inputs. A voltage above 1.2V on either pin turns on the IC. However, forcing either of these pins below 1.2V causes the IC to shut down the circuitry required for that particular channel. There are 1µA pull-up currents for these pins. Once the RUN pin rises above 1.2V, an additional 4.5µA pull-up current is added to the pin. SENSE1+, SENSE2+ (Pins 31, 10/Pins 2, 16): Current Sense Comparator Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing networks or current sensing resistors. SENSE1–, SENSE2– (Pins 32, 9/Pin 3, 15): Current Sense Comparator Inputs. The (–) inputs to the current comparators are connected to the outputs. SGND (Pin 33/Pin 8): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. Pin 33 is the Exposed Pad and available for QFN package. SGND (Exposed Pad Pin 33/ Exposed Pad Pin 39): Signal Ground. Must be soldered to PCB, providing a local ground for the control components of the IC, and be tied to the PGND pin under the IC. PGND1, PGND2 (NA/Pins 32, 26): Power Ground Pin. Connect this pin closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of CVCC and the (–) terminal of CIN. 3865f 10 LTC3865/LTC3865-1 FUNCTIONAL Diagram FREQ/FREQ MODE/PLLIN VID1 VID2 EXTVCC VIN 7.5µA + 4.7V INPUT VID LOGIC AND RESISTIVE DIVIDERS MODE/SYNC DETECT PLL-SYNC AND LPF + – F 0.6V CIN 5V REG + – VIN INTVCC INTVCC F BOOST OSC BURSTEN S R 3k + ON – ICMP + – TG FCNT Q IREV CB M1 SW SWITCH LOGIC AND ANTISHOOT THROUGH SENSE+ L1 SENSE– + RUN M2 CVCC SLOPE COMPENSATION PGND PGOOD INTVCC UVLO + 1 51k ITHB SLOPE RECOVERY ACTIVE CLAMP 0.54V VOSENSE UV – SLEEP VIN SGND + VFB – 0.66V OV – – + SS + – RUN + 1.3µA EA – + + 0.6V REF COUT BG OV ILIM VOUT DB 0.5V 1.2V 1µA 0.55V ITH RC CC1 RUN TK/SS CSS 3865 FBD 3865f 11 LTC3865/LTC3865-1 Operation Main Control Loop The LTC3865/LTC3865-1 are constant-frequency, current mode step-down controllers with two channels operating 180 degrees out-of-phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier, EA (refer to the Functional Diagram). VFB is the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in feedback voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator IREV, or the beginning of the next cycle. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 4.7V, an internal 5V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as one of the LTC3865/LTC3865-1 switching regulator outputs. Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period every third cycle to allow CB to recharge. However, it is recommended that a load be present during the drop-out transition to ensure CB is recharged. Shutdown and Start-Up (RUN1, RUN2 and TK/SS1, TK/SS2 Pins) The two channels of the LTC3865/LTC3865-1 can be independently shut down using the RUN1 and RUN2 pins. Pulling either of these pins below 1.2V shuts down the main control loop for that controller. Pulling both pins low disables both controllers and most internal circuits, including the INTVCC regulator. Releasing either RUN pin allows an internal 1µA current to pull up the pin and enable that controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of each controller’s output voltage VOUT is controlled by the voltage on the TK/SS1 and TK/SS2 pins. When the voltage on the TK/SS pin is less than the 0.6V internal reference, the LTC3865 regulates the VFB voltage to the TK/SS pin voltage instead of the 0.6V reference. This allows the TK/SS pin to be used to program a softstart by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.3µA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.6V (and beyond), the output voltage, VOUT , rises smoothly from zero to its final value. Alternatively the TK/SS pin can be used to cause the start-up of VOUT to “track” that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the corresponding RUN pin is pulled low to disable a controller, or when INTVCC drops below its undervoltage lockout threshold of 3.3V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, both controllers are disabled and the external MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse-Skipping or Continuous Conduction) The LTC3865/LTC3865-1 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulseskipping mode, or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN 3865f 12 LTC3865/LTC3865-1 Operation pin to a DC voltage below 0.6V (e.g., SGND). To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTVCC. To select Burst Mode operation, float the MODE/PLLIN pin. When a controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling “sleep” mode) and both external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTVCC, the LTC3865 operates in PWM pulse-skipping mode at light loads. At very light loads, the current comparator, ICMP , may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3865’s controllers can be selected using the FREQ pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller’s operating frequency from 250kHz to 770kHz. There is a precision 7.5µA current flow out of FREQ pin that user can program the controller’s switching frequency with a single resistor to SGND. A curve is provided later in the application section showing the relationship between the voltage on the FREQ pin and switching frequency. A phase-locked loop (PLL) is integrated on the LTC3865 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when it is synchronized. The PLL loop filter network is integrated inside the LTC3865/LTC3865-1. The phase-locked loop is capable of locking any frequency within the range of 250kHz to 770kHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock. Power Good (PGOOD Pins) On the LTC3865 (UH32 package), the PGOOD pin is bonded to the open drains of two individual internal Nchannel MOSFETs. When either VOSENSE voltage is not within ±10% of the programmed voltage, the PGOOD pin is pulled low. The PGOOD pin is also pulled low when either RUN pin is below 1.2V or when the LTC3865 is in the soft-start or tracking phase. The PGOOD pin will flag power good immediately when both VOSENSE are within the ±10% of the programmed output voltage window. However, there is an internal 20µs power bad mask when either VOSENSE goes out the ±10% window. The internal 3865f 13 LTC3865/LTC3865-1 Operation power bad mask is 100µs when there are any VID transitions. On the LTC3865‑1 (UH32 package) or the LTC3865 (FE38 package), each channel has its own PGOOD pin. Therefore, the PGOOD pins now only respond to their own channels. The PGOOD pins are allowed to be pulled up by external resistors to sources of up to 6V. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the reverse current limit for the overvoltage condition is reached. The bottom MOSFET will be turned on again at the next clock and be turned off when the reverse current limit is reached again. This process repeats until the overvoltage condition is cleared. Output Voltage Programming The output voltages of both channels of the LTC3865/ LTC3865-1 can be programmed to a preset value. There are two VID pins for each channel and by connecting these pins to INTVCC, GND, or by floating them, the output voltages can be set to the values in Table 1. Table 1. Programming of Output Voltage VID11/VID21 VID12/VID22 VOUT1/VOUT2 (V) INTVCC INTVCC 5.0 INTVCC Float 3.3 INTVCC GND 2.5 Float INTVCC 1.8 Float Float 0.6 or External Divider Float GND 1.5 GND INTVCC 1.2 GND Float 1.0 GND GND 1.1 Applications Information The Typical Application on the first page is a basic LTC3865 application circuit. The LTC3865 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Next, the power MOSFETs are selected. Finally, input and output capacitors are selected. Current Limit Programming The ILIM pin is a tri-level logic input which sets the maximum current limit of the controller. When ILIM is either grounded, floated or tied to INTVCC, the typical value for the maximum current sense threshold will be 30mV, 50mV or 75mV, respectively. Which setting should be used? For the best current limit accuracy, use the 75mV setting. The 30mV setting will allow for the use of very low DCR inductors or sense resistors, but at the expense of current limit accuracy. The 50mV setting is a good balance between the two. For single output dual phase applications, use the 50mV or 75mV setting for optimal current sharing. SENSE+ and SENSE– Pins The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 0V to 5V. Both SENSE pins are high impedance inputs with small base currents of less than 1µA. When the SENSE pins ramp up from 0V to 1.4V, the small base currents flow out of the SENSE pins. When the SENSE pins ramp down from 5V to 1.1V, the small base currents flow into the SENSE pins. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. 3865f 14 LTC3865/LTC3865-1 Applications Information Filter components mutual to the sense lines should be placed close to the LTC3865/LTC3865-1, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If DCR sensing is used (Figure 2b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1 should be placed close to the IC pins. VIN INTVCC VIN SENSE RESISTOR PLUS PARASITIC INDUCTANCE BOOST TG RS LTC3865 SW BG SENSE– SGND VOUT CF • 2RF ≤ ESL/RS POLE-ZERO CANCELLATION PGND SENSE+ ESL RF CF RF FILTER COMPONENTS PLACED NEAR SENSE PINS 3865 F02a (2a) Using a Resistor to Sense Current TO SENSE FILTER, NEXT TO THE CONTROLLER 3865 F01 COUT INDUCTOR OR RSENSE Figure 1. Sense Lines Placement with Inductor or Sense Resistor Low Value Resistors Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. RSENSE is chosen based on the required output current. The current comparator has a maximum threshold VSENSE(MAX) determined by the ILIM setting. The input common mode range of the current comparator is 0V to 5V. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-topeak ripple current, ∆IL. To calculate the sense resistor value, use the equation: VSENSE(MAX ) ∆I I(MAX ) + L 2 Because of possible PCB noise in the current sensing loop, the AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE also needs to be checked in the design to get a good signal-to-noise ratio. In general, for a reasonably good PCB layout, a 15mV ∆VSENSE voltage is recommended as a conservative number to start with, either for RSENSE or DCR sensing applications. RSENSE = VIN INTVCC VIN BOOST INDUCTOR TG LTC3865 L SW DCR VOUT BG PGND R1 SENSE+ C1* R2 SENSE– SGND *PLACE C1 NEAR SENSE+, SENSE– PINS R1||R2 • C1 = L DCR RSENSE(EQ) = DCR R2 R1 + R2 3865 F02b (2b) Using the Inductor DCR to Sense Current Figure 2. Two Different Methods of Sensing Current For previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mV for the LTC1628 / LTC3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. For today’s highest current density solutions, however, the value of the sense resistor can be less than 1mΩ and the peak sense voltage can be as low as 20mV. In addition, inductor ripple currents greater than 50% with operation up to 1MHz are becoming more common. Under these conditions the voltage drop across the sense resistor’s parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 2a. In previous generations of controllers, a small RC filter placed near the IC was commonly used to reduce the effects of capacitive and inductive noise coupled in 3865f 15 LTC3865/LTC3865-1 Applications Information the sense traces on the PCB. A typical filter consists of two series 10Ω resistors connected to a parallel 1000pF capacitor, resulting in a time constant of 20ns. This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 3 illustrates the voltage waveform across a 2mΩ sense resistor with a 2010 footprint for the 1.2V/15A converter operating at 100% load. The waveform is the superposition of a purely resistive component and a purely inductive component. It was measured using two scope probes and waveform math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: ESL = VESL(STEP) tON • tOFF ∆IL tON + tOFF If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resulting waveform looks resistive again, as shown in Figure 4. For applications using low maximum sense voltages, check the sense resistor manufacturer’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use the equation above to determine the ESL. However, do not over filter. Keep the RC time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on VRSENSE. The above generally applies to high density/high current applications where I(MAX) >10A and low values of inductors are used. For applications where I(MAX) < 10A, set RF to 10Ω and CF to 1000pF. This will provide a good starting point. The filter components need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair and Kelvin connected to the sense resistor. Inductor DCR Sensing VSENSE 20mV/DIV VESL(STEP) 500ns/DIV 3865 F03 Figure 3. Voltage Waveform Measured Directly Across the Sense Resistor VSENSE 20mV/DIV 500ns/DIV 3865 F04 Figure 4. Voltage Waveform Measured After the Sense Resistor Filter. CF = 1000pF, RF = 100Ω For applications requiring the highest possible efficiency at high load currents, the LTC3865/LTC3865-1 are capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to DCR sensing. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not 3865f 16 LTC3865/LTC3865-1 Applications Information always the same and varies with temperature; consult the manufacturers’ data sheets for detailed information. Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: RSENSE(EQUIV ) = VSENSE(MAX ) ∆I I(MAX ) + L 2 To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold (VSENSE(MAX)) in the Electrical Characteristics table (24mV, 44mV or 68mV, depending on the state of the ILIM pin). Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A conservative value for TL(MAX) is 100°C. To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: RD = RSENSE(EQUIV ) DCR(MAX ) at TL(MAX ) C1 is usually selected to be in the range of 0.047µF to 0.47µF. This forces R1||R2 to around 2kΩ, reducing error that might have been caused by the SENSE pins’ ±1µA current. The equivalent resistance R1||R2 is scaled to the room temperature inductance and maximum DCR: R1|| R2 = L (DCR at 20°C ) • C1 The sense resistor values are: R1 = R1|| R2 R1 • RD ; R2 = RD 1 − RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS R1= (V IN(MAX ) − VOUT R1 )• V OUT Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. To maintain a good signal to noise ratio for the current sense signal, use a minimum ∆VSENSE of 10mV to 15mV. For a DCR sensing application, the actual ripple voltage will be determined by the equation: ∆VSENSE = VIN − VOUT VOUT R1• C1 VIN • fOSC Slope Compensation and Inductor Peak Current Slope compensation provides stability in constantfrequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40%. However, the LTC3865/LTC3865-1 use a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency fOSC directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VIN – VOUT VIN fOSC • L 3865f 17 LTC3865/LTC3865-1 Applications Information Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC • IRIPPLE VIN Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the onresistance, RDS(ON) , Miller capacitance, CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected Synchronous Switch Duty Cycle = VIN – VOUT VIN The MOSFET power dissipations at maximum output current are given by: VOUT 2 IMAX ) (1+ d) RDS(ON) + ( VIN 2 I ( VIN ) MAX (RDR )(CMILLER ) • 2 1 1 • fOSC + VINTVCC – VTH(MIN) VTH(MIN) PMAIN = Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3865/LTC3865-1: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. VOUT VIN PSYNC = VIN – VOUT 2 IMAX ) (1+ d) RDS(ON) ( VIN where d is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTH(MIN) is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, 3865f 18 LTC3865/LTC3865-1 Applications Information which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + d) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but d = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diodes conduct during the dead time between the conduction of the two power MOSFETs. These prevent the body diodes of the bottom MOSFETs from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. Soft-Start and Tracking The LTC3865/LTC3865-1 have the ability to either soft-start by themselves with a capacitor or track the output of another channel or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown state if its RUN pin voltage is below 1.2V. Its TK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.2V, the channel powers up. A soft-start current of 1.3µA then starts to charge its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.6V on the TK/SS pin. The total soft-start time can be calculated as: t SOFTSTART = 0.6 • CSS 1.3 µA Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.54V. The output ripple is minimized during the 40mV forced continuous mode window ensuring a clean PGOOD signal. When the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC3865/LTC3865-1 are forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.54V regardless of the setting on the MODE/PLLIN pin. However, the LTC3865/LTC3865-1 should always be set in force continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, the corresponding channel will operate in discontinuous mode. Output Voltage Tracking The LTC3865/LTC3865-1 allow the user to program how its output ramps up and down by means of the TK/SS pins. Through these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown in Figure 5. In the following discussions, VOUT1 refers to the LTC3865/LTC3865-1’s output 1 as a master channel and VOUT2 refers to the LTC3865/LTC3865‑1’s output 2 as a slave channel. In practice, though, either phase can be used as the master. To implement the coincident tracking in Figure 5a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TK/SS pin of the slave channel. The ratio of this divider should be the same as that of the slave channel’s internal feedback divider 3865f 19 LTC3865/LTC3865-1 Applications Information VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 VOUT2 TIME TIME (5a) Coincident Tracking 3865 F05 (5b) Ratiometric Tracking Figure 5. Two Different Modes of Output Voltage Tracking VOUT1 TO TK/SS2 PIN VOUT1 VOUT2 nR3 R1 R3 TO TK/SS2 PIN TO TO EA1 EA2 nR4 R2 R4 VOUT2 nR1 R1 R3 TO TO EA1 EA2 nR2 R2 R4 38551 F06 (6a) Coincident Tracking Setup (6b) Ratiometric Tracking Setup Figure 6. Setup for Coincident and Ratiometric Tracking I I + D1 D2 EA2 TK/SS2 0.6V – 3865 F07 D3 VFB2 Figure 7. Equivalent Input Circuit of Error Amplifier shown in Figure 6a. In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking, the ratio of the VOUT2 divider should be exactly the same as the master channel’s internal feedback divider. By selecting different resistors, the LTC3865/LTC3865-1 can achieve different modes of tracking including the two in Figure 5. So which mode should be programmed? The coincident mode offers better output regulation. This can be better understood with the help of Figure 7. At the input stage of the slave channel’s error amplifier, two common anode diodes are used to clamp the equivalent reference 20 voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same magnitude. In coincident mode, the TK/SS voltage is substantially higher than 0.6V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB2 and the internal precision 0.6V at steady state. In the ratiometric mode, however, TK/SS equals 0.6V at steady state. D1 will divert part of the bias current to make VFB2 slightly lower than 0.6V. Although this error is minimized by the exponential I-V characteristics of the diode, it does impose a finite amount of output voltage deviation. 3865f LTC3865/LTC3865-1 Applications Information When the master channel’s output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. INTVCC Regulators and EXTVCC The LTC3865 features a true PMOS LDO that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC3865/LTC3865-1’s internal circuitry. The linear regulator regulates the voltage at the INTVCC pin to 5V when VIN is greater than 5.5V. EXTVCC connects to INTVCC through a P-channel MOSFET and can supply the needed power when its voltage is higher than 4.7V. Each of these can supply a peak current of 80mA and must be bypassed to ground with a minimum of 4.7µF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3865/LTC3865-1 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the 5V linear regulator or EXTVCC. When the voltage on the EXTVCC pin is less than 4.7V, the linear regulator is enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3865 INTVCC current is limited to less than 42mA from a 38V supply in the UH package and not using the EXTVCC supply: TJ = 70°C + (42mA)(38V)(34°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the INTVCC linear regulator is turned off and the EXTVCC is connected to the INTVCC. The EXTVCC remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using the EXTVCC allows the MOSFET driver and control power to be derived from one of the LTC3865/LTC3865-1’s switching regulator outputs during normal operation and from the INTVCC when the output is out of regulation (e.g., start-up, short-circuit). If more current is required through the EXTVCC than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC < VIN. Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to: TJ = 70°C + (42mA)(5V)(34°C/W) = 77°C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If a 5V external supply is available, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. 3865f 21 LTC3865/LTC3865-1 Applications Information For applications where the main input power is below 5V, tie the VIN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown in Figure 8 to minimize the voltage drop caused by the gate charge current. This will override the INTVCC linear regulator and will prevent INTVCC from dropping too low due to the dropout voltage. Make sure the INTVCC voltage is at or exceeds the RDS(ON) test voltage for the MOSFET which is typically 4.5V for logic-level devices. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors, CB, connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged through external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor, CB, needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. VIN LTC3865 INTVCC RVIN 1Ω CINTVCC 4.7µF + 5V CIN 3865 F08 Figure 8. Setup for a 5V Input Undervoltage Lockout The LTC3865/LTC3865-1 have two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.3V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 550mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pins have a precision turn-on reference of 1.2V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.2V. One can program the hysteresis of the run comparator by adjusting the values of the resistive divider. For accurate VIN undervoltage detection, VIN needs to be higher than 4.5V. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-ofphase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the 3865f 22 LTC3865/LTC3865-1 Applications Information maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Re quired IRMS ≈ 1/ 2 IMAX ( VOUT )( VIN – VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3865, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the LTC3865/LTC3865-1 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1µF to 1µF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3865/LTC3865-1, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by: 1 ∆VOUT ≈ IRIPPLE ESR + 8 fCOUT where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Setting Output Voltage The LTC3865/LTC3865-1 output voltages are each set by the voltages at VID pins. Each of the VID pins can be floated, or INTVCC or grounded, depending on what preset voltages are needed at the output (Table 1). If the desired output voltage is not one of the preset values, select 0.6V and use 1% resistors to divide VOUT , as shown in Figure 9. The regulated output voltage is determined by: R VOUT = 0.6 V • 1+ B RA To improve the frequency response, a feed-forward capacitor, CFF , may be used. Great care should be taken to route the VOSENSE line away from noise sources, such as the inductor or the SW line. VOUT 1/2 LTC3865 RB CFF VOSENSE RA 3865 F09 Figure 9. Setting Output Voltage 3865f 23 LTC3865/LTC3865-1 Applications Information Fault Conditions: Current Limit and Current Foldback The LTC3865/LTC3865-1 include current foldback to help limit load current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start or tracking up. Under short-circuit conditions with very low duty cycles, the LTC3865 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC3865/LTC3865-1 (≈ 90ns), the input voltage and inductor value: ∆IL(SC) = tON(MIN) • VIN L The resulting short-circuit current is: ISC = 1/ 3 VSENSE(MAX ) RSENSE 1 – ∆IL(SC) 2 Phase-Locked Loop and Frequency Synchronization The LTC3865/LTC3865-1 have a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The turn-on of controller 2’s top MOSFET is thus 180 degrees out-of-phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. There is a precision 7.5µA of current flowing out of FREQ pin. This allows the user to use a single resistor to SGND to set the switching frequency when no external clock is applied to the MODE/PLLIN pin. The internal switch between FREQ pin and the integrated PLL filter network is on, allowing the filter network to be at the same voltage potential as of FREQ pin. The relationship between the voltage on the FREQ pin and the operating frequency is shown in Figure 10 and specified in the Electrical Characteristic table. If an external clock is detected on the MODE/PLLIN pin, the internal switch mentioned above will turn off and isolate the influence of FREQ pin. Note that the LTC3865 can only be synchronized to an external clock whose frequency is within range of the LTC3865/LTC3865-1’s internal VCO. This is guaranteed to be between 250kHz and 770kHz. A simplified block diagram is shown in Figure 11. 2.4V 5V 900 7.5µA 800 FREQ 700 FREQUENCY (kHz) RSET 600 EXTERNAL OSCILLATOR 500 400 MODE/ PLLIN DIGITAL SYNC PHASE/ FREQUENCY DETECTOR VCO 300 200 100 0 3865 F11 0 0.5 1 1.5 FREQ PIN VOLTAGE (V) 2 2.5 3865 F10 Figure 11. Phase-Locked Loop Block Diagram Figure 10. Relationship Between Oscillator Frequency and Voltage at the FREQ Pin 3865f 24 LTC3865/LTC3865-1 Applications Information If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the filter network. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the filter network. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. Typically, the external clock (on MODE/PLLIN pin) input high threshold is 1.6V, while the input low thres-hold is 1V. The external clock should not be applied when the IC is in shutdown. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC3865/LTC3865-1 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that tON(MIN) < VOUT VIN( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3865/LTC3865-1 is approximately 90ns, with reasonably good PCB layout, minimum 30% inductor current ripple and at least 10mV to 15mV ripple on the current sense signal. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on-time gradually increases to 130ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3865/LTC3865-1 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1.The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VIN current typically results in a small (<0.1%) loss. 2.INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. 3865f 25 LTC3865/LTC3865-1 Applications Information Supplying INTVCC power through EXTVCC from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3.I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor. In continuous mode, the average output current flows through L and RSENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A for a 5V output, or a 3% to 12% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4.Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20µF to 40µF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. The LTC3865 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. 3865f 26 LTC3865/LTC3865-1 Applications Information The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD . Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 12. Figure 13 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1.Are the top N-channel MOSFETs M1 and M3 located within 1 cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2.Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The VOSENSE and ITH traces should be as short as possible. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3.Do the LTC3865 VOSENSE pins connect to the (+) terminals of COUT? The connections between the VOSENSE pins and COUT should not be along the high current input feeds from the input capacitor(s). 4.Are the SENSE+ and SENSE– leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5.Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 3865f 27 LTC3865/LTC3865-1 Applications Information VID11 ITH1 LTC3865 RPU2 PGOOD PGOOD VPULL-UP VID12 VID21 L1 VID22 SENSE1+ – CB1 M1 BOOST1 FREQ ILIM BG1 MODE/PLLIN RIN VIN INTVCC SENSE2+ BG2 VOSENSE2 BOOST2 ITH2 TK/SS2 CIN CINTVCC CERAMIC + SENSE2– COUT1 M3 GND M4 + EXTVCC D1 CERAMIC CVIN PGND SGND M2 + VIN RUN1 RUN2 VOUT1 SW1 SENSE1 fIN RSENSE TG1 + VOSENSE1 TK/SS1 COUT2 D2 CB2 SW2 RSENSE TG2 VOUT2 L2 3865 F12 Figure 12. Recommended Printed Circuit Layout Diagram SW1 L1 D1 RSENSE1 VOUT1 COUT1 RL1 VIN RIN CIN SW2 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. D2 L2 RSENSE2 VOUT2 COUT2 RL2 3865 F13 Figure 13. Branch Current Waveforms 28 3865f LTC3865/LTC3865-1 Applications Information 6.Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposite channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3865/LTC3865-1 and occupy minimum PC trace area. If DCR sensing is used, place the top resistor (Figure 2b, R1) close to the switching node. 7.Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. PC Board Layout Debugging Start with one controller at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. 3865f 29 LTC3865/LTC3865-1 Applications Information Design Example As a design example for a 2-channel medium current regulator, assume VIN = 12V (nominal), VIN = 20V (maximum), VOUT1 = 3.3V, VOUT2 = 1.8V, IMAX1,2 = 5A, and f = 500kHz (see Figure 14). The regulated output voltages are set by connecting VID11 and VID22 to INTVCC and floating VID12 and VID21. The frequency is set by biasing the FREQ pin to 1.2V (see Figure 9). The inductance values are based on a 35% maximum ripple current assumption (1.75A for each channel). The highest value of ripple current occurs at the maximum input voltage: VOUT VOUT L= 1− f • ∆IL (MAX ) VIN(MAX ) 4.7µF M1 0.1µF D3 LTC3865 MODE/PLLIN ILIM The minimum on-time occurs on Channel 1 at the maximum VIN, and should not be less than 90ns: 0.1µF RUN1 TK/SS1 100pF VIN(MAX ) f = 1.8 V = 180ns 20 V(500kHz) + 0.1µF D4 VIN 7V TO 20V 22µF 50V M2 0.1µF L2 2.2µH BOOST2 SW2 BG2 3.65k 1% PGND 0.1µF RUN2 SENSE2– SENSE1 VID11 VID12 VOSENSE1 ITH1 1800pF VOUT SENSE2+ – VOUT1 3.3V 5A tON(MIN) = FREQ SENSE1+ 4.75k 1% Channel 1 will have 1.45A (29%) ripple, and Channel 2 will have 1.4A (28%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or 5.725A for Channel 1 and 5.7A for Channel 2. VIN PGOOD EXTVCC INTVCC TG1 TG2 BG1 5.49k 1% COUT1 100µF s2 VOUT VOUT 1− f •L VIN(NOM) 1µF BOOST1 SW1 1.37k 1% ∆IL(NOM) = 2.2Ω L1 3.3µH Channel 1 will require 3.2µH, and Channel 2 will require 1.9µH. The next highest standard values are 3.3µH and 2.2µH. At the nominal input voltage (12V), the ripple will be: 1.58k 1% VID21 VID22 VOSENSE2 ITH2 SGND TK/SS2 0.1µF VOUT2 1.8V 5A 2200pF 162k 1% 5.49k 1% L1, L2: COILTRONICS HCP0703 M1, M2: VISHAY SILICONIX Si4816BDY COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM 100pF COUT2 100µF s2 3865 F14 Figure 14. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter 3865f 30 LTC3865/LTC3865-1 Applications Information With ILIM floating, the equivalent RSENSE resistor value can be calculated by using the minimum value for the maximum current sense threshold (44mV). VSENSE(MIN) RSENSE(EQUIV ) = ∆IL(NOM) ILOAD(MAX ) + 2 44mV = @ 7.7mΩ 1.5A 5A + 2 The equivalent RSENSE is the same for Channel 2. The Coiltronics (Cooper) HCP0703-2R2 (20mΩ DCRMAX at 20°C) and HCP0703-3R3 (30mΩ DCRMAX at 20°C) are chosen. At 100°C, the estimated maximum DCR values are 26.4mΩ and 39.6mΩ. The divider ratios are: RD = and RSENSE(EQUIV ) DCRMAX at TL(MAX ) = 7.7mΩ = 0.3; 26.4mΩ 7.7mΩ @ 0.2 39.6 mΩ For each channel, 0.1µF is selected for C1. L 2.2µH = (DCRMAX at 20°C) • C1 20 mΩ • 0.1µF 3.3 µH = 1.1k = 1.1k ; and 30 mΩ • 0.1µF R1|| R2 = The power loss in R1 at the maximum input voltage is: PLOSS R1= R1 (20 V − 3.3V) • 3.3V = = 10mW 5.5k The respective values for Channel 2 are R1 = 3.66k, R2 = 1.57k; and PLOSS R1 = 8mW. Burst Mode operation is chosen for high light load efficiency (Figure 15) by floating the MODE/PLLIN pin. Power loss due to the DCR sensing network is slightly higher at light loads than would have been the case with a suitable sense resistor (8mΩ). At heavier loads, DCR sensing provides higher efficiency. The power dissipation on the topside MOSFET can be easily estimated. Choosing a Siliconix Si4816BDY dual MOSFET results in: RDS(ON) = 0.023Ω/0.016Ω, CMILLER @ 100pF. At maximum input voltage with T(estimated) = 50°C: 3.3V 2 (5) [1+ (0.005)(50°C – 25°C)] • 20 V (0.023Ω) + (20V )2 52A (2Ω)(100pF ) • PMAIN = 1 1 5 – 2.3 + 2.3 ( 500kHz ) = 186 mW 100 EFFICIENCY (%) EFFICIENCY 1 80 70 60 POWER LOSS 50 40 0.01 0.1 DCR 8mΩ 0.1 1 LOAD CURRENT (mA) 10 POWER LOSS (mW) R1|| R2 1.1k = @ 5.5 k ; RD 0.2 R1 • RD 5.5 k • 0.2 = R2 = @ 1.37k 1 − RD 1 − 0.2 10 90 For channel 1, the DCRSENSE filter/divider values are: R1 = ( VIN(MAX ) − VOUT ) • VOUT 0.01 3865 F16 Figure 15. Design Example Efficiency vs Load 3865f 31 LTC3865/LTC3865-1 Applications Information A short-circuit to ground will result in a folded back current of: ISC = CIN is chosen for an RMS current rating of at least 2A at temperature assuming only channel 1 or 2 is on. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: (1/ 3) 50mV – 1 90ns(20V) = 1.8 A 2 0.008Ω 3.3 µH with a typical value of RDS(ON) and d = (0.005/°C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is: VORIPPLE = RESR (∆IL) = 0.02Ω(1.5A) = 30mVP-P 20 V – 3.3V 2 1.8 A ) (1.125) ( 0.016Ω ) ( 20 V = 48mW PSYNC = which is less than under full-load conditions. TYPICAL APPLICATIONS 10µF 35V + 10µF 35V 2.2Ω 22µF 50V VIN 4.5V TO 24V 1µF 4.7µF L2 0.47µH D1 Q1 RJK0305DPB D3 0.1µF Q2 RJK0330DPB BG1 COUT1 100µF 100Ω 1000pF RUN1 + 1000pF 10k LTC3865 MODE/PLLIN ILIM 100Ω COUT2,3 TG2 BOOST1 SW1 2mΩ VOUT1 1.5V 15A VIN PGOOD EXTVCC INTVCC TG1 100pF SENSE1+ D4 BOOST2 SW2 Q4 RJK0330DPB BG2 PGND FREQ SENSE2+ 100Ω RUN2 1000pF SENSE1– SENSE2– VID11 VID21 VID12 VID22 VOSENSE2 VOSENSE1 ITH2 ITH1 TK/SS1 SGND TK/SS2 0.1µF Q3 RJK0305DPB 0.1µF 0.1µF L2 0.47µH D2 2mΩ 100Ω 1000pF 162k 1% 15k D1, D2: VISHAY B340A L1, L2: VISHAY IHLP4040DZERR47M11 COUT1, COUT4: TDK C322JX5R0J107MT COUT2, COUT3, COUT5, COUT6: SANYO 4TPE 220µF COUT5,6 100pF + VOUT2 1.2V 15A COUT4 100µF 3865 F16 Figure 16. 1.5V/15A, 1.2V/15A Converter Using Sense Resistors 3865f 32 LTC3865/LTC3865-1 TYPICAL APPLICATIONS 3.3µF 50V CIN2 1µF 2.2Ω 4.7µF D3 CMDSH-3 HAT2266H 0.004Ω VIN PGOOD EXTVCC INTVCC TG1 TG2 0.1µF L1 2.2µH BOOST1 SW1 HAT2266H PLLIN 400kHz 100Ω 1nF COUT1 220µF s2 100pF BOOST2 SW2 L2 1.2µH BG2 PGND 100Ω 1nF 100Ω – SENSE2 VID21 VID22 VOSENSE2 ITH2 SGND 0.1µF 0.004Ω HAT2266H RUN2 TK/SS1 17.8k 1% HAT2266H 0.1µF FREQ SENSE1 VID11 VID12 VOSENSE1 ITH1 VIN 7V TO 36V CIN1 22µF 50V D4 CMDSH-3 SENSE2+ – 1800pF 10k 1% ILIM RUN1 50k 1% + MODE/PLLIN SENSE1+ 100Ω VOUT1 3.6V 10A BG1 LTC3865 + 3.3µF 50V 23.2k 1% 2200pF TK/SS2 0.1µF 121k 14.7k 1% 10k 1% 100pF COUT1, COUT2: SANYO 4TPE 220µF L1: TOKO FDA1055-2R2M L2: TOKO FD1055-1R2M VOUT2 2V 10A + COUT2 220µF s2 3865 F17 Figure 17. High VIN, 3.6V/10A, 2V/10A Converter With External Sense Resistors Synchronized at 400kHz 10µF 35V 4.7µF RJK0305DPB D3 VIN PGOOD EXTVCC INTVCC TG2 TG1 0.1µF L1 0.47µH 1µF 2.2Ω BOOST1 SW1 RJK0330DPB BG1 LTC3865 MODE/PLLIN ILIM 100Ω 2mΩ + 100Ω 1.21k 1% RUN1 L2 0.47µH RJK0330DPB PGND 100Ω 0.1µF RUN2 SENSE2– SENSE1 VID11 VID12 VOSENSE1 ITH1 TK/SS1 BG2 2mΩ 100Ω VID21 VID22 1.2V 30A VOSENSE2 ITH2 SGND + TK/SS2 162k 100pF 22µF 50V RJK0305DPB 0.1µF SENSE2+ – 6800pF COUT1 220µF BOOST2 SW2 VIN 7V TO 20V D4 FREQ SENSE1+ 0.1µF + 10µF 35V COUT2 220µF 0.1µF COUT1, COUT2: SANYO 4TPE 220µF L1, L2: VISHAY IHLP4040DZERR47M11 RUN1 0Ω 3865 F18 RUN2 Figure 18. High Current, Single Output, 1.2V/30A Converter Using Sense Resistors 3865f 33 LTC3865/LTC3865-1 Package Description UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 p0.05 5.50 p0.05 4.10 p0.05 3.50 REF (4 SIDES) 3.45 p 0.05 3.45 p 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 p 0.05 R = 0.05 TYP 0.00 – 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 31 32 0.40 p 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.50 REF (4-SIDES) 3.45 p 0.10 3.45 p 0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 p 0.05 0.50 BSC 3865f 34 LTC3865/LTC3865-1 Package Description FE Package 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1772 Rev A) Exposed Pad Variation AA 4.75 REF 38 9.60 – 9.80* (.378 – .386) 4.75 REF (.187) 20 6.60 ±0.10 4.50 REF 2.74 REF SEE NOTE 4 6.40 2.74 REF (.252) (.108) BSC 0.315 ±0.05 1.05 ±0.10 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.50 – 0.75 (.020 – .030) 0.09 – 0.20 (.0035 – .0079) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 1 0.25 REF 19 1.20 (.047) MAX 0o – 8o 0.50 (.0196) BSC 0.17 – 0.27 (.0067 – .0106) TYP 0.05 – 0.15 (.002 – .006) FE38 (AA) TSSOP 0608 REV A 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3865f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC3865/LTC3865-1 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC3850/LTC3850-1 Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz, 4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V LTC3850-2 Controllers, RSENSE or DCR Current Sensing and Tracking LTC3855 Dual, Multiphase Synchronous Step-Down DC/DC Controller with Diffamp and DCR Temperature Compensation Phase-Lockable Fixed Operating Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12.5V LTM®4619 Dual, 4A DC/DC µModule® Complete Power Supply High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ VIN ≤ 26.5V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LGA LTC3868/LTC3868-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 24V, 0.8V ≤ VOUT ≤ 14V, IQ = 170µA, LTC3857/LTC3857-1 Low IQ, Dual, 2-Phase Synchronous Step-Down Controllers 50µA IQ, 0.8V ≤ VOUT ≤ 24V, 4V ≤ VIN ≤ 38V, Output Overcurrent Foldback Protection LTC3858/LTC3858-1 Low IQ, Dual, 2-Phase Synchronous Step-Down Controllers 170µA IQ, 0.8V ≤ VOUT ≤ 24V, 4V ≤ VIN ≤ 38V, Output Overcurrent Latchoff Protection LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz, 4V ≤ VIN ≤ 24V, VOUT Up to 13.5V LTC3854 Small Footprint Wide VIN Range Synchronous Step-Down DC/DC Controller Fixed 400kHz Operating Frequency 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12 LTC3851A LTC3851A-1 No RSENSE™ Wide VIN Range Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16 LTC3775 High Frequency, Synchronous Voltage Mode Step-Down DC/DC Controller Synchronizable Fixed Frequency 250kHz to 1MHz, tON(MIN) = 30ns, 4V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 0.8V, MSOP-16E, 3mm × 3mm QFN-16 LTC3878 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Controller Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16 LTC3879 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Controller Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16 LTM4600HV 10A DC/DC µModule Regulator High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LGA LTM4601AHV 12A DC/DC µModule Regulator High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LGA LTC3610 12A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time 4V ≤ VIN ≤ 24V, VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 LTC3611 10A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time 4V ≤ VIN ≤ 32V, VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 3865f 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 0210 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2010