TI SN74LVC245APWR

SN74LVC245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
•
•
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
RGY PACKAGE
(TOP VIEW)
A1
A2
A3
A4
A5
A6
A7
A8
DESCRIPTION/ORDERING INFORMATION
This octal bus transceiver is designed for 1.65-V to
3.6-V VCC operation.
The SN74LVC245A is designed for asynchronous
communication between data buses. The device
transmits data from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level
at the direction-control (DIR) input. The output-enable
(OE) input can be used to disable the device so the
buses effectively are isolated.
VCC
•
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
4
19 OE
18 B1
17 B2
5
6
16 B3
15 B4
7
8
14 B5
13 B6
9
12 B7
2
3
10
11
B8
•
DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
DIR
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
GND
FEATURES
•
•
•
•
ORDERING INFORMATION
PACKAGE (1)
TA
Tube of 20
SN74LVC245AN
SN74LVC245AN
QFN – RGY
Reel of 1000
SN74LVC245ARGYR
LC245A
Tube of 25
SN74LVC245ADW
Reel of 2000
SN74LVC245ADWR
SOP – NS
Reel of 2000
SN74LVC245ANSR
LVC245A
SSOP – DB
Reel of 2000
SN74LVC245ADBR
LC245A
Tube of 70
SN74LVC245APW
Reel of 2000
SN74LVC245APWR
Reel of 250
SN74LVC245APWT
Reel of 2000
SN74LVC245ADGVR
TSSOP – PW
TVSOP – DGV
VFBGA – GQN
VFBGA – ZQN (Pb-Free)
(1)
TOP-SIDE MARKING
PDIP – N
SOIC – DW
–40°C to 85°C
ORDERABLE PART NUMBER
Reel of 1000
SN74LVC245AGQNR
SN74LVC245AZQNR
LVC245A
LC245A
LC245A
LC245A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
SN74LVC245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
TERMINAL ASSIGNMENTS
1
2
3
4
A
A1
DIR
VCC
OE
B
A3
B2
A2
B1
C
A5
A4
B4
B3
D
A7
B6
A6
B5
E
GND
A8
B8
B7
FUNCTION TABLE
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
1
19
A1
OE
2
18
B1
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
2
SN74LVC245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
Absolute Maximum Ratings
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
DB
package (4)
DGV package
DW package
θJA
Package thermal impedance
(1)
(2)
(3)
(4)
(5)
Storage temperature range
92
(4)
58
78
package (4)
69
NS package (4)
60
PW package (4)
83
RGY
Tstg
70
(4)
GQN/ZQN package (4)
N
V
package (5)
°C/W
37
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
3
SN74LVC245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
Recommended Operating Conditions (1)
TA = 25°C
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.5
1.5
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
0.35 × VCC
0.35 × VCC
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
(1)
4
V
V
0
5.5
0
5.5
V
0
VCC
0
VCC
V
VCC = 1.65 V
–4
–4
VCC = 2.3 V
–8
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
4
4
VCC = 1.65 V
UNIT
V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VIL
–40°C TO 85°C
VCC = 2.3 V
8
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
10
10
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
mA
mA
ns/V
SN74LVC245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
VCC
1.65 V to 3.6 V
–40°C TO 85°C
TYP MAX
MIN MAX
VCC – 0.2
VCC – 0.2
IOH = –4 mA
1.65 V
1.29
1.2
IOH = –8 mA
2.3 V
1.9
1.7
2.7 V
2.2
2.2
2.4
IOH = –12 mA
VOL
TA = 25°C
MIN
UNIT
V
3V
2.4
IOH = –24 mA
3V
2.3
IOL = 100 µA
1.65 V to 3.6 V
0.1
0.2
IOL = 4 mA
1.65 V
0.24
0.45
IOL = 8 mA
2.3 V
0.3
0.7
IOL = 12 mA
2.7 V
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
2.2
V
3.6 V
±1
±5
µA
Ioff
VI or VO = 5.5 V
0
±1
±10
µA
IOZ (1)
VO = 0 to 5.5 V
3.6 V
±1
±10
µA
1
10
1
10
500
500
II
Control inputs
VI = 0 to 5.5 V
VI = VCC or GND
ICC
IO = 0
3.6 V ≤ VI ≤ 5.5 V (2)
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
3.6 V
2.7 V to 3.6 V
µA
µA
Ci
Control inputs
VI = VCC or GND
3.3 V
4
pF
Cio
A or B ports
VI = VCC or GND
3.3 V
5.5
pF
(1)
(2)
For I/O ports, the parameter IOZ includes the input leakage current.
This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
A or B
OE
OE
TO
(OUTPUT)
B or A
A or B
A or B
VCC
MIN
–40°C TO 85°C
TYP
MAX
MIN
MAX
1.8 V ± 0.15 V
1
6
12.2
1
12.7
2.5 V ± 0.2 V
1
3.9
7.8
1
8.3
2.7 V
1
4.2
7.1
1
7.3
3.3 V ± 0.3 V
1.5
3.8
6.1
1.5
6.3
1.8 V ± 0.15 V
1
7
14.8
1
15.3
2.5 V ± 0.2 V
1
4.5
10
1
10.5
2.7 V
1
5.4
9.3
1
9.5
3.3 V ± 0.3 V
1.5
4.4
8.3
1.5
8.5
1.8 V ± 0.15 V
1
7.8
16.5
1
17
2.5 V ± 0.2 V
1
4
9
1
9.5
2.7 V
1
4.4
8.3
1
8.5
1.7
4.1
7.3
1.7
7.5
3.3 V ± 0.3 V
tsk(o)
TA = 25°C
3.3 V ± 0.3 V
1
UNIT
ns
ns
ns
ns
5
SN74LVC245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
f = 10 MHz
Outputs disabled
6
VCC
TYP
1.8 V
42
2.5 V
43
3.3 V
45
1.8 V
1
2.5 V
1
3.3 V
2
UNIT
pF
SN74LVC245A
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC245ADBLE
OBSOLETE
SSOP
DB
20
None
Call TI
SN74LVC245ADBR
ACTIVE
SSOP
DB
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LVC245ADGVR
ACTIVE
TVSOP
DGV
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LVC245ADW
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LVC245ADWR
ACTIVE
SOIC
DW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74LVC245AGQNR
ACTIVE
VFBGA
GQN
20
1000
None
SNPB
SN74LVC245AN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74LVC245ANSR
ACTIVE
SO
NS
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LVC245APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC245APWLE
OBSOLETE
TSSOP
PW
20
SN74LVC245APWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC245APWT
ACTIVE
TSSOP
PW
20
250
CU NIPDAU
Level-1-250C-UNLIM
SN74LVC245ARGYR
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LVC245AZQNR
ACTIVE
VFBGA
ZQN
20
1000
SNAGCU
Level-1-260C-UNLIM
None
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
Level-1-240C-UNLIM
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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