SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 FEATURES • • • • SN54LVC86A . . . J OR W PACKAGE SN74LVC86A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 2 13 4B 3 12 4A 4 11 4Y 10 3B 5 6 9 3A 7 8 SN54LVC86A . . . FK PACKAGE (TOP VIEW) 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 8 15 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 13 VCC 14 2 3Y 1 SN74LVC86A . . . RGY PACKAGE (TOP VIEW) 1A 1A 1B 1Y 2A 2B 2Y GND • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) GND • • • Operate From 1.65 V to 3.6 V Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C Inputs Accept Voltages to 5.5 V Max tpd of 4.6 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C NC - No internal connection DESCRIPTION/ORDERING INFORMATION The SN54LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 1.65-V to 3.6-V VCC operation. The 'LVC86A devices perform the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C QFN – RGY SOIC – D –40°C to 125°C (1) Reel of 1000 SN74LVC86ARGYR Tube of 50 SN74LVC86AD Reel of 2500 SN74LVC86ADR TOP-SIDE MARKING LC86A LVC86A Reel of 250 SN74LVC86ADT SOP – NS Reel of 2000 SN74LVC86ANSR LVC86A SSOP – DB Reel of 2000 SN74LVC86ADBR LC86A Tube of 90 SN74LVC86APW Reel of 2000 SN74LVC86APWR Reel of 250 SN74LVC86APWT CDIP – J Tube of 25 SNJ54LVC86AJ SNJ54LVC86AJ CFP – W Tube of 150 SNJ54LVC86AW SNJ54LVC86AW LCCC – FK Tube of 55 SNJ54LVC86AFK SNJ54LVC86AFK TSSOP – PW –55°C to 125°C ORDERABLE PART NUMBER LC86A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1993–2005, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. FUNCTION TABLE (EACH GATE) INPUTS A OUTPUT Y B L L L L H H H L H H H L EXCLUSIVE-OR LOGIC An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT = The output is active (low) if all inputs stand at the same logic level (i.e., A = B). 2 EVEN-PARITY ELEMENT 2k The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. ODD-PARITY ELEMENT 2k + 1 The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 VCC + 0.5 range (2) (3) UNIT VO Output voltage IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND D package (4) 86 DB package (4) θJA Package thermal impedance Tstg Storage temperature range Ptot Power dissipation (1) (2) (3) (4) (5) (6) V 96 NS package (4) 76 PW package (4) 113 RGY package (4) 47 –65 TA = –40°C to 125°C (5) (6) °C/W 150 °C 500 mW Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K. For the DB, DGV, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K. Recommended Operating Conditions (1) SN54LVC86A –55 TO 125°C Operating VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate (1) Data retention only UNIT MIN MAX 2 3.6 1.5 2 V V 0.8 V 0 5.5 V 0 VCC V VCC = 2.7 V –12 VCC = 3 V –24 VCC = 2.7 V 12 VCC = 3 V 24 9 mA mA ns/V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 Recommended Operating Conditions (1) SN74LVC86A TA = 25°C VCC Supply voltage VIH High-level input voltage Low-level input voltage VIL Operating –40 TO 85°C –40 TO 125°C MAX MIN MAX MIN MAX 1.65 3.6 1.65 3.6 1.65 3.6 Data retention only 1.5 1.5 1.5 0.65 × VCC 0.65 × VCC 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V UNIT MIN 2 V 2 0.35 × VCC 0.35 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 VCC = 2.7 V to 3.6 V 0.8 0.8 0.8 VCC = 1.65 V to 1.95 V V V VI Input voltage 0 5.5 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC 0 VCC V VCC = 1.65 V High-level output current IOH –4 –8 –8 –8 VCC = 2.7 V –12 –12 –12 VCC = 3 V –24 –24 –24 4 4 4 8 8 8 12 12 12 24 24 24 9 9 9 VCC = 1.65 V VCC = 3 V ∆t/∆v (1) –4 VCC = 2.3 V Low-level output VCC = 2.3 V current VCC = 2.7 V IOL –4 Input transition rise or fall rate mA mA ns/V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over operating free-air temperature range (unless otherwise noted) SN54LVC86A PARAMETER TEST CONDITIONS VCC –55 TO 125°C MIN IOH = –100 µA VOH VOL II ICC ∆ICC Ci (1) 4 TA = 25°C 2.7 V to 3.6 V UNIT TYP MAX VCC – 0.2 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 2.7 V to 3.6 V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 IOH = –12 mA VI = 5.5 V or GND VI = VCC or GND One input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND IO = 0 V 0.2 V 3.6 V ±5 µA 3.6 V 10 µA 2.7 V to 3.6 V 500 µA 3.3 V 5 (1) pF SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) SN74LVC86A PARAMETER TEST CONDITIONS VCC TA = 25°C MIN IOH = –100 µA VOH 1.65 V to 3.6 V VCC – 0.2 VCC – 0.2 VCC – 0.3 1.29 1.2 1.05 IOH = –8 mA 2.3 V 1.9 1.7 1.55 2.7 V 2.2 2.2 2.05 3V 2.4 2.4 2.25 IOH = –24 mA 3V 2.3 2.2 2 IOL = 100 µA 0.1 0.2 1.65 V 0.24 0.45 0.6 IOL = 8 mA 2.3 V 0.3 0.7 0.75 IOL = 12 mA 2.7 V 0.4 0.4 0.6 3V IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND ∆ICC Ci V 1.65 V to 3.6 V VI = VCC or GND 0.3 V 0.55 0.55 0.8 3.6 V ±1 ±5 ±20 µA 3.6 V 1 10 40 µA 500 500 5000 µA 2.7 V to 3.6 V VI = VCC or GND UNIT MAX IOL = 4 mA VI = 5.5 V or GND ICC MIN 1.65 V IOL = 24 mA II –40 TO 125°C MIN MAX IOH = –4 mA IOH = –12 mA VOL –40 TO 85°C TYP MAX 3.3 V 5 pF Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC86A FROM (INPUT) PARAMETER TO (OUTPUT) VCC –55 TO 125°C MIN tpd A 2.7 V Y MAX 5.6 3.3 V ± 0.3 V 1 UNIT 4.6 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC86A PARAMETER tpd FROM (INPUT) A TO (OUTPUT) Y VCC TA = 25°C –40 TO 85°C TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V 1 4.1 9.4 1 9.9 1 11.4 2.5 V ± 0.2 V 1 2.9 7.1 1 7.6 1 9.7 2.7 V 1 2.8 5.4 1 5.6 1 7.1 3.3 V ± 0.3 V 1 2.5 4.4 1 4.6 1 5.8 3.3 V ± 0.3 V tsk(o) –40 TO 125°C MIN 1 1.5 UNIT ns ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS f = 10 MHz VCC TYP 1.8 V 6.5 2.5 V 7.5 3.3 V 8.5 UNIT pF 5 SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9761901Q2A ACTIVE LCCC FK 20 1 TBD 5962-9761901QCA ACTIVE CDIP J 14 1 TBD 5962-9761901QDA ACTIVE CFP W 14 1 SN74LVC86AD ACTIVE SOIC D 14 50 SN74LVC86ADBLE OBSOLETE SSOP DB 14 SN74LVC86ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ADTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APWLE OBSOLETE TSSOP PW 14 SN74LVC86APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC86ARGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LVC86ARGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR A42 SNPB N / A for Pkg Type TBD A42 N / A for Pkg Type Green (RoHS & no Sb/Br) CU NIPDAU TBD TBD Addendum-Page 1 POST-PLATE N / A for Pkg Type Call TI Call TI Level-1-260C-UNLIM Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SNJ54LVC86AFK ACTIVE LCCC FK 20 1 TBD SNJ54LVC86AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SNJ54LVC86AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated