PIC16C84
8-bit CMOS EEPROM Microcontroller
High Performance RISC CPU Features:
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
Pin Diagram
PDIP, SOIC
RA2
1
18
RA1
RA3
2
17
RA0
RA4/T0CKI
3
16
OSC1/CLKIN
MCLR
4
15
OSC2/CLKOUT
VSS
5
14
VDD
RB0/INT
6
13
RB7
RB1
7
12
RB6
RB2
8
11
RB5
RB3
9
10
RB4
PIC16C84
• Only 35 single word instructions to learn
• All instructions single cycle (400 ns @ 10 MHz)
except for program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
• 14-bit wide instructions
• 8-bit wide data path
• 1K x 14 EEPROM program memory
• 36 x 8 general purpose registers (SRAM)
• 64 x 8 on-chip EEPROM data memory
• 15 special function hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources:
- External RB0/INT pin
- TMR0 timer overflow
- PORTB<7:4> interrupt on change
- Data EEPROM write complete
• 1,000,000 data memory EEPROM
ERASE/WRITE cycles
• EEPROM Data Retention > 40 years
CMOS Technology:
• Low-power, high-speed CMOS EEPROM
technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.0V to 6.0V
- Industrial:
2.0V to 6.0V
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 60 A typical @ 2V, 32 kHz
- 26 A typical standby current @ 2V
Special Microcontroller Features:
•
•
•
•
•
•
•
•
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Code protection
Power saving SLEEP mode
Selectable oscillator options
Serial In-System Programming - via two pins
1996-2013 Microchip Technology Inc.
DS30445D-page 1
PIC16C84
Table of Contents
1.0 General Description ....................................................................................................................................................................... 3
2.0 PIC16C84 Device Varieties ........................................................................................................................................................... 5
3.0 Architectural Overview ................................................................................................................................................................... 7
4.0 Memory Organization................................................................................................................................................................... 11
5.0 I/O Ports ....................................................................................................................................................................................... 19
6.0 Timer0 Module and TMR0 Register ............................................................................................................................................. 25
7.0 Data EEPROM Memory ............................................................................................................................................................... 31
8.0 Special Features of the CPU ....................................................................................................................................................... 35
9.0 Instruction Set Summary.............................................................................................................................................................. 51
10.0 Development Support .................................................................................................................................................................. 67
11.0 Electrical Characteristics for PIC16C84 ....................................................................................................................................... 71
12.0 DC & AC Characteristics Graphs/Tables for PIC16C84 .............................................................................................................. 83
13.0 Packaging Information ................................................................................................................................................................. 97
Appendix A: Feature Improvements - From PIC16C5X To PIC16C84 ............................................................................................ 99
Appendix B: Code Compatibility - from PIC16C5X to PIC16C84.................................................................................................... 99
Appendix C: What’s New In This Data Sheet ................................................................................................................................. 100
Appendix D: What’s Changed In This Data Sheet ......................................................................................................................... 100
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 101
Index .................................................................................................................................................................................................. 103
On-Line Support................................................................................................................................................................................. 105
PIC16C84 Product Identification System ........................................................................................................................................... 107
Sales and Support.............................................................................................................................................................................. 107
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you
find any information that is missing or appears in error, please use the reader response form in the back of this data
sheet to inform us. We appreciate your assistance in making this a better document.
DS30445D-page 2
1996-2013 Microchip Technology Inc.
PIC16C84
1.0
GENERAL DESCRIPTION
The PIC16C84 is a low-cost, high-performance,
CMOS, fully-static, 8-bit microcontroller.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. PIC16CXX devices have enhanced
core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with a separate
8-bit wide data bus. The two stage instruction pipeline
allows all instructions to execute in a single cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set is
used to achieve a very high performance level.
PIC16CXX microcontrollers typically achieve a 2:1
code compression and up to a 2:1 speed improvement
(at 10 MHz) over other 8-bit microcontrollers in their
class.
The PIC16C84 has 36 bytes of RAM, 64 bytes of Data
EEPROM memory, and 13 I/O pins. A timer/counter is
also available.
The PIC16CXX family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake the chip from sleep through several
external and internal interrupts and resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
The PIC16C84 EEPROM program memory allows the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).
The PIC16C84 fits perfectly in applications ranging
from high speed automotive and appliance motor
control to low-power remote sensors, electronic locks,
security devices and smart cards. The EEPROM
technology makes customization of application
programs (transmitter codes, motor speeds, receiver
frequencies, security codes, etc.) extremely fast and
convenient. The small footprint packages make this
microcontroller series perfect for all applications with
space limitations. Low cost, low power, high
performance, ease of use and I/O flexibility make the
PIC16C84 very versatile even in areas where no
microcontroller use has been considered before
(e.g., timer functions, serial communication, capture
and compare, PWM functions and co-processor
applications).
The serial in-system programming feature (via two
pins) offers flexibility of customizing the product after
complete assembly and testing. This feature can be
used to serialize a product, store calibration data, or
program the device with the current firmware before
shipping.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to the
PIC16C84 (Appendix B).
1.2
Development Support
The PIC16CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
Table 1-1 lists the features of the PIC16C84. A simplified block diagram of the PIC16C84 is shown in
Figure 3-1.
1996-2013 Microchip Technology Inc.
DS30445D-page 3
PIC16C84
TABLE 1-1
PIC16C8X FAMILY OF DEVICES
PIC16F83
Clock
Memory
Maximum Frequency
of Operation (MHz)
PIC16CR83
10
PIC16F84
10
PIC16CR84
10
Flash Program Memory
512
—
1K
—
EEPROM Program Memory
—
—
—
—
ROM Program Memory
—
512
—
1K
Data Memory (bytes)
36
36
68
68
Data EEPROM (bytes)
64
64
64
64
TMR0
TMR0
TMR0
TMR0
Interrupt Sources
4
4
4
4
I/O Pins
13
13
13
13
Voltage Range (Volts)
2.0-6.0
2.0-6.0
2.0-6.0
2.0-6.0
Packages
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
Peripherals Timer Module(s)
Features
10
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30445D-page 4
1996-2013 Microchip Technology Inc.
PIC16C84
2.0
PIC16C84 DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements the proper device option can be selected
using the information in this section. When placing
orders, please use the “PIC16C84 Product
Identification System” at the back of this data sheet to
specify the correct part number.
There are two device “types” as indicated in the device
number.
1.
2.
C, as in PIC16C84. These devices have
EEPROM program memory and operate over
the standard voltage range.
LC, as in PIC16LC84. These devices have
EEPROM program memory and operate over an
extended voltage range.
When discussing memory maps and other architectural
features, the use of C also implies the LC versions.
2.1
Electrically Erasable Devices
These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This allows the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically erasable version
is that they can be erased and reprogrammed in-circuit,
or by device programmers, such as Microchip's
PICSTART Plus or PRO MATE II programmers.
1996-2013 Microchip Technology Inc.
DS30445D-page 5
PIC16C84
NOTES:
DS30445D-page 6
1996-2013 Microchip Technology Inc.
PIC16C84
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CXX uses a Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC16CXX opcodes are 14-bits wide, enabling single
word instructions. The full 14-bit wide program memory
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (400 ns @ 10 MHz) except for
program branches.
The PIC16C84 addresses 1K x 14 program memory.
All program memory is internal.
PIC16CXX devices can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. An orthogonal (symmetrical)
instruction set that makes it possible to carry out any
operation on any register using any addressing mode.
This symmetrical nature and lack of ‘special optimal
situations’ make programming with the PIC16CXX
simple yet efficient. In addition, the learning curve is
reduced significantly.
The PIC16C84 has 36 x 8 SRAM and 64 x 8 EEPROM
data memory.
1996-2013 Microchip Technology Inc.
DS30445D-page 7
PIC16C84
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
data in the working register and any register file.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register), and the other operand is a file register or
an immediate constant. In single operand instructions,
the operand is either the W register or a file register.
FIGURE 3-1:
A simplified block diagram for the PIC16C84 is shown
in Figure 3-1, its corresponding pin description is
shown in Table 3-1.
PIC16C84 BLOCK DIAGRAM
13
EEPROM
Program
Memory
1K x 14
Data Bus 8
Program Counter
8 Level Stack
(13-bit)
Program
Bus 14
EEPROM Data Memory
RAM
File Registers
EEDATA
36 x 8
7
RAM Addr
EEPROM
Data Memory
64 x 8
EEADR
Addr Mux
Instruction reg
5
7
Direct Addr
Indirect
Addr
TMR0
FSR reg
RA4/T0CKI
STATUS reg
8
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
Oscillator
Start-up Timer
I/O Ports
ALU
Power-on
Reset
Watchdog
Timer
RA3:RA0
W reg
RB7:RB1
RB0/INT
OSC2/CLKOUT
OSC1/CLKIN
DS30445D-page 8
MCLR
VDD, VSS
1996-2013 Microchip Technology Inc.
PIC16C84
TABLE 3-1
PIC16C8X PINOUT DESCRIPTION
DIP
No.
SOIC
No.
I/O/P
Type
OSC1/CLKIN
16
16
I
OSC2/CLKOUT
15
15
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle
rate.
MCLR
4
4
I/P
ST
Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
RA0
17
17
I/O
TTL
RA1
18
18
I/O
TTL
RA2
1
1
I/O
TTL
Pin Name
Buffer
Type
Description
ST/CMOS (1) Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA3
2
2
I/O
TTL
RA4/T0CKI
3
3
I/O
ST
Can also be selected to be the clock input to the TMR0 timer/
counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT
6
6
I/O
TTL
RB1
7
7
I/O
TTL
RB2
8
8
I/O
TTL
RB3
9
9
I/O
TTL
RB4
10
10
I/O
TTL
RB5
11
11
I/O
TTL
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin.
Interrupt on change pin.
(2)
RB6
12
12
I/O
TTL/ST
RB7
13
13
I/O
TTL/ST (2)
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
VSS
5
5
P
—
Ground reference for logic and I/O pins.
VDD
14
14
P
—
Positive supply for logic and I/O pins.
Legend: I= input
Note 1:
2:
O = output
I/O = Input/Output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
This buffer is a Schmitt Trigger input when used in serial programming mode.
1996-2013 Microchip Technology Inc.
DS30445D-page 9
PIC16C84
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30445D-page 10
1996-2013 Microchip Technology Inc.
PIC16C84
MEMORY ORGANIZATION
There are two memory blocks in the PIC16C84. These
are the program memory and the data memory. Each
block has its own bus, so that access to each block can
occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
4.1
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
Reset Vector
0000h
Peripheral Interrupt Vector
0004h
User Memory
Space
4.0
Program Memory Organization
The PIC16CXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16C84, only the first 1K x 14 (0000h-03FFh) are
physically implemented (Figure 4-1). Accessing a location above the physically implemented address will
cause a wraparound. For example, locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction.
3FFh
1FFFh
The reset vector is at 0000h and the interrupt vector is
at 0004h.
1996-2013 Microchip Technology Inc.
DS30445D-page 11
PIC16C84
4.2
Data Memory Organization
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Figure 4-2 shows the data memory map organization.
Instructions MOVWF and MOVF can move values from
the W register to any location in the register file (“F”),
and vice-versa.
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects
Bank 1. Each Bank extends up to 7Fh (128 bytes). The
first twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are General Purpose Registers implemented as static RAM.
4.2.1
REGISTER FILE MAP
File Address
File Address
00h
Indirect addr.(1)
Indirect addr.(1)
01h
TMR0
OPTION
81h
02h
PCL
PCL
82h
03h
STATUS
STATUS
83h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
08h
EEDATA
EECON1
88h
09h
EEADR
EECON2(1)
89h
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
80h
87h
07h
8Ch
0Ch
36
General
Purpose
registers
(SRAM)
Mapped
(accesses)
in Bank 0
AFh
B0h
2Fh
30h
GENERAL PURPOSE REGISTER FILE
All devices have some amount of General Purpose
Register (GPR) area. Each GPR is 8 bits wide and is
accessed either directly or indirectly through the FSR
(Section 4.5).
The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR.
4.2.2
FIGURE 4-2:
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory location; read as '0'.
Note 1:
Not a physical register.
SPECIAL FUNCTION REGISTERS
The Special Function Registers (Figure 4-2 and
Table 4-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
DS30445D-page 12
1996-2013 Microchip Technology Inc.
PIC16C84
TABLE 4-1
Address
REGISTER FILE SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Bank 0
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ----
---- ----
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
02h
PCL
Low order 8 bits of the Program Counter (PC)
0000 0000
0000 0000
0001 1xxx
000q quuu
(2)
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
RP1
RP0
PD
Z
DC
C
Indirect data memory address pointer 0
07h
08h
IRP
TO
xxxx xxxx
uuuu uuuu
—
—
—
RA4/T0CKI
RA3
RA2
RA1
RA0
---x xxxx
---u uuuu
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
xxxx xxxx
uuuu uuuu
Unimplemented location, read as '0'
EEDATA
EEPROM data register
09h
EEADR
0Ah
PCLATH
—
—
—
EEPROM address register
0Bh
INTCON
GIE
EEIE
T0IE
80h
INDF
81h
OPTION_
REG
82h
PCL
---- ----
---- ----
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
---0 0000
---0 0000
0000 000x
0000 000u
Uses contents of FSR to address data memory (not a physical register)
---- ----
---- ----
INTEDG
1111 1111
1111 1111
0000 0000
0000 0000
0001 1xxx
000q quuu
Write buffer for upper 5 bits of the PC (1)
INTE
RBIE
T0IF
INTF
RBIF
Bank 1
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
Low order 8 bits of Program Counter (PC)
(2)
83h
STATUS
84h
FSR
85h
TRISA
86h
TRISB
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer 0
—
—
—
PORTA data direction register
PORTB data direction register
Unimplemented location, read as '0'
87h
88h
EECON1
—
—
—
89h
EECON2
0Ah
PCLATH
—
—
—
0Bh
INTCON
GIE
EEIE
T0IE
EEIF
WRERR
WREN
WR
RD
EEPROM control register 2 (not a physical register)
Write buffer for upper 5 bits of the PC (1)
INTE
RBIE
T0IF
INTF
RBIF
xxxx xxxx
uuuu uuuu
---1 1111
---1 1111
1111 1111
1111 1111
---- ----
---- ----
---0 x000
---0 q000
---- ----
---- ----
---0 0000
---0 0000
0000 000x
0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996-2013 Microchip Technology Inc.
DS30445D-page 13
PIC16C84
4.2.2.1
STATUS REGISTER
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
As with any register, the STATUS register can be the
destination for any instruction. If the STATUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
FIGURE 4-3:
R/W-0
IRP
Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 9-2)
because these instructions do not affect any status bit.
Note 1: The IRP and RP1 bits (STATUS<7:6>) are
not used by the PIC16C84 and should be
programmed as cleared. Use of these bits
as general purpose R/W bits is NOT
recommended, since this may affect
upward compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Note 3: When the STATUS register is the
destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP1
R/W-0
RP0
R-1
R-1
TO
PD
R/W-x
Z
R/W-x
DC
bit7
bit 7:
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16C8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16C8X. RP1 should be maintained clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (for ADDWF and ADDLW instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or
low order bit of the source register.
DS30445D-page 14
1996-2013 Microchip Technology Inc.
PIC16C84
4.2.2.2
OPTION_REG REGISTER
Note:
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-4:
When the prescaler is assigned to
the WDT (PSA = '1'), TMR0 has a 1:1
prescaler assignment.
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1996-2013 Microchip Technology Inc.
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS30445D-page 15
PIC16C84
4.2.2.3
INTCON REGISTER
Note:
The INTCON register is a readable and writable
register which contains the various enable bits for all
interrupt sources.
FIGURE 4-5:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section 8.5.
bit 6:
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1:
INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
DS30445D-page 16
1996-2013 Microchip Technology Inc.
PIC16C84
4.3
Program Counter: PCL and PCLATH
Note:
The Program Counter (PC) is 13-bits wide. The low
byte is the PCL register, which is a readable and
writable register. The high byte of the PC (PC<12:8>) is
not directly readable nor writable and comes from the
PCLATH register. The PCLATH (PC latch high) register
is a holding register for PC<12:8>. The contents of
PCLATH are transferred to the upper byte of the
program counter when the PC is loaded with a new
value. This occurs during a CALL, GOTO or a write to
PCL. The high bits of PC are loaded from PCLATH as
shown in Figure 4-6.
FIGURE 4-6:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
12
PCL
8 7
0
INST with PCL
as dest
PC
8
PCLATH<4:0>
5
ALU result
4.4
The entire 13-bit PC is “pushed” onto the stack when a
CALL instruction is executed or an interrupt is acknowledged. The stack is “popped” in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a push or a pop operation.
Note:
PCL
8 7
0
PC
GOTO, CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256 word block). Refer to the application
note “Implementing a Table Read” (AN556).
4.3.2
Stack
The PIC16C84 has an 8 deep x 13-bit wide hardware
stack (Figure 4-1). The stack space is not part of either
program or data space and the stack pointer is not
readable or writable.
PCLATH
PCH
12 11 10
The PIC16C84 ignores the PCLATH<4:3>
bits, which are used for program memory
pages 1, 2 and 3 (0800h - 1FFFh). The use
of PCLATH<4:3> as general purpose R/W
bits is not recommended since this may
affect upward compatibility with future
products.
There are no instruction mnemonics called
push or pop. These are actions that occur
from the execution of the CALL, RETURN,
RETLW, and RETFIE instructions, or the
vectoring to an interrupt address.
The stack operates as a circular buffer. That is, after the
stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. The
tenth push overwrites the second push (and so on).
If the stack is effectively popped nine times, the PC
value is the same as the value from the first pop.
Note:
There are no status bits to indicate stack
overflow or stack underflow conditions.
PROGRAM MEMORY PAGING
The PIC16C84 has 1K of program memory. The CALL
and GOTO instructions have an 11-bit address range.
This 11-bit address range allows a branch within a 2K
program memory page size. For future PIC16CXX
program memory expansion, there must be another
two bits to specify the program memory page. These
paging bits come from the PCLATH<4:3> bits
(Figure 4-6). When doing a CALL or a GOTO instruction,
the user must ensure that these page bits
(PCLATH<4:3>) are programmed to the desired
program memory page. If a CALL instruction (or
interrupt) is executed, the entire 13-bit PC is “pushed”
onto the stack (see next section). Therefore, manipulation of the PCLATH<4:3> is not required for the return
instructions (which “pops” the PC from the stack).
1996-2013 Microchip Technology Inc.
DS30445D-page 17
PIC16C84
4.5
Indirect Addressing; INDF and FSR
Registers
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 4-1:
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
INDIRECT ADDRESSING
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
FIGURE 4-7:
movlw
movwf
clrf
incf
btfss
goto
NEXT
0x20
FSR
INDF
FSR
FSR,4
NEXT
CONTINUE
:
;YES, continue
DIRECT/INDIRECT ADDRESSING
Indirect Addressing
Direct Addressing
RP1 RP0
bank select
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
6
from opcode
0
IRP
location select
7
bank select
00
01
10
11
not used
not used
Bank 2
Bank 3
(FSR)
0
location select
00h
00h
0Bh
0Ch
Addresses
map back
to Bank 0
Data
Memory
2Fh
30h
7Fh
7Fh
Bank 0
DS30445D-page 18
Bank 1
1996-2013 Microchip Technology Inc.
PIC16C84
5.0
I/O PORTS
EXAMPLE 5-1:
INITIALIZING PORTA
CLRF
PORTA
BSF
MOVLW
STATUS, RP0
0x0F
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
MOVWF
TRISA
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
FIGURE 5-2:
The PIC16C84 has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate function for other features on the device.
5.1
;
;
;
;
;
;
;
;
;
;
;
PORTA and TRISA Registers
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
Data
bus
WR
PORT
Initialize PORTA by
setting output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA4 as outputs
TRISA<7:5> are always
read as '0'.
BLOCK DIAGRAM OF PIN RA4
D
Q
CK
Q
N
Data Latch
VSS
WR
TRIS
The RA4 pin is multiplexed with the TMR0 clock input.
D
Q
CK
Q
Schmitt
Trigger
input
buffer
TRIS Latch
FIGURE 5-1:
RA4 pin
BLOCK DIAGRAM OF PINS
RA3:RA0
Data
bus
RD TRIS
D
Q
Q
VDD
WR
Port
CK
Q
D
EN
EN
P
RD PORT
Data Latch
N
D
WR
TRIS
I/O pin
Q
VSS
CK
TMR0 clock input
Note: I/O pin has protection diodes to VSS only.
Q
TRIS Latch
TTL
input
buffer
RD TRIS
Q
D
Note:
For crystal oscillator configurations
operating below 500 kHz, the device may
generate a spurious internal Q-clock when
PORTA<0> switches state. This does not
occur with an external clock in RC mode.
To avoid this, the RA0 pin should be kept
static, i.e. in input/output mode, pin RA0
should not be toggled.
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
1996-2013 Microchip Technology Inc.
DS30445D-page 19
PIC16C84
TABLE 5-1
Name
PORTA FUNCTIONS
Bit0
Buffer Type
Function
RA0
bit0
TTL
Input/output
RA1
bit1
TTL
Input/output
RA2
bit2
TTL
Input/output
RA3
bit3
TTL
Input/output
RA4/T0CKI
bit4
ST
Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2
Address
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
05h
PORTA
—
—
—
RA4/T0CKI
RA3
RA2
RA1
RA0
---x xxxx
---u uuuu
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30445D-page 20
1996-2013 Microchip Technology Inc.
PIC16C84
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' on
any bit in the TRISB register puts the corresponding
output driver in a hi-impedance mode. A '0' on any bit
in the TRISB register puts the contents of the output
latch on the selected pin(s).
Each of the PORTB pins have a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION_REG<7>) bit.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The pins value in input mode
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of the pins are
OR’ed together to generate the RB port
change interrupt.
FIGURE 5-3:
BLOCK DIAGRAM OF PINS
RB7:RB4
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Read (or write) PORTB. This will end the mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set the RBIF bit.
Reading PORTB will end the mismatch condition, and
allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (see AN552 in the
Embedded Control Handbook).
Note 1: If a change on the I/O pin should occur
when a read operation of PORTB is being
executed (start of the Q2 cycle), the RBIF
interrupt flag bit may not be set.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-4:
BLOCK DIAGRAM OF PINS
RB3:RB0
VDD
RBPU(1)
VDD
weak
P pull-up
RBPU(1)
Data Latch
Data bus
D
WR Port
Data bus
Q
I/O
pin(2)
CK
WR Port
TRIS Latch
D
WR TRIS
weak
P pull-up
Data Latch
D
Q
I/O
pin(2)
CK
TRIS Latch
D
Q
Q
TTL
Input
Buffer
CK
WR TRIS
Latch
RD TRIS
Q
RD Port
TTL
Input
Buffer
CK
RD TRIS
Q
D
EN
RD Port
D
EN
Set RBIF
From other
RB7:RB4 pins
RB0/INT
Q
D
RD Port
EN
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
RD Port
2: I/O pins have diode protection to VDD and VSS.
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
1996-2013 Microchip Technology Inc.
DS30445D-page 21
PIC16C84
EXAMPLE 5-1:
INITIALIZING PORTB
CLRF
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
TABLE 5-3
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
setting output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
PORTB FUNCTIONS
Name
Bit
Buffer Type
I/O Consistency Function
RB0/INT
bit0
TTL
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable weak pull-up.
RB6
bit6
TTL/ST(1)
Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock.
RB7
bit7
TTL/ST(1)
Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
xxxx xxxx
uuuu uuuu
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
81h
OPTION_
REG
PS0
1111 1111
1111 1111
Address
06h
Name
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30445D-page 22
1996-2013 Microchip Technology Inc.
PIC16C84
5.3
I/O Programming Considerations
5.3.2
5.3.1
BI-DIRECTIONAL I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 55). Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should be such that the
pin voltage stabilizes (load dependent) before the next
instruction which causes that file to be read into the
CPU is executed. Otherwise, the previous state of that
pin may be read into the CPU rather than the new state.
When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing
this I/O port.
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(i.e., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However, if
bit0 is switched into output mode later on, the content
of the data latch is unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port
pins is read, the desired operation is done to this value,
and this value is then written to the port latch.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output current may damage the chip.
FIGURE 5-5:
Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------BCF PORTB, 7
; 01pp ppp
11pp ppp
BCF PORTB, 6
; 10pp ppp
11pp ppp
BSF STATUS, RP0 ;
BCF TRISB, 7
; 10pp ppp
11pp ppp
BCF TRISB, 6
; 10pp ppp
10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
SUCCESSIVE OPERATIONS ON I/O PORTS
PC
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
Note:
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Instruction
executed
NOP
MOVWF PORTB
write to
PORTB
1996-2013 Microchip Technology Inc.
MOVF PORTB,W
Therefore, at higher clock frequencies,
a write followed by a read may be problematic.
DS30445D-page 23
PIC16C84
NOTES:
DS30445D-page 24
1996-2013 Microchip Technology Inc.
PIC16C84
6.0
TIMER0 MODULE AND TMR0
REGISTER
edge select bit, T0SE (OPTION<4>). Clearing bit T0SE
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.2.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
The prescaler is shared between the Timer0 Module
and the Watchdog Timer. The prescaler assignment is
controlled, in software, by control bit PSA
(OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 Module. The prescaler is not
readable or writable. When the prescaler (Section 6.3)
is assigned to the Timer0 Module, the prescale value
(1:2, 1:4, ..., 1:256) is software selectable.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
6.1
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module
(Figure 6-1) will increment every instruction cycle
(without prescaler). If the TMR0 register is written, the
increment is inhibited for the following two cycles
(Figure 6-2 and Figure 6-3). The user can work around
this by writing an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
the T0IF bit (INTCON<2>). The interrupt can be
masked by clearing enable bit T0IE (INTCON<5>). The
T0IF bit must be cleared in software by the Timer0
Module interrupt service routine before re-enabling this
interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
the processor from SLEEP since the timer is shut off
during SLEEP.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode TMR0 will increment either
on every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the T0 source
FIGURE 6-1:
TMR0 Interrupt
TMR0 BLOCK DIAGRAM
Data bus
FOSC/4
0
PSout
1
1
RA4/T0CKI
pin
Programmable
Prescaler
8
Sync with
Internal
clocks
0
TMR0 register
PSout
(2 cycle delay)
T0SE
3
PS2, PS1, PS0
Set bit T0IF
on Overflow
PSA
T0CS
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2:
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
MOVWF TMR0
Instruction
Fetch
TMR0
PC
T0
T0+1
Instruction
Executed
1996-2013 Microchip Technology Inc.
PC+1
PC+2
PC+3
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
Read TMR0
reads NT0 + 1
NT0+2
T0
Read TMR0
reads NT0 + 2
DS30445D-page 25
PIC16C84
FIGURE 6-3:
TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0
TMR0
PC+2
PC+3
T0+1
Instruction
Execute
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
FIGURE 6-4:
PC+4
MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TMR0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
T0IF bit 4
(INTCON<2>)
1
FFh
00h
01h
02h
1
GIE bit
(INTCON<7>)
Interrupt Latency(2)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.
DS30445D-page 26
1996-2013 Microchip Technology Inc.
PIC16C84
6.2
Using TMR0 with External Clock
6.2.2
TMR0 INCREMENT DELAY
When an external clock input is used for TMR0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing
of
the
TMR0
register
after
synchronization.
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
Module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
6.2.1
6.3
EXTERNAL CLOCK SYNCHRONIZATION
Prescaler
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of pin RA4/T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2Tosc (plus a small RC delay) and low
for at least 2Tosc (plus a small RC delay). Refer to the
electrical specification of the desired device.
An 8-bit counter is available as a prescaler for the
Timer0 Module, or as a postscaler for the Watchdog
Timer (Figure 6-6). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusive between the Timer0 Module and the
Watchdog Timer. Thus, a prescaler assignment for the
Timer0 Module means that there is no prescaler for the
Watchdog Timer, and vice-versa.
When a prescaler is used, the external clock input is
divided by an asynchronous ripple counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4Tosc (plus a small RC delay) divided
by the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the AC Electrical
Specifications of the desired device.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
FIGURE 6-5:
When assigned to the Timer0 Module, all instructions
writing to the Timer0 Module (e.g., CLRF 1, MOVWF
1, BSF 1,x ....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Ext. Clock Input or
Prescaler Out (Note 2)
(Note 3)
Ext. Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
1996-2013 Microchip Technology Inc.
DS30445D-page 27
PIC16C84
FIGURE 6-6:
BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
Data Bus
CLKOUT (= Fosc/4)
0
RA4/T0CKI
pin
M
U
X
8
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 register
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set bit T0IF
on overflow
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS30445D-page 28
1996-2013 Microchip Technology Inc.
PIC16C84
6.3.1
SWITCHING PRESCALER ASSIGNMENT
EXAMPLE 6-1:
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution).
Note:
To avoid an unintended device RESET, the
following
instruction
sequence
(Example 6-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be taken even if the WDT is disabled. To
change prescaler from the WDT to the
Timer0 module use the sequence shown in
Example 6-2.
TABLE 6-1
Address
Name
CHANGING PRESCALER
(TIMER0WDT)
BCF
CLRF
STATUS, RP0
TMR0
BSF
CLRWDT
MOVLW
MOVWF
BCF
STATUS, RP0
b'xxxx1xxx'
OPTION
STATUS, RP0
EXAMPLE 6-2:
;Bank 0
;Clear TMR0
; and Prescaler
;Bank 1
;Clears WDT
;Select new
; prescale value
;Bank 0
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
MOVWF
BCF
OPTION
STATUS, RP0
;Clear WDT and
; prescaler
;Bank 1
;Select TMR0, new
; prescale value
’ and clock source
;
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Timer0 module’s register
Value on all
other resets
01h
TMR0
xxxx xxxx
uuuu uuuu
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
1996-2013 Microchip Technology Inc.
DS30445D-page 29
PIC16C84
NOTES:
DS30445D-page 30
1996-2013 Microchip Technology Inc.
PIC16C84
7.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
•
•
•
•
EECON1
EECON2
EEDATA
EEADR
EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16C84 devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
7.1
EEADR
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 64 bytes of
data EEPROM are implemented.
The upper two bits are address decoded. This means
that these two bits must always be '0' to ensure that the
address is in the 64 byte memory space.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
FIGURE 7-1:
EECON1 REGISTER (ADDRESS 88h)
U
U
U
R/W-0
R/W-x
R/W-0
R/S-0
R/S-x
—
—
—
EEIF
WRERR
WREN
WR
RD
bit7
bit0
R
W
S
U
= Readable bit
= Writable bit
= Settable bit
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:5
Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read
1996-2013 Microchip Technology Inc.
DS30445D-page 31
PIC16C84
EECON1 and EECON2 Registers
EECON1 is the control register with five low order bits
physically implemented. The upper-three bits are nonexistent and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The data and
address will be unchanged in the EEDATA and
EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It
must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
7.3
Reading the EEPROM Data Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 7-1:
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF
DATA EEPROM READ
STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W
DS30445D-page 32
;
;
;
;
;
;
;
Bank 0
Address to read
Bank 1
EE Read
Bank 0
W = EEDATA
7.4
Writing to the EEPROM Data Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 7-1:
Required
Sequence
7.2
DATA EEPROM WRITE
BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
STATUS, RP0
INTCON, GIE
EECON1, WREN
55h
EECON2
AAh
EECON2
EECON1,WR
BSF
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
Bank 1
Disable INTs.
Enable Write
Write 55h
Write AAh
Set WR bit
begin write
Enable INTs.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
Note:
The data EEPROM memory E/W cycle
time may occasionally exceed the 10 ms
specification (typical). To ensure that the
write cycle is complete, use the EE
interrupt or poll the WR bit (EECON1<1>).
Both these events signify the completion of
the write cycle.
1996-2013 Microchip Technology Inc.
PIC16C84
7.5
Write Verify
7.6
Depending on the application, good programming practice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
Generally the EEPROM write failure will be a bit which
was written as a '1', but reads back as a '0' (due to
leakage off the bit).
EXAMPLE 7-1:
7.7
WRITE VERIFY
BCF
:
:
MOVF
BSF
STATUS, RP0 ;
;
;
EEDATA, W
;
STATUS, RP0 ;
BSF
EECON1, RD
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data EEPROM.
Must be in Bank 0
Bank 1
For ROM devices, there are two code protection bits
(Section 8.1). One for the ROM program memory and
one for the Data EEPROM memory.
; YES, Read the
;
value written
STATUS, RP0 ; Bank 0
7.8
Note:
;
; Is the value written (in W reg) and
;
read (in EEDATA) the same?
;
SUBWF EEDATA, W
;
BTFSS STATUS, Z
; Is difference 0?
GOTO WRITE_ERR
; NO, Write error
:
; YES, Good write
:
; Continue program
TABLE 7-1
Address
Data EEPROM Operation during Code
Protect
Bank 0
Any code can go here
READ
BCF
Protection Against Spurious Writes
Power Consumption Considerations
It is recommended that the EEADR<7:6>
bits be cleared. When either of these bits is
set, the maximum IDD for the device is
higher than when both are cleared. The
specification is 400 A. With EEADR<7:6>
cleared, the maximum is approximately
150 A.
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
08h
EEDATA
EEPROM data register
xxxx xxxx
uuuu uuuu
09h
EEADR
EEPROM address register
xxxx xxxx
uuuu uuuu
88h
EECON1
---0 x000
---0 q000
89h
EECON2
---- ----
---- ----
—
—
—
EEPROM control register 2
EEIF
WRERR
WREN
WR
RD
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
used by Data EEPROM.
1996-2013 Microchip Technology Inc.
DS30445D-page 33
PIC16C84
NOTES:
DS30445D-page 34
1996-2013 Microchip Technology Inc.
PIC16C84
8.0
SPECIAL FEATURES OF THE
CPU
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. This
design keeps the device in reset while the power supply
stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
What sets a microcontroller apart from other
processors are special circuits to deal with the needs of
real time applications. The PIC16C84 has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These features are:
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external reset, Watchdog Timer time-out or through an
interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.
• OSC selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
8.1
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
Address 2007h is beyond the user program memory
space and it belongs to the special test/configuration
memory space (2000h - 3FFFh). This space can only
be accessed during programming.
The PIC16C84 has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
FIGURE 8-1:
Configuration Bits
To find out how to program the PIC16C84, refer to
PIC16C84 EEPROM Memory Programming Specification (DS30189).
CONFIGURATION WORD
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
R/P-u
—
—
—
—
—
—
—
—
—
CP
bit13
R/P-u
R/P-u
R/P-u
R/P-u
PWRTE WDTE FOSC1 FOSC0
bit0
R = Readable bit
P = Programmable bit
U = Unimplemented bit,
read as ‘1’
- n = Value at POR reset
u = unchanged
bit 13:5 Unimplemented: Read as '1'
bit 4
CP: Code Protection bit
1 = Code protection off
0 = All memory is code protected
bit 3
PWRTE: Power-up Timer Enable bit
1 = Power-up timer is enabled
0 = Power-up timer is disabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0
FOSC1:FOSC0: Oscillator Selection bits
11 =RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
1996-2013 Microchip Technology Inc.
DS30445D-page 35
PIC16C84
8.2
Oscillator Configurations
8.2.1
OSCILLATOR TYPES
TABLE 8-1
Ranges Tested:
The PIC16C84 can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
LP
XT
HS
RC
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
8.2.2
Mode
Freq
XT
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
10.0 MHz
HS
Note :
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 8-2).
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
C1(1)
OSC1
XTAL
RF(3)
OSC2
SLEEP
RS(2)
PIC16CXX
C2(1)
Note1:
2:
3:
To
internal
logic
See Table 8-1 and Table 8-2 for recommended values of C1 and C2.
A series resistor (RS) may be required for
AT strip cut crystals.
RF varies with the crystal chosen.
The PIC16C84 oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the device
can have an external clock source to drive the OSC1/
CLKIN pin (Figure 8-3).
FIGURE 8-3:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
Clock from
ext. system
PIC16CXX
Open
DS30445D-page 36
OSC2
OSC1/C1
OSC2/C2
47 - 100 pF 47 - 100 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
Recommended values of C1 and C2 are identical to
the ranges tested table.
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for the
appropriate values of external components.
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
FIGURE 8-2:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Resonators Tested:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
10.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA10.00MTZ
0.3%
0.5%
0.5%
0.5%
0.5%
None of the resonators had built-in capacitors.
TABLE 8-2
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Mode
Freq
LP
32 kHz
200 kHz
100 kHz
2 MHz
4 MHz
4 MHz
10 MHz
XT
HS
Note :
OSC1/C1
OSC2/C2
68 - 100 pF
68 - 100 pF
15 - 33 pF
15 - 33 pF
100 - 150 pF 100 - 150 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
Higher capacitance increases the stability of
oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level specification. Since each crystal has its own
characteristics, the user should consult the crystal
manufacturer for appropriate values of external
components.
For VDD > 4.5V, C1 = C2 30 pF is recommended.
Crystals Tested:
32.768 kHz
100 kHz
200 kHz
1.0 MHz
2.0 MHz
4.0 MHz
10.0 MHz
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 KHz
ECS ECS-10-13-2
ECS ECS-20-S-2
ECS ECS-40-S-4
ECS ECS-100-S-4
20 PPM
20 PPM
20 PPM
50 PPM
50 PPM
50 PPM
50 PPM
1996-2013 Microchip Technology Inc.
PIC16C84
8.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
8.2.4
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits are
available; one with series resonance, and one with
parallel resonance.
Figure 8-4 shows a parallel resonant oscillator circuit.
The circuit is designed to use the fundamental
frequency of the crystal. The 74AS04 inverter performs
the 180-degree phase shift that a parallel oscillator
requires. The 4.7 k resistor provides negative
feedback for stability. The 10 k potentiometer biases
the 74AS04 in the linear region. This could be used for
external oscillator designs.
FIGURE 8-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
PIC16CXX
10k
74AS04
4.7k
CLKIN
74AS04
10k
XTAL
10k
20 pF
20 pF
Figure 8-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180degree phase shift. The 330 k resistors provide the
negative feedback to bias the inverters in their linear
region.
FIGURE 8-5:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
RC OSCILLATOR
For timing insensitive applications the RC device option
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) values, capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types also affects the oscillation frequency, especially
for low Cext values. The user needs to take into
account variation due to tolerance of the external
R and C components. Figure 8-6 shows how an R/C
combination is connected to the PIC16C84. For Rext
values below 2.2 k, the oscillator operation may
become unstable, or stop completely. For very high
Rext values (e.g., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend keeping Rext between 3 k and 100 k.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
See the electrical specification section for RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance has a greater affect on
RC frequency).
See the electrical specification section for variation of
oscillator frequency due to VDD for given Rext/Cext
values as well as frequency variation due to
operating temperature.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (see Figure 3-2
for waveform).
FIGURE 8-6:
RC OSCILLATOR MODE
VDD
Rext
Internal
clock
OSC1
330 k
330 k
74AS04
74AS04
To Other
Devices
PIC16CXX
Cext
VSS
74AS04
CLKIN
0.1F
Fosc/4
Recommended values:
XTAL
Note:
1996-2013 Microchip Technology Inc.
PIC16CXX
OSC2/CLKOUT
3 k Rext 100 k
Cext > 20pF
When the device oscillator is in RC mode,
do not drive the OSC1 pin with an external
clock or you may damage the device.
DS30445D-page 37
PIC16C84
8.3
Reset
The PIC16C84 differentiates between various kinds
of reset:
•
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Figure 8-7 shows a simplified block diagram of the onchip reset circuit. The electrical specifications state the
pulse width requirements for the MCLR pin.
FIGURE 8-7:
Some registers are not affected in any reset condition;
their status is unknown on a POR reset and unchanged
in any other reset. Most other registers are reset to a
“reset state” on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
They are not affected by a WDT reset during SLEEP,
since this reset is viewed as the resumption of normal
operation.
Table 8-3 gives a description of reset conditions for the
program counter (PC) and the STATUS register.
Table 8-4 gives a full description of reset states for all
registers.
The TO and PD bits are set or cleared differently in different reset situations (Section 8.7). These bits are
used in software to determine the nature of the reset.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
SLEEP
WDT
Time_Out
Reset
VDD rise
detect
Power_on_Reset
S
10-bit Ripple counter
R
VDD
OST/PWRT
OST
Chip_Reset
Q
OSC1/
CLKIN
PWRT
On-chip
RC OSC(1)
10-bit Ripple counter
Enable PWRT
Note 1: This is a separate oscillator from the
RC oscillator of the CLKIN pin.
DS30445D-page 38
See Table 8-5
Enable OST
1996-2013 Microchip Technology Inc.
PIC16C84
TABLE 8-3
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Program Counter
Condition
STATUS Register
Power-on Reset
000h
0001 1xxx
MCLR Reset during normal operation
000h
000u uuuu
MCLR Reset during SLEEP
000h
0001 0uuu
WDT Reset (during normal operation)
000h
0000 1uuu
WDT Wake-up
PC + 1
Interrupt wake-up from SLEEP
PC + 1
uuu0 0uuu
(1)
uuu1 0uuu
Legend: u = unchanged, x = unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 8-4
Register
W
RESET CONDITIONS FOR ALL REGISTERS
Address
Power-on Reset
MCLR Reset during:
– normal operation
– SLEEP
WDT Reset during normal operation
Wake-up from SLEEP:
– through interrupt
– through WDT time-out
—
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h
---- ----
---- ----
---- ----
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h
0000h
0000h
STATUS
03h
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
04h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
---x xxxx
---u uuuu
---u uuuu
PORTB
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATA
08h
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
09h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
0Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh
0000 000x
0000 000u
uuuu uuuu(1)
INDF
80h
---- ----
---- ----
---- ----
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
PCL
82h
0000h
0000h
PC + 1(2)
PC + 1
(3)
uuuq quuu(3)
STATUS
83h
0001 1xxx
000q quuu
FSR
84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TRISA
85h
---1 1111
---1 1111
---u uuuu
TRISB
86h
1111 1111
1111 1111
uuuu uuuu
EECON1
88h
---0 x000
---0 q000
---0 uuuu
EECON2
89h
---- ----
---- ----
---- ----
PCLATH
8Ah
---0 0000
---0 0000
---u uuuu
INTCON
8Bh
0000 000x
0000 000u
uuuu uuuu(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0',
q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 8-3 lists the reset value for each specific condition.
1996-2013 Microchip Technology Inc.
DS30445D-page 39
PIC16C84
8.4
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD
must be met for this to operate properly. See Electrical
Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions
are met.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting.
The POR circuit does not produce an internal reset
when VDD declines.
8.5
Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (TPWRT) from POR (Figure 8-9,
Figure 8-10, Figure 8-11 and Figure 8-12). The Powerup Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT delay allows the VDD to rise to an acceptable
level (Possible exception shown in Figure 8-12).
FIGURE 8-8:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
VDD
VDD
D
R
R1
MCLR
C
PIC16CXX
Note 1: External Power-on Reset circuit is required
only if VDD power-up rate is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade VIH level on the MCLR pin.
3: R1 = 100 to 1 k will limit any current
flowing into MCLR from external
capacitor C in the event of an MCLR pin
breakdown due to ESD or EOS.
A configuration bit, PWRTE, can enable/disable the
PWRT (Figure 8-1).
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
8.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 8-9, Figure 8-10, Figure 811 and Figure 8-12). This ensures the crystal oscillator
or resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case (Figure 812), an external power-on reset circuit may be necessary (Figure 8-8).
DS30445D-page 40
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 8-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1996-2013 Microchip Technology Inc.
DS30445D-page 41
PIC16C84
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
DS30445D-page 42
1996-2013 Microchip Technology Inc.
PIC16C84
8.7
Time-out Sequence and Power Down
Status Bits (TO/PD)
On power-up (Figure 8-9, Figure 8-10, Figure 8-11 and
Figure 8-12) the time-out sequence is as follows: First
PWRT time-out is invoked after a POR has expired.
Then the OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE
configuration bit status. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
TABLE 8-5
Power-up
PWRT
Enabled
PWRT
Disabled
Wake-up
from
SLEEP
XT, HS, LP
72 ms +
1024TOSC
1024TOSC
1024TOSC
RC
72 ms
—
—
Since the time-outs occur from the POR reset pulse, if
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin
immediately (Figure 8-9). This is useful for testing
purposes or to synchronize more than one PIC16CXX
device when operating in parallel.
Table 8-6 shows the significance of the TO and PD bits.
Table 8-3 lists the reset conditions for some special
registers, while Table 8-4 lists the reset conditions for
all the registers.
TABLE 8-6
Reset on Brown-Out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
To reset PIC16C84 devices when a brown-out occurs,
external brown-out protection circuits may be built, as
shown in Figure 8-13 and Figure 8-14.
FIGURE 8-13: BROWN-OUT PROTECTION
CIRCUIT 1
TIME-OUT IN VARIOUS
SITUATIONS
Oscillator
Configuration
8.8
STATUS BITS AND THEIR
SIGNIFICANCE
VDD
VDD
33k
10k
MCLR
40k
PIC16CXX
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
FIGURE 8-14: BROWN-OUT PROTECTION
CIRCUIT 2
VDD
VDD
TO
PD
1
0
x
0
0
1
1
1
x
0
1
0
1
0
Condition
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset (during normal operation)
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt
wake-up from SLEEP
R1
Q1
MCLR
R2
40k
This brown-out circuit is less expensive, although less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
VDD •
1996-2013 Microchip Technology Inc.
PIC16CXX
R1
R1 + R2
= 0.7V
DS30445D-page 43
PIC16C84
8.9
Interrupts
The PIC16C84 has 4 sources of interrupt:
•
•
•
•
External interrupt RB0/INT pin
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which reenable interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
When an interrupt is responded to; the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs
(Figure 8-16). The latency is the same for both one and
two cycle instructions. Once in the interrupt service
routine the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling
interrupts to avoid infinite interrupt requests.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
Note 2: If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be reenabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1.
An instruction clears the GIE bit while
an interrupt is acknowledged
2.
The program branches to the
Interrupt vector and executes the
Interrupt Service Routine.
3.
The Interrupt Service Routine
completes with the execution of the
RETFIE instruction. This causes the
GIE bit to be set (enables interrupts),
and the program returns to the
instruction after the one which was
meant to disable interrupts.
The method to ensure that interrupts are
globally disabled is:
1.
LOOP
BCF
Ensure that the GIE bit is cleared by
the instruction, as shown in the
following code:
INTCON,GIE
BTFSC INTCON,GIE
GOTO
DS30445D-page 44
LOOP
;Disable All
; Interrupts
;All Interrupts
; Disabled?
;NO, try again
; Yes, continue
; with program
; flow
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 8-15: INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE
FIGURE 8-16: INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF flag
(INTCON<1>)
Interrupt Latency 2
5
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC+1
Inst (PC+1)
Inst (PC)
0004h
PC+1
—
Dummy Cycle
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
1996-2013 Microchip Technology Inc.
DS30445D-page 45
PIC16C84
8.9.1
8.10
INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.9.2
TMR0 INTERRUPT
An overflow (FFh 00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 6.0).
8.9.3
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and
STATUS register). This is implemented in software.
Example 8-1 stores and restores the STATUS and W
register’s values. The User defined registers, W_TEMP
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
Example 8-1 does the following:
a)
b)
c)
d)
e)
Stores the W register.
Stores the STATUS register in STATUS_TEMP.
Executes the Interrupt Service Routine code.
Restores the STATUS (and bank select bit)
register.
Restores the W register.
PORT RB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 5.2).
Note 1: If a change on an I/O pin should occur
when a read operation of PORTB is being
executed (start of the Q2 cycle), the RBIF
interrupt flag bit may not get set.
EXAMPLE 8-1:
PUSH
ISR
POP
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
W_TEMP
STATUS, W
STATUS_TEMP
MOVWF
STATUS
SWAPF
SWAPF
W_TEMP, F
W_TEMP, W
DS30445D-page 46
STATUS_TEMP, W
;
;
;
:
;
;
;
;
;
;
;
;
Copy W to TEMP register,
Swap status to be saved into W
Save status to STATUS_TEMP register
Interrupt Service Routine
should configure Bank as required
Swap nibbles in STATUS_TEMP register
and place result into W
Move W into STATUS register
(sets bank to original state)
Swap nibbles in W_TEMP and place result in W_TEMP
; Swap nibbles in W_TEMP and place result into W
1996-2013 Microchip Technology Inc.
PIC16C84
8.11
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT Wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 8.1).
8.11.1
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device
RESET condition.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
8.11.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
FIGURE 8-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
WDT Timer
1
•
M
U
X
Postscaler
8
8 - to -1 MUX
PS2:PS0
•
To TMR0 (Figure 6-6)
PSA
WDT
Enable Bit
1
0
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 8-7
Address
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
2007h
Config. bits
81h
OPTION_
REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
CP
PWRTE
WDTE
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Value on
Power-on
Reset
Value on all
other resets
1111 1111
1111 1111
Legend: x = unknown. Shaded cells are not used by the WDT.
1996-2013 Microchip Technology Inc.
DS30445D-page 47
PIC16C84
8.12
Power-down Mode (SLEEP)
8.12.2
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
8.12.1
SLEEP
The Power-down mode is entered by executing the
SLEEP instruction.
If enabled, the Watchdog Timer is cleared (but keeps
running), the PD bit (STATUS<3>) is cleared, the TO bit
(STATUS<4>) is set, and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high, low,
or hi-impedance).
For the lowest current consumption in SLEEP mode,
place all I/O pins at either at VDD or VSS, with no
external circuitry drawing current from the I/O pins, and
disable external clocks. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS. The
contribution from on-chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (VIHMC).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
WDT Wake-up (if WDT was enabled).
Interrupt from RB0/INT pin, RB port change, or
data EEPROM write complete.
Peripherals cannot generate interrupts during SLEEP,
since no on-chip Q clocks are present.
The first event (MCLR reset) will cause a device reset.
The two latter events are considered a continuation of
program execution. The TO and PD bits can be used to
determine the cause of a device reset. The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up).
While the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 8-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst(PC) = SLEEP
Instruction
executed
Inst(PC - 1)
Note
1:
2:
3:
4:
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30445D-page 48
1996-2013 Microchip Technology Inc.
PIC16C84
8.12.3
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep . The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and
the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
8.13
Program Verification/Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
8.14
Microchip does not recommend code protecting windowed devices..
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations to store checksum or other code
identification numbers. These locations are not
accessible during normal execution but are readable
and writable only during program/verify. Only the
4 least significant bits of ID location are usable.
For ROM devices, these values are submitted along
with the ROM code.
8.15
In-Circuit Serial Programming
PIC16C84
microcontrollers
can
be
serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product,
allowing the most recent firmware or custom firmware
to be programmed.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR pin from VIL to VIHH (see PIC16C84 EEPROM
Memory Programming Specification (DS30189)). RB6
becomes the programming clock and RB7 becomes
the programming data. Both RB6 and RB7 are Schmitt
Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) points to location 00h.
A 6-bit command is then supplied to the device, 14-bits
of program data is then supplied to or from the device,
using load or read-type instructions. For complete
details of serial programming, please refer to the In-Circuit Serial Programming Guide (DS30277).
For ROM devices, both the program memory and Data
EEPROM memory may be read, but only the Data
EEPROM memory may be programmed.
FIGURE 8-19: TYPICAL IN-SYSTEM SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC16CXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
1996-2013 Microchip Technology Inc.
DS30445D-page 49
PIC16C84
NOTES:
DS30445D-page 50
1996-2013 Microchip Technology Inc.
PIC16C84
9.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 9-1
OPCODE FIELD
DESCRIPTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Label name
TOS
Top of Stack
PC
Program Counter
PCLATH
Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
dest
Destination either the W register or the specified
register file location
[ ]
Options
italics
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 s.
Table 9-2 lists the instructions recognized by the
MPASM assembler.
Figure 9-1 shows the general formats that the instructions can have.
Note:
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label
( )
<>
The instruction set is highly orthogonal and is grouped
into three basic categories:
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
Contents
0
k (literal)
k = 8-bit immediate value
Assigned to
Register bit field
In the set of
User defined term (font is courier)
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
1996-2013 Microchip Technology Inc.
DS30445D-page 51
PIC16C84
TABLE 9-2
PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30445D-page 52
1996-2013 Microchip Technology Inc.
PIC16C84
9.1
Instruction Descriptions
ADDLW
Add Literal and W
ANDLW
AND Literal with W
Syntax:
[label] ADDLW
Syntax:
[label] ANDLW
Operands:
0 k 255
Operands:
0 k 255
Operation:
(W) + k (W)
Operation:
(W) .AND. (k) (W)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
11
k
111x
kkkk
kkkk
Encoding:
11
k
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
ADDLW
0x15
Q Cycle Activity:
Example
=
=
ADDWF
Add W and f
Q3
Q4
Process
data
Write to
W
ANDLW
0x5F
W
0x10
=
0xA3
After Instruction
After Instruction
W
Q2
Read
literal "k"
Before Instruction
Before Instruction
W
Q1
Decode
W
0x25
=
ANDWF
AND W with f
0x03
Syntax:
[label] ADDWF
Syntax:
[label] ANDWF
Operands:
0 f 127
d
Operands:
0 f 127
d
Operation:
(W) + (f) (destination)
Operation:
(W) .AND. (f) (destination)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
00
f,d
0111
dfff
ffff
Encoding:
00
f,d
0101
dfff
ffff
Description:
Add the contents of the W register with
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
AND the W register with register 'f'. If 'd'
is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in
register 'f'.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
ADDWF
FSR, 0
Before Instruction
W =
FSR =
1996-2013 Microchip Technology Inc.
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
ANDWF
FSR, 1
Before Instruction
0x17
0xC2
After Instruction
W =
FSR =
Q Cycle Activity:
W =
FSR =
0x17
0xC2
After Instruction
0xD9
0xC2
W =
FSR =
0x17
0x02
DS30445D-page 53
PIC16C84
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[label] BCF
Syntax:
[label] BTFSC f,b
Operands:
0 f 127
0b7
Operands:
0 f 127
0b7
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
BCF
Encoding:
10bb
bfff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is executed.
If bit 'b', in register 'f', is '0' then the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
FLAG_REG, 7
01
Description:
Before Instruction
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
No-Operat
ion
Q3
Q4
FLAG_REG = 0xC7
If Skip:
After Instruction
FLAG_REG = 0x47
(2nd Cycle)
Q1
Q2
No-Operat
ion
Example
HERE
FALSE
TRUE
No-Operati No-Opera No-Operat
on
tion
ion
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC =
address HERE
After Instruction
BSF
Bit Set f
Syntax:
[label] BSF
Operands:
0 f 127
0b7
Operation:
1 (f<b>)
Status Affected:
None
Encoding:
Description:
01
1
Cycles:
1
Example
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
Words:
Q Cycle Activity:
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
f,b
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30445D-page 54
1996-2013 Microchip Technology Inc.
PIC16C84
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[label] BTFSS f,b
Syntax:
[ label ] CALL k
Operands:
0 f 127
0b<7
Operands:
0 k 2047
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected:
None
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
Description:
01
1
Cycles:
1(2)
If Skip:
ffff
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
No-Operat
ion
(2nd Cycle)
Q1
Q2
No-Operat
ion
Example
bfff
If bit 'b' in register 'f' is '0' then the next
instruction is executed.
If bit 'b' is '1', then the next instruction is
discarded and a NOP is executed
instead, making this a 2TCY instruction.
Words:
Q Cycle Activity:
11bb
HERE
FALSE
TRUE
Q3
10
Words:
1
Cycles:
2
Q Cycle Activity:
FLAG,1
PROCESS_CODE
2nd Cycle
Example
0kkk
kkkk
kkkk
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH. CALL
is a two cycle instruction.
Q1
Q2
Q3
Q4
Decode
Read
literal 'k',
Push PC
to Stack
Process
data
Write to
PC
Q4
No-Opera
tion
HERE
No-Opera No-Opera No-Operat
tion
tion
ion
CALL
THERE
Before Instruction
PC = Address HERE
After Instruction
Before Instruction
PC =
Description:
1st Cycle
No-Operati No-Opera No-Operat
on
tion
ion
BTFSC
GOTO
•
•
•
Encoding:
address HERE
PC = Address THERE
TOS = Address HERE+1
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
1996-2013 Microchip Technology Inc.
DS30445D-page 55
PIC16C84
CLRF
Clear f
Syntax:
[label] CLRF
Operands:
0 f 127
Operation:
00h (f)
1Z
Status Affected:
Z
Encoding:
00
f
0001
1fff
ffff
Description:
The contents of register 'f' are cleared
and the Z bit is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
CLRF
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Z
Encoding:
0xxx
xxxx
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No-Opera
tion
Process
data
Write to
W
CLRW
Before Instruction
Before Instruction
=
0x5A
=
=
0x00
1
W
=
0x5A
After Instruction
After Instruction
FLAG_REG
Z
0001
W register is cleared. Zero bit (Z) is
set.
Example
FLAG_REG
FLAG_REG
00
Description:
W
Z
=
=
0x00
1
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
TO, PD
Encoding:
00
0000
0110
0100
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
No-Opera
tion
Process
data
Clear
WDT
Counter
CLRWDT
Before Instruction
WDT counter =
?
After Instruction
WDT counter =
WDT prescaler=
TO
=
PD
=
DS30445D-page 56
0x00
0
1
1
1996-2013 Microchip Technology Inc.
PIC16C84
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Z
Encoding:
Description:
00
f,d
1001
dfff
ffff
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Status Affected:
None
Encoding:
COMF
0x13
1
Cycles:
1(2)
=
=
0x13
0xEC
If Skip:
After Instruction
REG1
W
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
Q3
Q4
Decrement f
Syntax:
[label] DECF f,d
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Z
Example
DECFSZ
GOTO
CONTINUE •
•
•
CNT, 1
LOOP
Before Instruction
00
0011
dfff
ffff
Description:
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
1
Cycles:
1
Example
No-Opera No-Operat No-Operati
tion
ion
on
HERE
PC
Encoding:
Q Cycle Activity:
(2nd Cycle)
Q1
Q2
No-Operat
ion
DECF
ffff
Words:
Before Instruction
=
dfff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 1, the next instruction, is
executed. If the result is 0, then a NOP is
executed instead making it a 2TCY instruction.
REG1,0
REG1
1011
Description:
Q Cycle Activity:
Example
00
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
DECF
=
address HERE
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
CNT, 1
Before Instruction
CNT
Z
=
=
0x01
0
=
=
0x00
1
After Instruction
CNT
Z
1996-2013 Microchip Technology Inc.
DS30445D-page 57
PIC16C84
Unconditional Branch
INCF
Increment f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 2047
Operands:
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
None
Status Affected:
Z
GOTO
Status Affected:
Encoding:
10
GOTO k
1kkk
kkkk
kkkk
dfff
ffff
1
Words:
1
2
Cycles:
1
Words:
Cycles:
2nd Cycle
1010
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruction.
1st Cycle
00
Description:
Description:
Q Cycle Activity:
Encoding:
INCF f,d
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
PC
No-Operat
ion
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
No-Operat No-Opera No-Operat
ion
tion
ion
Example
INCF
CNT, 1
Before Instruction
Example
GOTO THERE
CNT
Z
After Instruction
PC =
DS30445D-page 58
Address THERE
=
=
0xFF
0
=
=
0x00
1
After Instruction
CNT
Z
1996-2013 Microchip Technology Inc.
PIC16C84
INCFSZ
Increment f, Skip if 0
IORLW
Inclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
(W) .OR. k (W)
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
Z
Status Affected:
00
1
Cycles:
1(2)
If Skip:
dfff
ffff
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
Q3
Q4
(2nd Cycle)
Q1
Q2
No-Operat
ion
Example
1111
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 1, the next instruction is
executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction.
Words:
Q Cycle Activity:
Encoding:
None
Encoding:
Description:
INCFSZ f,d
11
IORLW k
1000
kkkk
kkkk
Description:
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
IORLW
0x35
Before Instruction
W
=
0x9A
After Instruction
W
Z
=
=
0xBF
1
No-Opera No-Opera No-Operati
tion
tion
on
HERE
INCFSZ
GOTO
CONTINUE •
•
•
CNT, 1
LOOP
Before Instruction
PC
=
address HERE
After Instruction
CNT =
if CNT=
PC
=
if CNT
PC
=
CNT + 1
0,
address CONTINUE
0,
address HERE +1
1996-2013 Microchip Technology Inc.
DS30445D-page 59
PIC16C84
IORWF
Inclusive OR W with f
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k (W)
Status Affected:
None
IORWF
f,d
Operation:
(W) .OR. (f) (destination)
Status Affected:
Z
Encoding:
Description:
00
0100
dfff
ffff
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Encoding:
11
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
IORWF
00xx
kkkk
kkkk
Description:
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
MOVLW k
Example
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
MOVLW
0x5A
After Instruction
RESULT, 0
W
=
0x5A
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
RESULT =
W
=
Z
=
0x13
0x93
1
MOVWF
Move W to f
Syntax:
[ label ]
0 f 127
d [0,1]
Operands:
0 f 127
Operation:
(W) (f)
Operation:
(f) (destination)
Status Affected:
None
Status Affected:
Z
Encoding:
MOVF
Move f
Syntax:
[ label ]
Operands:
Encoding:
Description:
00
1000
dfff
ffff
The contents of register f is moved to a
destination dependant upon the status
of d. If d = 0, destination is W register. If
d = 1, the destination is file register f
itself. d = 1 is useful to test a file register since status flag Z is affected.
Words:
1
Cycles:
1
Q Cycle Activity:
MOVF f,d
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
00
MOVWF
0000
f
1fff
ffff
Description:
Move data from W register to register
'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
MOVWF
OPTION_REG
Before Instruction
OPTION =
W
=
0xFF
0x4F
After Instruction
Example
MOVF
FSR, 0
After Instruction
OPTION =
W
=
0x4F
0x4F
W = value in FSR register
Z =1
DS30445D-page 60
1996-2013 Microchip Technology Inc.
PIC16C84
NOP
No Operation
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS PC,
1 GIE
Status Affected:
None
Encoding:
00
NOP
0000
Description:
No operation.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example
0xx0
0000
Encoding:
Q2
Q3
0000
0000
1001
Description:
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Words:
1
Cycles:
2
Q4
No-Opera No-Opera No-Operat
tion
tion
ion
NOP
00
RETFIE
Q Cycle Activity:
1st Cycle
2nd Cycle
Example
Q1
Q2
Q3
Q4
Decode
No-Opera
tion
Set the
GIE bit
Pop from
the Stack
No-Operat
ion
No-Opera No-Opera No-Operat
tion
tion
ion
RETFIE
After Interrupt
PC =
GIE =
OPTION
Load Option Register
Syntax:
[ label ]
Operands:
None
Operation:
(W) OPTION
TOS
1
OPTION
Status Affected: None
Encoding:
00
0000
0110
0010
Description:
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words:
1
Cycles:
1
Example
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
1996-2013 Microchip Technology Inc.
DS30445D-page 61
PIC16C84
RETLW
Return with Literal in W
RETURN
Return from Subroutine
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W);
TOS PC
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
RETLW k
11
Description:
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
1st Cycle
2nd Cycle
Q1
Q2
Q3
Q4
Read
literal 'k'
No-Opera
tion
Write to
W, Pop
from the
Stack
No-Opera No-Opera No-Operat
tion
tion
ion
No-Operat
ion
0000
Words:
1
Cycles:
2
1st Cycle
2nd Cycle
Example
Q1
Decode
No-Operat
ion
Q2
Q3
Q4
No-Opera No-Opera Pop from
tion
tion
the Stack
No-Opera No-Opera No-Opera
tion
tion
tion
RETURN
After Interrupt
CALL TABLE
TOS
;W contains table
;offset value
;W now has table value
•
•
•
TABLE ADDWF PC
RETLW k1
RETLW k2
1000
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter. This
is a two cycle instruction.
PC =
Example
0000
Description:
Q Cycle Activity:
Decode
00
RETURN
;W = offset
;Begin table
;
•
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
DS30445D-page 62
=
value of k8
1996-2013 Microchip Technology Inc.
PIC16C84
RLF
Rotate Left f through Carry
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
See description below
Operation:
See description below
Status Affected:
C
Status Affected:
C
Encoding:
Description:
RLF
00
1101
f,d
dfff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
C
Encoding:
Description:
00
Register f
C
1
Words:
1
Cycles:
1
Cycles:
1
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
RLF
REG1,0
1996-2013 Microchip Technology Inc.
dfff
ffff
Register f
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
RRF
REG1,0
Before Instruction
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
After Instruction
REG1
W
C
Q Cycle Activity:
Example
Before Instruction
REG1
C
1100
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Words:
Q Cycle Activity:
RRF f,d
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
0111 0011
0
After Instruction
REG1
W
C
DS30445D-page 63
PIC16C84
SLEEP
SUBLW
Subtract W from Literal
Syntax:
[ label ]
SUBLW k
Syntax:
[ label ]
Operands:
None
Operands:
0 k 255
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Operation:
k - (W) W)
Status Affected:
C, DC, Z
SLEEP
Encoding:
11
110x
kkkk
kkkk
Description:
The W register is subtracted (2’s complement method) from the eight bit literal 'k'.
The result is placed in the W register.
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped. See
Section 14.8 for more details.
Words:
1
Cycles:
1
Words:
1
Example 1:
Cycles:
1
Status Affected:
TO, PD
Encoding:
Description:
Q Cycle Activity:
00
0000
0110
0011
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to W
SUBLW
0x02
Before Instruction
Q1
Decode
Q2
Q3
No-Opera No-Opera
tion
tion
Q4
W
C
Z
Go to
Sleep
=
=
=
1
?
?
After Instruction
Example:
SLEEP
W
C
Z
Example 2:
=
=
=
1
1; result is positive
0
Before Instruction
W
C
Z
=
=
=
2
?
?
After Instruction
W
C
Z
Example 3:
=
=
=
0
1; result is zero
1
Before Instruction
W
C
Z
=
=
=
3
?
?
After Instruction
W
C
Z
DS30445D-page 64
=
=
=
0xFF
0; result is negative
0
1996-2013 Microchip Technology Inc.
PIC16C84
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
Syntax:
[ label ] SWAPF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - (W) destination)
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected:
None
SUBWF f,d
Status Affected: C, DC, Z
Encoding:
Description:
00
1
Cycles:
1
Example 1:
dfff
ffff
Subtract (2’s complement method) W register from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Words:
Q Cycle Activity:
0010
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
SUBWF
00
Example 2:
=
=
=
=
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
SWAPF REG,
=
=
=
=
=
=
=
=
Example 3:
=
=
=
=
REG1
=
=
=
=
REG1
W
=
=
=
=
1996-2013 Microchip Technology Inc.
0xA5
=
=
0xA5
0x5A
1
2
1; result is positive
0
2
2
?
?
TRIS
Load TRIS Register
Syntax:
[label]
Operands:
5f7
Operation:
(W) TRIS register f;
TRIS
f
Status Affected: None
0
2
1; result is zero
1
1
2
?
?
After Instruction
REG1
W
C
Z
=
After Instruction
Encoding:
0xFF
2
0; result is negative
0
00
0000
0110
0fff
Description:
The instruction is supported for code
compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly
address them.
Words:
1
Cycles:
1
Before Instruction
REG1
W
C
Z
0
Before Instruction
3
2
?
?
After Instruction
REG1
W
C
Z
ffff
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Example
Before Instruction
REG1
W
C
Z
dfff
Description:
After Instruction
REG1
W
C
Z
1110
REG1,1
Before Instruction
REG1
W
C
Z
Encoding:
Example
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
DS30445D-page 65
PIC16C84
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[label]
Syntax:
[label]
Operands:
0 k 255
Operands:
Operation:
(W) .XOR. k W)
0 f 127
d [0,1]
Status Affected:
Z
Operation:
(W) .XOR. (f) destination)
Status Affected:
Z
Encoding:
11
XORLW k
1010
kkkk
kkkk
Description:
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Words:
1
Cycles:
1
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
XORLW
Encoding:
00
XORWF
0110
f,d
dfff
ffff
Description:
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
0xAF
Before Instruction
W
=
Example
0xB5
After Instruction
W
=
0x1A
XORWF
REG
1
Before Instruction
REG
W
=
=
0xAF
0xB5
=
=
0x1A
0xB5
After Instruction
REG
W
DS30445D-page 66
1996-2013 Microchip Technology Inc.
PIC16C84
10.0
DEVELOPMENT SUPPORT
10.1
Development Tools
The PICmicr microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER/PICMASTER CEReal-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLABSIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECHMP)
10.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the SX, PIC14C000, PIC16C5X,
PIC16CXXX and PIC17CXX families. PICMASTER is
supplied with the MPLAB Integrated Development
Environment (IDE), which allows editing, “make” and
download, and source debugging from a single environment.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
10.3
ICEPIC: Low-Cost PIC MCU
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.
10.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
10.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is not
recommended for production programming.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
The PICMASTER Emulator System has been designed
as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x environment were chosen to best make these features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1996-2013 Microchip Technology Inc.
DS30445D - page 67
PIC16C84
10.6
PICDEM-1 Low-Cost PIC MCU
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
10.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
10.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
DS30445D - page 68
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
10.9
MPLAB™ Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC MCU tools (automatically updates all project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
10.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
1996-2013 Microchip Technology Inc.
PIC16C84
MPASM has the following features to assist in developing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PIC MCU. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
10.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC MCU series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
10.12
C Compiler (MPLAB-C)
10.14
MP-DriveWay – Application Code
Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC device
and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip’s
MPLAB-C C compiler. The code produced is highly
modular and allows easy integration of your own code.
MP-DriveWay is intelligent enough to maintain your
code through subsequent code generation.
10.15
SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
10.16
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC family of microcontrollers. The compiler provides powerful integration
capabilities and ease of use not found with other
compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display.
10.13
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
1996-2013 Microchip Technology Inc.
DS30445D - page 69
Emulator Products
Software Tools
DS30445D - page 70
Programmers
✔
Evaluation Kit
KEELOQ
PICDEM-3
PICDEM-2
PICDEM-1
SEEVAL
Designers Kit
KEELOQ
Programmer
PRO
II
Universal
Programmer
MATE
Plus Low-Cost
Universal Dev. Kit
PICSTART
PICSTART
Lite Ultra Low-Cost
Dev. Kit
Total Endurance
Software Model
✔
✔
✔
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
MP-DriveWay
Applications
Code Generator
✔
MPLAB C
Compiler
✔
✔
MPLAB
Integrated
Development
Environment
ICEPIC Low-Cost
In-Circuit Emulator
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
✔
✔
✔
✔
✔
✔
PIC14000
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C5X
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16CXXX
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
✔
✔
✔
✔
Available
3Q97
PIC17C75X
✔
✔
✔
24CXX
25CXX
93CXX
✔
✔
✔
HCS200
HCS300
HCS301
TABLE 10-1:
Demo Boards
PIC12C5XX
PIC16C84
DEVELOPMENT TOOLS FROM MICROCHIP
1996-2013 Microchip Technology Inc.
PIC16C84
11.0
ELECTRICAL CHARACTERISTICS FOR PIC16C84
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-55C to +125C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on VDD with respect to VSS ............................................................................................................. -0.3 to +7.5V
Voltage on MCLR with respect to VSS(2) .......................................................................................................-0.3 to +14V
Voltage on all other pins with respect to VSS .................................................................................. -0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO >VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk byPORTA ..........................................................................................................................80 mA
Maximum current sourced by PORTA .....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB...................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996-2013 Microchip Technology Inc.
DS30445D-page 71
PIC16C84
TABLE 11-1
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC
PIC16C84-04
PIC16C84-10
PIC16LC84-04
RC
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
4.5 mA max. at 5.5V
100 A max. at 4.0V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
1.8 mA typ. at 5.5V
40.0 A typ. at 4.5V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
4.5 mA max. at 5.5V
100 A max. at 4V WDT dis
2.0 MHz max.
XT
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
4.5 mA max. at 5.5V
100 A max. at 4.0V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
1.8 mA typ. at 5.5V
40.0 A typ. at 4.5V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
4.5 mA max. at 5.5V
100 A max. at 4V WDT dis
2.0 MHz max.
HS
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
4.5 mA typ. at 5.5V
40.0 A typ. at 4.5V WDT dis
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
10 mA max. at 5.5V typ.
40.0 A typ. at 4.5V WDT dis
10 MHz max.
Do not use in HS mode
LP
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
60 A typ. at 32 kHz, 2.0V
26 A typ. at 2.0V WDT dis
200 kHz max.
Do not use in LP mode
VDD:
IDD:
IPD:
Freq:
2.0V to 6.0V
400 A max. at 32 kHz, 2.0V
100 A max. at 4.0V WDT dis
200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is
recommended that the user select the device type that ensures the specifications required.
DS30445D-page 72
1996-2013 Microchip Technology Inc.
PIC16C84
11.1
DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial)
PIC16C84-10 (Commercial, Industrial)
DC Characteristics
Power Supply Pins
Parameter No.
D001
D001A
D002
D003
D004
D010
D010A
Sym
VDD
Characteristic
Supply Voltage
VDR
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
Min Typ† Max Units
Conditions
4.0
4.5
1.5*
RAM Data Retention
Voltage(1)
—
VPOR VDD start voltage to
ensure internal Poweron Reset signal
SVDD VDD rise rate to ensure 0.05*
internal Power-on
Reset signal
Supply Current (2)
IDD
—
—
—
—
—
6.0
5.5
—
V
V
V
XT, RC and LP osc configuration
HS osc configuration
Device in SLEEP mode
VSS
—
V
See section on Power-on Reset for details
—
—
1.8
7.3
4.5
10
V/ms See section on Power-on Reset for details
mA
mA
RC and XT osc configuration(4)
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
(During EEPROM programming)
HS osc configuration (PIC16C84-10)
FOSC = 10 MHz, VDD = 5.5V
VDD = 4.0V, WDT enabled, industrial
VDD = 4.0V, WDT disabled, commercial
VDD = 4.0V, WDT disabled, industrial
—
5.0
10
mA
D013
D020
IPD
Power-down Current(3)
—
40 100 A
D021
—
38 100 A
D021A
—
38 100 A
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1996-2013 Microchip Technology Inc.
DS30445D-page 73
PIC16C84
11.2
DC CHARACTERISTICS PIC16LC84-04 (Commercial, Industrial)
DC Characteristics
Power Supply Pins
Parameter
No.
Sym
D001
D002
VDD
VDR
Characteristic
2.0
1.5 *
—
—
6.0
—
V
V
XT, RC, and LP osc configuration
Device in SLEEP mode
—
VSS
—
V
See section on Power-on Reset for details
0.05*
—
—
D010
D010A
—
—
1
7.3
4
10
mA
mA
D014
—
60
400
A
D003
D004
Supply Voltage
RAM Data Retention
Voltage(1)
VPOR VDD start voltage to
ensure internal Poweron Reset signal
SVDD VDD rise rate to ensure
internal Power-on
Reset signal
Supply Current(2)
IDD
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0C TA +70C (commercial)
-40C TA +85C (industrial)
Min Typ† Max Units
Conditions
V/ms See section on Power-on Reset for details
RC and XT osc configuration(4)
FOSC = 2 MHz, VDD = 5.5V
FOSC = 2 MHz, VDD = 5.5V
(During EEPROM programming)
LP osc configuration
FOSC = 32 kHz, VDD = 2.0V,
WDT disabled
VDD = 2.0V, WDT enabled, industrial
VDD = 2.0V, WDT disabled, commercial
VDD = 2.0V, WDT disabled, industrial
D020
IPD
Power-down Current(3)
—
26 100
A
D021
—
26 100
A
D021A
—
26 100
A
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30445D-page 74
1996-2013 Microchip Technology Inc.
PIC16C84
11.3
DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial)
PIC16C84-10 (Commercial, Industrial)
PIC16LC84-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
Operating voltage VDD range as described in DC spec Section 111 and Section 11.2.
DC Characteristics
All Pins Except
Power Supply Pins
Parameter
Sym
No.
VIL
D030
D030A
D031
D032
D033
D040
D040A
D041
D042
D043
D070
D060
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
Min
VSS
VSS
VSS
Vss
with Schmitt Trigger buffer
MCLR, RA4/T0CKI, OSC1
(RC mode)
Vss
OSC1 (XT, HS and LP modes)(1)
Input High Voltage
VIH
I/O ports
with TTL buffer
0.36VDD
0.48VDD
with Schmitt Trigger buffer
0.45VDD
MCLR, RA4/T0CKI, OSC1
0.85VDD
(RC mode)
OSC1 (XT, HS and LP modes)(1) 0.7VDD
IPURB PORTB weak pull-up current
50*
IIL
D061
D063
Typ†
Max
Units
Conditions
4.5 VDD 5.5V
entire range(4)
entire range
—
0.8
— 0.16VDD
— 0.2VDD
— 0.2VDD
V
V
V
V
—
0.3VDD
V
—
VDD
V
—
—
VDD
VDD
V
—
250*
VDD
400*
V
A VDD = 5V, VPIN = VSS
Input Leakage Current(2,3)
I/O ports
—
—
1
MCLR, RA4/T0CKI
OSC1/CLKIN
—
—
—
—
5
5
4.5 VDD 5.5V
entire range(4)
entire range
A Vss VPIN VDD,
Pin at hi-impedance
A Vss VPIN VDD
A Vss VPIN VDD, XT, HS and LP
osc configuration
Output Low Voltage
I/O ports
—
—
0.6
V IOL = 8.5 mA, VDD = 4.5V
OSC2/CLKOUT
—
—
0.6
V IOL = 1.6 mA, VDD = 4.5V
(RC osc configuration)
Output High Voltage
D090
VOH I/O ports(3)
VDD - 0.7 —
—
V IOH = -3.0 mA, VDD = 4.5V
D093
OSC2/CLKOUT
VDD - 0.7 —
—
V IOH = -1.3 mA, VDD = 4.5V
(RC osc configuration)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C84 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: The user may use better of the two specs.
D080
D083
VOL
1996-2013 Microchip Technology Inc.
DS30445D-page 75
PIC16C84
11.4
DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial)
PIC16C84-10 (Commercial, Industrial)
PIC16LC84-04 (Commercial, Industrial)
DC Characteristics
All Pins Except
Power Supply Pins
Parameter
No.
Sym
D100
COSC2
D101
CIO
D120
D121
ED
VDRW
D122
TDEW
D130
D131
EP
VPR
Characteristic
Capacitive Loading Specs
on Output Pins
OSC2/CLKOUT pin
All I/O pins and OSC2
(RC mode)
Data EEPROM Memory
Endurance
VDD for read/write
Erase/Write cycle time(1)
Program EEPROM Memory
Endurance
VDD for read
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
Operating voltage VDD range as described in DC spec Section 11-1
and Section 11.2.
Min
Typ†
Max Units
Conditions
—
—
15
pF
—
—
50
pF
1M
VMIN
10M
—
6.0
—
10
20*
100
VMIN
1000
—
—
6.0
—
In XT, HS and LP modes when
external clock is used to drive
OSC1.
E/W 25C at 5V
V VMIN = Minimum operating
voltage
ms
E/W
V VMIN = Minimum operating
voltage
V
ms
D132
VPEW VDD for erase/write
4.5
—
5.5
D133
TPEW Erase/Write cycle time(1)
—
10
—
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The user should use interrupts or poll the EEIF or WR bits to ensure the write cycle has completed.
DS30445D-page 76
1996-2013 Microchip Technology Inc.
PIC16C84
TABLE 11-2
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
2
to
ck
CLKOUT
cy
cycle time
io
I/O port
inp
INT pin
mc
MCLR
Uppercase symbols and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
T
Time
os,osc
ost
pwrt
rbt
t0
wdt
OSC1
oscillator start-up timer
power-up timer
RBx pins
T0CKI
watchdog timer
P
R
V
Z
Period
Rise
Valid
Hi-impedance
FIGURE 11-1: PARAMETER MEASUREMENT INFORMATION
0.7 VDD XTAL
0.8 VDD RC (High)
2.0 VDD (High)
0.3 VDD XTAL
0.15 VDD RC (Low)
OSC1 Measurement Points
0.2 VDD (Low)
I/O Port Measurement Points
All timings are measured between high and low measurement points as indicated in the figure.
FIGURE 11-2: LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL =
464
CL =
50 pF
for all pins except OSC2.
15 pF
for OSC2 output.
1996-2013 Microchip Technology Inc.
DS30445D-page 77
PIC16C84
11.5
Timing Diagrams and Specifications
FIGURE 11-3: EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 11-3
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
FOSC
External CLKIN Frequency(1)
DC
—
2
MHz
XT, RC osc
PIC16LC84-04
DC
—
4
MHz
XT, RC osc
PIC16C84-04
Tosc
TCY
3
TosL,
TosH
4
TosR,
TosF
Units Conditions
—
10
MHz
HS osc
PIC16C84-10
DC
—
200
kHz
LP osc
PIC16LC84-04
DC
—
2
MHz
RC osc
PIC16LC84-04
DC
—
4
MHz
RC osc
PIC16C84-04
0.1
—
2
MHz
XT osc
PIC16LC84-04
0.1
—
4
MHz
XT osc
PIC16C84-04
1
—
10
MHz
HS osc
PIC16C84-10
DC
—
200
kHz
LP osc
PIC16LC84-04
500
—
—
ns
XT, RC osc
PIC16LC84-04
250
—
—
ns
XT, RC osc
PIC16C84-04
100
—
—
ns
HS osc
PIC16C84-10
5
—
—
s
LP osc
PIC16LC84-04
500
250
—
—
—
—
ns
ns
RC osc
RC osc
PIC16LC84-04
PIC16C84-04
500
—
10,000
ns
XT osc
PIC16LC84-04
250
—
10,000
ns
XT osc
PIC16C84-04
100
—
1,000
ns
HS osc
PIC16C84-10
5
—
—
s
LP osc
PIC16LC84-04
Instruction Cycle Time(1)
0.4
4/Fosc
DC
s
Clock in (OSC1) High or Low
Time
60 *
—
—
ns
XT osc
PIC16LC84-04
50 *
—
—
ns
XT osc
PIC16C84-04
2*
—
—
s
LP osc
PIC16LC84-04
35 *
—
—
ns
HS osc
PIC16C84-10
PIC16C84-04
External CLKIN Period(1)
Oscillator Period
2
Max
DC
Oscillator Frequency(1)
1
Typ†
(1)
Clock in (OSC1) Rise or Fall Time
25 *
—
—
ns
XT osc
50 *
—
—
ns
LP osc
PIC16LC84-04
15 *
—
—
ns
HS osc
PIC16C84-10
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30445D-page 78
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 11-4: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
12
13
14
19
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT.
TABLE 11-4
Parameter
No.
10
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
TosH2ckL
OSC1 to CLKOUT
TosH2ckH
OSC1 to CLKOUT
10A
11
11A
12
TckR
CLKOUT rise time
12A
13
TckF
CLKOUT fall time
13A
PIC16C84
Min
Typ†
Max
—
15
30 *
Units Conditions
ns
Note 1
PIC16LC84
—
15
120 *
ns
Note 1
PIC16C84
—
15
30 *
ns
Note 1
PIC16LC84
—
15
120 *
ns
Note 1
PIC16C84
—
15
30 *
ns
Note 1
PIC16LC84
—
15
100 *
ns
Note 1
PIC16C84
—
15
30 *
ns
Note 1
PIC16LC84
—
15
100 *
ns
Note 1
Note 1
14
TckL2ioV
CLKOUT to Port out valid
—
—
0.5TCY +20 *
ns
15
TioV2ckH
Port in valid before
PIC16C84
0.30TCY + 30 *
—
—
ns
Note 1
CLKOUT
PIC16LC84
0.30TCY + 80 *
—
—
ns
Note 1
0*
—
—
ns
Note 1
16
TckH2ioI
17
TosH2ioV
Port in hold after CLKOUT
OSC1 (Q1 cycle) to
PIC16C84
—
—
125 *
ns
Port out valid
PIC16LC84
—
—
250 *
ns
18
TosH2ioI
OSC1 (Q2 cycle) to Port input invalid
(I/O in hold time)
TBD
—
—
ns
19
TioV2osH
Port input valid to OSC1
(I/O in setup time)
TBD
—
—
ns
20
TioR
Port output rise time
20A
21
TioF
Port output fall time
21A
22
Tinp
22A
23
23A
Trbp
PIC16C84
—
10
25 *
ns
PIC16LC84
—
10
60 *
ns
PIC16C84
—
10
25 *
ns
PIC16LC84
—
10
60 *
ns
INT pin high
PIC16C84
20 *
—
—
ns
or low time
PIC16LC84
55 *
—
—
ns
RB7:RB4 change INT
PIC16C84
20 *
—
—
ns
high or low time
PIC16LC84
55 *
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
1996-2013 Microchip Technology Inc.
DS30445D-page 79
PIC16C84
FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
TABLE 11-5
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
30
TmcL
MCLR Pulse Width (low)
31
Twdt
32
Tost
33
Tpwrt
34
TIOZ
*
†
Min
Typ†
Max
Units
350 *
150 *
—
—
—
—
ns
ns
2.0V VDD 3.0V
3.0V VDD 6.0V
Watchdog Timer Time-out Period
(No Prescaler)
7*
18
33 *
ms
VDD = 5V
Oscillation Start-up Timer Period
—
1024TOSC
—
ms
TOSC = OSC1 period
28 *
72
132 *
ms
VDD = 5.0V
—
—
100 *
ns
Power-up Timer Period
I/O Hi-impedance from MCLR Low
or reset
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30445D-page 80
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 11-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 11-6
Parameter
No.
40
TIMER0 CLOCK REQUIREMENTS
Sym Characteristic
Tt0H T0CKI High Pulse Width
Min
No Prescaler
With Prescaler
41
Tt0L T0CKI Low Pulse Width
No Prescaler
With Prescaler
42
*
†
Tt0P T0CKI Period
Typ† Max Units Conditions
0.5TCY + 20 *
—
—
ns
50 *
30 *
—
—
—
—
ns
ns
2.0V VDD 3.0V
3.0V VDD 6.0V
0.5TCY + 20 *
—
—
ns
50 *
20 *
—
—
—
—
ns
ns
2.0V VDD 3.0V
3.0V VDD 6.0V
TCY + 40 *
N
—
—
ns
N = prescale value
(2, 4, ..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1996-2013 Microchip Technology Inc.
DS30445D-page 81
PIC16C84
NOTES:
DS30445D-page 82
1996-2013 Microchip Technology Inc.
PIC16C84
12.0
DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16C84
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. 'Typical' represents the mean of the distribution at 25C, while 'max' or 'min' represents
(mean + 3) and (mean - 3) respectively, where is standard deviation.
FIGURE 12-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
FOSC (25C)
Frequency Normalized To +25C
1.10
Rext 10 k
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(C)
TABLE 12-1
RC OSCILLATOR FREQUENCIES *
Cext
Rext
20 pF
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
100k
100 pF
300 pF
Average
Fosc @ 5V, 25C
4.68 MHz
3.94 MHz
2.34 MHz
250.16 kHz
1.49 MHz
1.12 MHz
620.31 kHz
90.25 kHz
524.24 kHz
415.52 kHz
270.33 kHz
25.37 kHz
27%
25%
29%
33%
25%
25%
30%
26%
28%
30%
26%
25%
*Measured in PDIP Packages.The percentage variation indicated here is part to part variation due to normal process
distribution. The variation indicated is 3 standard deviation from average value.
1996-2013 Microchip Technology Inc.
DS30445D-page 83
PIC16C84
FIGURE 12-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD (Cext = 20 pF)
5.5
5.0
Rext = 3.3k
4.5
4.0
Rext = 5k
FOSC (MHz)
3.5
3.0
T = 25C
2.5
2.0
Rext = 10k
1.5
1.0
Rext = 100k
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30445D-page 84
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 12-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD (Cext = 100 pF)
2.2
2.0
1.8
Rext = 3.3k
1.6
FOSC (MHz)
1.4
Rext = 5k
1.2
1.0
0.8
Rext = 10k
0.6
T = 25C
0.4
Rext = 100k
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD (Cext = 300 pF)
1.1
1.0
0.9
0.8
T = 25C
FOSC (MHz)
0.7
Rext = 3.3k
0.6
0.5
Rext = 5k
0.4
0.3
Rext = 10k
0.2
0.1
Rext = 100k
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1996-2013 Microchip Technology Inc.
DS30445D-page 85
PIC16C84
FIGURE 12-5: TYPICAL IPD vs. VDD WATCHDOG DISABLED (25°C)
60
50
IPD (A)
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-6: TYPICAL IPD vs. VDD WATCHDOG ENABLED (25°C)
60
50
IPD(A)
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
DS30445D-page 86
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 12-7: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
120
100
Te
Max.
IPD(A)
80
85C
mp. =
= 25C
emp.
Typ. T
60
C
= -40
emp.
Min. T
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-8: MAXIMUM IPD vs. VDD WATCHDOG ENABLED*
120
100
Te
Max.
IPD(A)
80
85C
mp. =
= 25C
emp.
Typ. T
60
0C
p. = -4
m
e
T
.
Min
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
* IPD, with Watchdog Timer enabled, has two components: The leakage current which increases with higher temperature
and the operating current of the Watchdog Timer logic which increases with lower temperature. At -40C, the latter
dominates explaining the apparently anomalous behavior.
1996-2013 Microchip Technology Inc.
DS30445D-page 87
PIC16C84
FIGURE 12-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.0
1.8
Max (-40C to +85C)
VTH(Volts)
1.6
Typ @ 25C
1.4
1.2
Min (-40C to +85C)
1.0
0.8
0.6
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-10: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
vs. VDD
3.4
3.2
3.0
VTH (Volts)
2.8
2.6
(-4
x
Ma
2.4
0
85
o+
Ct
2.2
(Min
2.0
C)
(2
Typ
40
)
5C
85
o+
Ct
C)
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30445D-page 88
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 12-11: VIH, VIL OF MCLR, T0CKI and OSC1 (IN RC MODE) vs. VDD
5.0
VIH, max (-40C to +85C)
4.5
VIH, typ (25C)
4.0
VIH, min (-40C to +85C)
VIH, VIL(volts)
3.5
3.0
VIL, max (-40C to +85C)
2.5
VIL, typ (25C)
VIL, min (-40C to +85C)
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1996-2013 Microchip Technology Inc.
DS30445D-page 89
PIC16C84
FIGURE 12-12: TYPICAL IDD vs. FREQ (EXT CLOCK, 25°C)
10,000
IDD (A)
1,000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10k
100k
1M
10M
100M
10M
100M
External Clock Frequency (Hz)
FIGURE 12-13: MAXIMUM IDD vs. FREQ (EXT CLOCK, -40° TO +85°C)
10,000
IDD (A)
1,000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
10
10k
100k
1M
External Clock Frequency (Hz)
DS30445D-page 90
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 12-14: WDT TIME-OUT PERIOD vs. VDD
70
60
WDT Time-out Period (ms)
Max. 85C
50
Max. 70C
40
Typ. 25C
30
Min. 0C
20
Min. -40C
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-15: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD
10000
9000
8000
7000
gm(A/V)
6000
5000
Max @ -40C
4000
Typ @ 25C
3000
Min @ 85C
2000
1000
0
2.0
3.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
1996-2013 Microchip Technology Inc.
DS30445D-page 91
PIC16C84
FIGURE 12-16: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD
250
225
200
175
Typ @ 25C
Max @ -40C
gm(A/V)
150
125
Min @ 85C
100
75
50
25
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
FIGURE 12-17: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
2000
1800
1600
Max @ -40C
1400
Typ @ 25C
gm(A/V)
1200
1000
Min @ 85C
800
600
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS30445D-page 92
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 12-18: IOH vs. VOH, VDD = 3V
0
-2
IOH (mA)
-4
-6
Min @ 85C
-8
-10
-12
Typ @ 25C
-14
Max @ -40C
-16
-18
0.0
0.5
1.0
1.5
2.0
3.0
2.5
VOH (Volts)
FIGURE 12-19: IOH vs. VOH, VDD = 5V
0
-5
-10
Min @ 85C
-15
IOH (mA)
-20
Max @ -40C
-25
Typ @ 25C
-30
-35
-40
-45
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOH (Volts)
1996-2013 Microchip Technology Inc.
DS30445D-page 93
PIC16C84
FIGURE 12-20: IOL vs. VOL, VDD = 3V
35
Max. -40C
30
Typ. 25C
IOL (mA)
25
20
Min. +85C
15
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
FIGURE 12-21: IOL vs. VOL, VDD = 5V
90
80
Max @ -40C
IOL (mA)
70
60
Typ @ 25C
50
40
Min @ +85C
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
DS30445D-page 94
1996-2013 Microchip Technology Inc.
PIC16C84
FIGURE 12-22: MAXIMUM DATA MEMORY ERASE/WRITE CYCLE TIME VS. VDD
20
18
DMEM Max. E/W Cycle Time (ms)
16
14
12
10
8
6
4
2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
Shaded areas are beyond recommended range.
TABLE 12-2
INPUT CAPACITANCE*
Typical Capacitance (pF)
Pin Name
18L PDIP
18L SOIC
PORTA
5.0
4.3
PORTB
5.0
4.3
MCLR
17.0
17.0
OSC1/CLKIN
4.0
3.5
OSC2/CLKOUT
4.3
3.5
T0CKI
3.2
2.8
* All capacitance values are typical at 25C. A part to part variation of 25% (three standard deviations) should
be taken into account.
1996-2013 Microchip Technology Inc.
DS30445D-page 95
PIC16C84
NOTES:
DS30445D-page 96
1996-2013 Microchip Technology Inc.
PIC16C84
13.0
PACKAGING INFORMATION
13.1
K04-007 18-Lead Plastic Dual In-line (P) – 300 mil
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
D
2
n
1
E1
A1
A
R
L
c
A2
B1
p
B
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
n
p
B
B1†
R
c
A
A1
A2
L
D‡
E‡
E1
eB
0.013
0.055
0.000
0.005
0.110
0.075
0.000
0.125
0.890
0.245
0.230
0.310
5
5
INCHES*
NOM
0.300
18
0.100
0.018
0.060
0.005
0.010
0.155
0.095
0.020
0.130
0.895
0.255
0.250
0.349
10
10
MAX
0.023
0.065
0.010
0.015
0.155
0.115
0.020
0.135
0.900
0.265
0.270
0.387
15
15
MILLIMETERS
NOM
MAX
7.62
18
2.54
0.33
0.46
0.58
1.40
1.52
1.65
0.00
0.13
0.25
0.13
0.25
0.38
2.79
3.94
3.94
1.91
2.41
2.92
0.00
0.51
0.51
3.18
3.30
3.43
22.61
22.73
22.86
6.22
6.48
6.73
5.84
6.35
6.86
7.87
8.85
9.83
5
10
15
5
10
15
MIN
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed
0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall
not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1996-2013 Microchip Technology Inc.
DS30445D-page 97
PIC16C84
13.2
K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
p
E
D
2
B
1
n
X
45 °
L
R2
c
A
R1
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
A2
INCHES*
NOM
0.050
18
0.099
0.093
0.058
0.048
0.008
0.004
0.456
0.450
0.296
0.292
0.407
0.394
0.020
0.010
0.005
0.005
0.005
0.005
0.016
0.011
0
4
0.015
0.010
0.011
0.009
0.017
0.014
0
12
0
12
MIN
p
n
A
A1
A2
D‡
E‡
E1
X
R1
R2
L
L1
c
B†
A1
MAX
0.104
0.068
0.011
0.462
0.299
0.419
0.029
0.010
0.010
0.021
8
0.020
0.012
0.019
15
15
MILLIMETERS
NOM
MAX
1.27
18
2.50
2.36
2.64
1.47
1.22
1.73
0.19
0.10
0.28
11.58
11.43
11.73
7.51
7.42
7.59
10.33
10.01
10.64
0.50
0.25
0.74
0.13
0.13
0.25
0.13
0.13
0.25
0.41
0.28
0.53
0
4
8
0.38
0.25
0.51
0.27
0.23
0.30
0.42
0.36
0.48
0
12
15
0
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30445D-page 98
1996-2013 Microchip Technology Inc.
PIC16C84
APPENDIX A: FEATURE
IMPROVEMENTS FROM PIC16C5X TO
PIC16C84
The following is the list of feature improvements over
the PIC16C5X microcontroller family:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
the register file (128 bytes now versus 32 bytes
before).
A PC latch register (PCLATH) is added to handle
program memory paging. PA2, PA1 and PA0 bits
are removed from the status register and placed
in the option register.
Data memory paging is redefined slightly. The
STATUS register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW. Two
instructions, TRIS and OPTION, are being
phased out although they are kept for
compatibility with PIC16C5X.
OPTION and TRIS registers are made
addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
Reset vector is changed to 0000h.
Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized.
Registers are reset differently.
Wake up from SLEEP through interrupt is
added.
Two separate timers, the Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt on
change features.
T0CKI pin is also a port pin (RA4/T0CKI).
FSR is a full 8-bit register.
"In system programming" is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
1996-2013 Microchip Technology Inc.
APPENDIX B: CODE COMPATIBILITY
- FROM PIC16C5X TO
PIC16C84
To convert code written for PIC16C5X to PIC16C84,
the user should take the following steps:
1.
2.
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables for reallocation.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to 0000h.
DS30445D-page 99
PIC16C84
APPENDIX C: WHAT’S NEW IN THIS
DATA SHEET
APPENDIX D: WHAT’S CHANGED IN
THIS DATA SHEET
No new information has been added to this data sheet.
Here’s what’s changed in this data sheet:
For information on upgrade devices from the
PIC16C84, please refer to the PIC16F8X data sheet.
1.
2.
Some sections have been rearranged for clarity
and consistency.
Errata information has been included.
Revision D (January 2013)
Added a note to each package drawing.
DS30445D-page 100
1996-2013 Microchip Technology Inc.
PIC16C84
APPENDIX E: CONVERSION CONSIDERATIONS - PIC16C84 TO PIC16F83/F84 AND
PIC16CR83/CR84
Considerations for converting from the PIC16C84 to
the PIC16F84 are listed in the table below. These considerations apply to converting from the PIC16C84 to
the PIC16F83 (same as PIC16F84 except for program
Difference
and data RAM memory sizes) and the PIC16CR84 and
PIC16CR83 (ROM versions of Flash devices). Development Systems support is available for all of the
PIC16X8X devices.
PIC16C84
PIC16F84
The polarity of the PWRTE bit has
been reversed. Ensure that the programmer has this bit correctly set
before programming.
PWRTE
PWRTE
The PIC16F84 (and PIC16CR84)
have larger RAM sizes. Ensure that
this does not cause an issue with
your program.
RAM = 36 bytes
RAM = 68 bytes
The MCLR pin now has an on-chip
filter. The input signal on the MCLR
pin will require a longer low pulse to
generate an interrupt.
MCLR pulse width (low)
= 350ns; 2.0V VDD 3.0V
= 150ns; 3.0V VDD 6.0V
MCLR pulse width (low)
= 1000ns; 2.0V VDD 6.0V
Some electrical specifications have
been improved (see IPD example).
Compare the electrical specifications of the two devices to ensure
that this will not cause a compatibility issue.
IPD (typ @ 2V) = 26A
IPD (typ @ 2V) < 1A
IPD (max @ 4V, WDT disabled)
=100A (PIC16C84)
=100A (PIC16LC84)
IPD (max @ 4V, WDT disabled)
=14A (PIC16F84)
=7A (PIC16LF84)
PORTA and crystal oscillator values
less than 500kHz
For crystal oscillator configurations
operating below 500kHz, the device
may generate a spurious internal Qclock when PORTA<0> switches
state.
N/A
RB0/INT pin
TTL
TTL/ST*
(* This buffer is a Schmitt Trigger
input when configured as the external interrupt.)
EEADR<7:6> and IDD
It is recommended that the
EEADR<7:6> bits be cleared.
When either of these bits is set, the
maximum IDD for the device is
higher than when both are cleared.
N/A
Code Protect
1 CP bit
9 CP bits
Recommended value of REXT for
RC oscillator circuits
REXT = 3k - 100k
REXT = 5k - 100k
GIE bit unintentional enable
If an interrupt occurs while the
Global Interrupt Enable (GIE) bit is
being cleared, the GIE bit may unintentionally be re-enabled by the
user’s Interrupt Service Routine (the
RETFIE instruction).
N/A
1996-2013 Microchip Technology Inc.
DS30445D-page 101
PIC16C84
NOTES:
DS30445D-page 102
1996-2013 Microchip Technology Inc.
PIC16C84
INDEX
DC Characteristics ........................................... 73, 74, 75, 76
Development Support ........................................................ 67
Development Tools ............................................................ 67
Digit Carry ............................................................................ 7
CLRWDT ................................................................... 56
COMF ........................................................................ 57
DECF ......................................................................... 57
DECFSZ .................................................................... 57
GOTO ........................................................................ 58
INCF .......................................................................... 58
INCFSZ ...................................................................... 59
IORLW ....................................................................... 59
IORWF ....................................................................... 60
MOVF ........................................................................ 60
MOVLW ..................................................................... 60
MOVWF ..................................................................... 60
NOP ........................................................................... 61
OPTION ..................................................................... 61
RETFIE ...................................................................... 61
RETLW ...................................................................... 62
RETURN .................................................................... 62
RLF ............................................................................ 63
RRF ........................................................................... 63
SLEEP ....................................................................... 64
SUBLW ...................................................................... 64
SUBWF ...................................................................... 65
SWAPF ...................................................................... 65
TRIS .......................................................................... 65
XORLW ..................................................................... 66
XORWF ..................................................................... 66
Section ....................................................................... 51
Summary Table ......................................................... 52
INT Interrupt ...................................................................... 46
INTCON ........................................................... 16, 39, 44, 46
INTEDG ............................................................................. 46
Interrupts
Flag ............................................................................ 44
Interrupt on Change Feature ..................................... 21
Interrupts ............................................................. 35, 44
E
K
External Power-on Reset Circuit ........................................ 40
KeeLoq Evaluation and Programming Tools .................. 69
F
L
Family of Devices
PIC16C8X .................................................................... 4
FSR .............................................................................. 18, 39
Fuzzy Logic Dev. System (fuzzyTECH-MP) ................... 69
Loading of PC .................................................................... 17
A
Absolute Maximum Ratings ............................................... 71
ALU ...................................................................................... 7
Architectural Overview ......................................................... 7
Assembler
MPASM Assembler .................................................... 68
B
Block Diagram
Interrupt Logic ............................................................ 45
On-Chip Reset Circuit ................................................ 38
RA3:RA0 and RA5 Port Pins ..................................... 19
RA4 Pin ...................................................................... 19
RB3:RB0 Port Pins .................................................... 21
RB7:RB4 Port Pins .................................................... 21
TMR0/WDT Prescaler ................................................ 28
Watchdog Timer ......................................................... 47
Brown-out Protection Circuit .............................................. 43
C
Carry .................................................................................... 7
CLKIN .................................................................................. 9
CLKOUT .............................................................................. 9
Code Protection ........................................................... 35, 49
Compatibility, upward ........................................................... 3
Computed GOTO ............................................................... 17
Configuration Bits ............................................................... 35
D
G
GIE ..................................................................................... 44
I
I/O Ports ............................................................................. 19
I/O Programming Considerations ....................................... 23
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 67
In-Circuit Serial Programming ...................................... 35, 49
INDF ................................................................................... 39
Instruction Format .............................................................. 51
Instruction Set
ADDLW ...................................................................... 53
ADDWF ...................................................................... 53
ANDLW ...................................................................... 53
ANDWF ...................................................................... 53
BCF ............................................................................ 54
BSF ............................................................................ 54
BTFSC ....................................................................... 54
BTFSS ....................................................................... 55
CALL .......................................................................... 55
CLRF .......................................................................... 56
CLRW ........................................................................ 56
1996-2013 Microchip Technology Inc.
M
MCLR ...................................................................... 9, 38, 39
Memory Organization
Data Memory ............................................................. 12
Memory Organization ................................................ 11
Program Memory ....................................................... 11
MP-DriveWay™ - Application Code Generator ................. 69
MPLAB C ........................................................................... 69
MPLAB Integrated Development Environment Software ... 68
O
OPCODE ........................................................................... 51
OPTION_REG ....................................................... 15, 39, 46
OSC selection .................................................................... 35
OSC1 ................................................................................... 9
OSC2 ................................................................................... 9
Oscillator
HS ........................................................................ 36, 43
LP ........................................................................ 36, 43
RC ....................................................................... 36, 37
XT ........................................................................ 36, 43
Oscillator Configurations .................................................... 36
P
Paging, Program Memory .................................................. 17
DS30445D-page 103
PIC16C84
PCL .............................................................................. 17, 39
PCLATH ....................................................................... 17, 39
PD .......................................................................... 14, 38, 43
PICDEM-1 Low-Cost PIC MCU Demo Board .................... 68
PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 68
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 68
PICMASTER In-Circuit Emulator ..................................... 67
PICSTART Plus Entry Level Development System ........ 67
Pinout Descriptions .............................................................. 9
POR ................................................................................... 40
Oscillator Start-up Timer (OST) ........................... 35, 40
Power-on Reset (POR) .................................. 35, 39, 40
Power-up Timer (PWRT) ..................................... 35, 40
Time-out Sequence .................................................... 43
Time-out Sequence on Power-up .............................. 41
TO .................................................................. 14, 38, 43
Port RB Interrupt ................................................................ 46
PORTA ..................................................................... 9, 19, 39
PORTB ..................................................................... 9, 21, 39
Power-down Mode (SLEEP) .............................................. 48
Prescaler ............................................................................ 27
PRO MATE II Universal Programmer .............................. 67
Product Identification System ........................................... 107
Z
Zero bit ................................................................................. 7
R
RBIF bit ........................................................................ 21, 46
RC Oscillator ...................................................................... 43
Read-Modify-Write ............................................................. 23
Register File ....................................................................... 12
Reset ............................................................................ 35, 38
Reset on Brown-Out ........................................................... 43
S
Saving W Register and STATUS in RAM .......................... 46
SEEVAL Evaluation and Programming System .............. 69
SLEEP .................................................................... 35, 38, 48
Software Simulator (MPLAB-SIM) ...................................... 69
Special Features of the CPU .............................................. 35
Special Function Registers ................................................ 12
Stack .................................................................................. 17
Overflows ................................................................... 17
Underflows ................................................................. 17
STATUS ................................................................... 7, 14, 39
T
time-out .............................................................................. 39
Timer0
Switching Prescaler Assignment ................................ 29
T0IF ............................................................................ 46
Timer0 Module ........................................................... 25
TMR0 Interrupt ........................................................... 46
TMR0 with External Clock .......................................... 27
Timing Diagrams
Time-out Sequence .................................................... 41
Timing Diagrams and Specifications .................................. 78
TRISA ................................................................................. 19
TRISB ........................................................................... 21, 39
W
W ........................................................................................ 39
Wake-up from SLEEP .................................................. 39, 48
Watchdog Timer (WDT) ................................... 35, 38, 39, 47
WDT ................................................................................... 39
Period ......................................................................... 47
Programming Considerations .................................... 47
Time-out ..................................................................... 39
DS30445D-page 104
1996-2013 Microchip Technology Inc.
PIC16C84
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel
for you to use in extending your technical staff with
microcontroller and memory experts.
To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
the latest component data and software tool updates,
provides technical help and embedded systems
insights, and discusses how Microchip products provide project solutions.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers. To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp.mchip.com/biz/mchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allow multiple users various baud rates
depending on the local point of access.
The following connect procedure applies in most locations.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
will appear.
5. Type MCHIPBBS, depress the <Enter> key and you
will be connected to the Microchip BBS.
In the United States, to find the CompuServe phone
number closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with “Host Name:”, type NETWORK, depress
the <Enter> key and follow CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
number.
Microchip regularly uses the Microchip BBS to distribute
technical information, application notes, source code,
errata sheets, bug reports, and interim patches for
Microchip systems software products. For each SIG, a
moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files
are accepted from the user community in general to
limit the spread of computer viruses.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either
the Internet or the CompuServe communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the
address:
mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense.
The Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
1996-2013 Microchip Technology Inc.
DS30445D-page 11-105
PIC16C84
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can
better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16C84
Y
N
Literature Number: DS30445D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30445D-page 11-106
1996-2013 Microchip Technology Inc.
PIC16C84
PIC16C84 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
-XX
Frequency Temperature
Range
Range
/XX
XXX
Package
Pattern
Device
PIC16C84(2), PIC16C84T(3)
PIC16LC84(2), PIC16LC84T(3)
Frequency
Range
04
10
= 4 MHz
= 10 MHz
Temperature
Range
b(1)
I
= 0C to
= -40C to
Package
P
SO
= PDIP
= SOIC (Gull Wing, 300 mil body)
Pattern
3-digit Pattern Code for QTP, ROM (blank otherwise)
+70C
+85C
(Commercial)
(Industrial)
Examples:
a)
PIC16C84 -04/P 301 = Commercial
temp., PDIP package, 4MHz, normal VDD
limitis, QTP pattern #301.
b)
PIC16LC84 - 04I/SO = Industrial temp.,
SOIC package, 200kHz, Extended VDD
limits.
Note 1: b = blank
2: C
= Standard VDD range
LC = Extended VDD range
3: T = in tape and reel - SOIC, SSOP
packages only.
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see last page)
2. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
1996-2013 Microchip Technology Inc.
DS30445D-page 107
PIC16C84
DS30445D-page 108
1996-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1996-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769256
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
1996-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS30445D-page 109
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS30445D-page 110
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
1996-2013 Microchip Technology Inc.