PEMD2; PIMD2; PUMD2 NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ Rev. 07 — 24 September 2008 Product data sheet 1. Product profile 1.1 General description NPN/PNP Resistor-Equipped Transistors (RET). Table 1. Product overview Type number Package NXP JEITA PNP/PNP complement NPN/NPN complement PEMD2 SOT666 - PEMB1 PEMH1 PIMD2 SOT457 SC-74 - - PUMD2 SOT363 SC-88 PUMB1 PUMH1 1.2 Features n n n n Built-in bias resistors Simplifies circuit design Reduces component count Reduces pick and place costs 1.3 Applications n Low current peripheral driver n Control of IC inputs n Replaces general-purpose transistors in digital applications 1.4 Quick reference data Table 2. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - 50 V IO output current - - 100 mA R1 bias resistor 1 (input) 15.4 22 28.6 kΩ R2/R1 bias resistor ratio 0.8 1 1.2 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 2. Pinning information Table 3. Pinning Pin Description Simplified outline Graphic symbol PEMD2; PUMD2 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1 6 5 4 6 5 4 R1 R2 TR2 1 2 3 TR1 001aab555 R2 R1 1 2 3 006aaa143 PIMD2 1 GND (emitter) TR2 2 input (base) TR2 3 output (collector) TR1 4 GND (emitter) TR1 5 input (base) TR1 6 output (collector) TR2 6 5 4 6 5 4 R1 1 2 R2 3 TR1 TR2 R2 1 R1 2 3 006aab235 3. Ordering information Table 4. Ordering information Type number Package Name Description Version PEMD2 - plastic surface-mounted package; 6 leads SOT666 PIMD2 SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 PUMD2 SC-88 plastic surface-mounted package; 6 leads SOT363 PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 2 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 4. Marking Table 5. Marking codes Type number Marking code[1] PEMD2 D4 PIMD2 M5 PUMD2 D*2 [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor with negative polarity VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage TR1 positive - +40 V negative - −10 V input voltage TR2 positive - +10 V negative - −40 V IO output current - 100 mA ICM peak collector current single pulse; tp ≤ 1 ms - 100 mA Ptot total power dissipation Tamb ≤ 25 °C - 200 mW - 300 mW PEMD2 (SOT666) PIMD2 (SOT457) [2] PUMD2 (SOT363) - 200 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C PEMD2_PIMD2_PUMD2_7 Product data sheet [1] © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 3 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ Table 6. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions total power dissipation Tamb ≤ 25 °C Min Max Unit Per device Ptot [1] [2] PEMD2 (SOT666) - 300 mW PIMD2 (SOT457) - 600 mW PUMD2 (SOT363) - 300 mW [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. 6. Thermal characteristics Table 7. Symbol Thermal characteristics Parameter Conditions Min Typ Max Unit - - 625 K/W PIMD2 (SOT457) - - 417 K/W PUMD2 (SOT363) - - 625 K/W Per transistor Rth(j-a) thermal resistance from junction to ambient in free air [1] [2] PEMD2 (SOT666) Per device Rth(j-a) thermal resistance from junction to ambient in free air PEMD2 (SOT666) [2] - - 416 K/W PIMD2 (SOT457) - - 208 K/W PUMD2 (SOT363) - - 416 K/W [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. PEMD2_PIMD2_PUMD2_7 Product data sheet [1] © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 4 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 7. Characteristics Table 8. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per transistor; for the PNP transistor with negative polarity ICBO collector-base cut-off VCB = 50 V; IE = 0 A current - - 100 nA ICEO collector-emitter cut-off current VCE = 30 V; IB = 0 A - - 1 µA VCE = 30 V; IB = 0 A; Tj = 150 °C - - 50 µA µA IEBO emitter-base cut-off current VEB = 5 V; IC = 0 A - - 180 hFE DC current gain VCE = 5 V; IC = 5 mA 60 - - VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - - 150 mV VI(off) off-state input voltage VCE = 5 V; IC = 100 µA - 1.1 0.8 V VI(on) on-state input voltage VCE = 0.3 V; IC = 5 mA 2.5 1.7 - V R1 bias resistor 1 (input) 15.4 22 28.6 kΩ R2/R1 bias resistor ratio 0.8 1 1.2 Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz TR1 (NPN) - - 2.5 pF TR2 (PNP) - - 3 pF PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 5 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 006aaa038 103 006aaa039 10−1 hFE (1) (1) (2) (3) VCEsat (V) (2) 102 (3) 10 1 10−1 1 102 10 10−2 1 IC (mA) VCE = 5 V IC/IB = 20 (1) Tamb = 150 °C (1) Tamb = 100 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = −40 °C (3) Tamb = −40 °C Fig 1. TR1 (NPN): DC current gain as a function of collector current; typical values Fig 2. 006aaa040 10 102 10 IC (mA) TR1 (NPN): Collector-emitter saturation voltage as a function of collector current; typical values 006aaa041 10 VI(off) (V) VI(on) (V) (1) (2) (3) 1 (1) (2) 1 (3) 10−1 10−1 1 102 10 10−1 10−2 10−1 IC (mA) IC (mA) VCE = 0.3 V VCE = 5 V (1) Tamb = −40 °C (1) Tamb = −40 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = 100 °C (3) Tamb = 100 °C Fig 3. TR1 (NPN): On-state input voltage as a function of collector current; typical values Fig 4. TR1 (NPN): Off-state input voltage as a function of collector current; typical values PEMD2_PIMD2_PUMD2_7 Product data sheet 101 1 © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 6 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 006aab351 103 RCEsat (Ω) 102 (1) (2) (3) 10 1 10−1 1 102 10 IC (mA) IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −40 °C Fig 5. TR1 (NPN): Collector-emitter saturation resistance as a function of collector current; typical values PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 7 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 006aab197 103 hFE (1) (2) (3) 006aab198 −1 VCEsat (V) 102 −10−1 (1) (2) (3) 10 1 −10−1 −1 −10 −102 −10−2 −1 IC (mA) VCE = −5 V IC/IB = 20 (1) Tamb = 150 °C (1) Tamb = 100 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = −40 °C (3) Tamb = −40 °C Fig 6. −102 −10 IC (mA) TR2 (PNP): DC current gain as a function of collector current; typical values Fig 7. 006aab199 −10 TR2 (PNP): Collector-emitter saturation voltage as a function of collector current; typical values 006aab200 −10 VI(off ) (V) VI(on) (V) (1) (1) (2) −1 (2) −1 (3) (3) −10−1 −10−1 −1 −10 −102 −10−1 −10−2 −10−1 IC (mA) VCE = −0.3 V VCE = −5 V (1) Tamb = −40 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = 100 °C (3) Tamb = 100 °C TR2 (PNP): On-state input voltage as a function of collector current; typical values Fig 9. TR2 (PNP): Off-state input voltage as a function of collector current; typical values PEMD2_PIMD2_PUMD2_7 Product data sheet −10 IC (mA) (1) Tamb = −40 °C Fig 8. −1 © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 8 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 006aab352 103 RCEsat (Ω) 102 (1) (2) (3) 10 1 −10−1 −1 −10 −102 IC (mA) IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −40 °C Fig 10. TR2 (PNP): Collector-emitter saturation resistance as a function of collector current; typical values PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 9 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 8. Package outline 1.7 1.5 6 3.1 2.7 0.6 0.5 5 6 4 1.1 0.9 5 4 2 3 0.6 0.2 0.3 0.1 1.7 1.5 3.0 2.5 1.3 1.1 1.7 1.3 pin 1 index 1 2 1 3 0.18 0.08 0.27 0.17 0.5 pin 1 index 0.40 0.25 0.95 1 0.26 0.10 1.9 Dimensions in mm Dimensions in mm 04-11-08 Fig 11. Package outline PEMD2 (SOT666) 04-11-08 Fig 12. Package outline PIMD2 (SOT457/SC-74) 2.2 1.8 6 2.2 1.35 2.0 1.15 1.1 0.8 5 4 2 3 0.45 0.15 pin 1 index 1 0.3 0.2 0.65 0.25 0.10 1.3 Dimensions in mm 06-03-16 Fig 13. Package outline PUMD2 (SOT363/SC-88) PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 10 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 9. Packing information Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 4000 8000 10000 PEMD2 SOT666 PIMD2 SOT457 PUMD2 SOT363 2 mm pitch, 8 mm tape and reel - - -315 - 4 mm pitch, 8 mm tape and reel - -115 - - 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165 [1] For further information and the availability of packing methods, see Section 13. [2] T1: normal taping [3] T2: reverse taping 10. Soldering 2.75 2.45 2.1 1.6 solder lands 0.4 (6×) 0.25 (2×) 0.538 2 1.7 1.075 0.3 (2×) 0.55 (2×) placement area solder paste occupied area 0.325 0.375 (4×) (4×) Dimensions in mm 1.7 0.45 (4×) 0.6 (2×) 0.5 (4×) 0.65 (2×) sot666_fr Reflow soldering is the only recommended soldering method. Fig 14. Reflow soldering footprint PEMD2 (SOT666) PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 11 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 3.45 1.95 0.45 0.55 (6×) (6×) 0.95 solder lands solder resist 3.3 2.825 0.95 solder paste occupied area 0.7 (6×) Dimensions in mm 0.8 (6×) 2.4 sot457_fr Fig 15. Reflow soldering footprint PIMD2 (SOT457/SC-74) 5.3 1.5 (4×) solder lands 1.475 0.45 (2×) 5.05 solder resist occupied area 1.475 Dimensions in mm preferred transport direction during soldering 1.45 (6×) 2.85 sot457_fw Fig 16. Wave soldering footprint PIMD2 (SOT457/SC-74) PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 12 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 2.65 solder lands 2.35 1.5 0.4 (2×) 0.6 0.5 (4×) (4×) solder resist solder paste 0.5 (4×) 0.6 (2×) occupied area 0.6 (4×) Dimensions in mm 1.8 sot363_fr Fig 17. Reflow soldering footprint PUMD2 (SOT363/SC-88) 1.5 solder lands 0.3 2.5 4.5 solder resist occupied area 1.5 Dimensions in mm 1.3 1.3 preferred transport direction during soldering 2.45 5.3 sot363_fw Fig 18. Wave soldering footprint PUMD2 (SOT363/SC-88) PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 13 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 11. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PEMD2_PIMD2_PUMD2_7 20080924 Product data sheet - PEMD2_PIMD2_PUMD2_6 Modifications: PEMD2_PIMD2_PUMD2_6 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Table 8 “Characteristics”: VCEsat unit corrected Figure 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10: added Section 12 “Legal information”: updated 20040421 Product specification - PEMD2_PIMD2_PUMD2_7 Product data sheet PEMD2_PIMD2_PUMD2_5 © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 14 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 12. Legal information 12.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 12.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 13. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PEMD2_PIMD2_PUMD2_7 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 07 — 24 September 2008 15 of 16 PEMD2; PIMD2; PUMD2 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ 14. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 12.1 12.2 12.3 12.4 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Packing information. . . . . . . . . . . . . . . . . . . . . 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 September 2008 Document identifier: PEMD2_PIMD2_PUMD2_7