SAMSUNG M368L1624DTL-CLA2

M368L1624DTL
184pin Unbuffered DDR SDRAM MODULE
128MB DDR SDRAM MODULE
(16Mx64 based on 16Mx16 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.1
May. 2002
Rev. 0.1 May. 2002
M368L1624DTL
184pin Unbuffered DDR SDRAM MODULE
Revision History
Revision 0 (Jan. 2002)
1. First release for internal usage
Revision 0.1 (May. 2002)
1.Change pin location of A13 from pin 103 to pin 167
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
M368L1624DTL DDR SDRAM 184pin DIMM
16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
GENERAL DESCRIPTION
FEATURE
The Samsung M368L1624DTL is 16M bit x 64 Double Data
• Performance range
Part No.
Rate SDRAM high density memory modules.
Max Freq.
Interface
M368L1624DTL consists of four CMOS 16M x
M368L1624DTL-C(L)B3 166MHz([email protected]=2.5)
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
M368L1624DTL-C(L)A2 133MHz([email protected]=2)
II(400mil) packages mounted on a 184pin glass-epoxy sub-
M368L1624DTL-C(L)B0 133MHz([email protected]=2.5)
The Samsung
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
SSTL_2
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
The M368L1624DTL is Dual In-line Memory Modules and
intended for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK )
of system clock. Data I/O transactions are possible on both
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
edges of DQS. Range of operating frequencies, programmable
• Programmable Burst length (2, 4, 8)
latencies and burst lengths allow the same device to be useful
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
for a variety of high bandwidth, high performance memory system applications.
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB :Height 1250 mil, double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front
Pin
Front Pin
Front
Pin
Back
Pin
Back
1 VREF
2
DQ0
3
VSS
4
DQ1
5 DQS0
6
DQ2
7
VDD
8
DQ3
9
NC
10
NC
11
VSS
12 DQ8
13 DQ9
14 DQS1
15 VDDQ
16
CK1
17 /CK1
18
VSS
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
23 DQ16
24 DQ17
25 DQS2
26
VSS
27
A9
28 DQ18
29
A7
30 VDDQ
31 DQ19
32
A5
62
33 DQ24 6 3
34
VSS 6 4
35 DQ25 6 5
36 DQS3 6 6
37
A4
67
38
VDD 6 8
39 DQ26 6 9
40 DQ27 7 0
41
A2
71
42
VSS 7 2
43
A1
73
44 *CB0 7 4
45 *CB1 7 5
46
VDD 7 6
47 *DQS8 7 7
48
A0
78
49 *CB2 7 9
50
VSS 8 0
51 *CB3 8 1
52
BA1 8 2
KEY
83
53 DQ32 8 4
54 VDDQ 8 5
55 DQ33 8 6
56 DQS4 8 7
57 DQ34 8 8
58
VSS 8 9
59
BA0 9 0
60 DQ35 9 1
61 DQ40 9 2
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
*CK0
*/CK0
VSS
*DM8
A10
*CB6
VDDQ
*CB7
KEY
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
145
146
147
148
149
150
151
152
153
PIN DESCRIPTION
Pin
Back
154
/RAS
155
DQ45
156 VDDQ
157
/CS0
158
*/CS1
159
DM5
160
VSS
161
DQ46
162
DQ47
163
*/CS3
164 VDDQ
165
DQ52
166
DQ53
167
*A13
168
VDD
169
DM6
170
DQ54
171
DQ55
172 VDDQ
173
NC
174
DQ60
175
DQ61
176
VSS
177
DM7
178
DQ62
179
DQ63
180 VDDQ
181
SA0
182
SA1
183
SA2
184 VDDSPD
Pin Name
*
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Bank Select Address
DQ0 ~ DQ63
Data input/output
DQS0 ~ DQS7
Data Strobe input/output
CK1 ,CK1, CK2, CK2
Clock input
CKE0
Clock enable input
CS0
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DM0 ~ DM7
Data - in mask
VDD
Power supply (2.5V)
VDDQ
Power Supply for DQS(2.5V)
VSS
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply ( 2.3V to 3.6V)
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
VDDID
VDD identification flag
NC
No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
FUNCTIONAL BLOCK DIAGRAM
CS0
DQS1
DM1
LDQS
LDM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
DQS5
DM5
D0
DQS4
DM4
CS
LDQS
LDM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS7
DM7
D1
DQS6
DM6
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
D2
CS
D3
*Clock Net Wiring
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D3
A0 - A13
A0-A13: DDR SDRAMs D0 - D3
RAS
CAS : SDRAMs D0 - D3
CKE0
CKE: SDRAMs D0 - D3
WE
WE: SDRAMs D0 - D3
VD D /V DDQ
Cap
RAS : SDRAMs D0 - D3
CAS
V DDSPD
Dram1
R=120Ω
Clock Wiring
Clock
SDRAMs
Input
Card
Edge
NC
2 SDRAMs
2 SDRAMs
CK0/CK0
CK1/CK1
CK2/C K2
Cap
Cap
Dram5
Cap
*If two DRAMs are loaded,
Cap will replace DRAM3
SPD
D0 - D3
D0 - D3
Serial PD
VREF
D0 - D3
SCL
V SS
D0 - D3
WP
SDA
A0
A1
A2
SA0
SA1
SA2
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 May. 2002
M368L1624DTL
184pin Unbuffered DDR SDRAM MODULE
Absolute Maximum Rate
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V SS
V I N, VOUT
-0.5 ~ 3.6
V
Voltage on V D D & V DDQ supply relative to V SS
V DD , VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
6
W
Short circuit current
IOS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V SS =0V, T A=0 to 70°C)
Parameter
Symbol
Min
Max
Supply voltage(for device with a nominal V DD of 2.5V)
V DD
2.3
2.7
I/O Supply voltage
V DDQ
2.3
2.7
V
I/O Reference voltage
V REF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
V TT
V REF-0.04
V REF+0.04
V
2
Input logic high voltage
V I H(DC)
V REF+0.15
V DDQ +0.3
V
4
Input logic low voltage
V IL (DC)
-0.3
V REF-0.15
V
4
Input Voltage Level, CK and CK inputs
V I N(DC)
-0.3
V DDQ +0.3
V
Input Differential Voltage, CK and CK inputs
V I D(DC)
0.3
V DDQ +0.6
V
3
Input crossing point voltage, CK and CK inputs
V IX (DC)
1.15
1.35
V
5
II
-2
2
uA
Output leakage current
IO Z
-5
5
uA
Output High Current(Normal strengh driver)
;V OUT = VT T + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver)
;V OUT = VT T - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver)
;V OUT = V T T + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver)
;V OUT = VT T - 0.45V
IOL
9
mA
I/O Termination voltage(system)
Input leakage current
Unit
Note
Notes 1. Includes ± 25mV margin for DC offset on V REF, and a combined total of ± 50mV margin for all AC noise and DC offset on V REF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF and internal DRAM noise coupled
TO V REF, both of which may result in V REF noise. V REF should be de-coupled with an inductance of ≤ 3nH.
2.V TT is not applied directly to the device. V T T is a system supply for signal termination resistors, is expected to be set equal to
V REF, and must track variations in the DC level of V REF
3. V I D is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
DDR SDRAM module IDD spec table
IDD6
Symbol
B3([email protected]=2.5)
A2([email protected]=2)
B0([email protected]=2.5)
Unit
IDD0
360
320
320
mA
IDD1
500
460
460
mA
IDD2P
12
12
12
mA
IDD2F
100
80
80
mA
IDD2Q
80
72
72
mA
IDD3P
140
120
120
mA
IDD3N
220
180
180
mA
IDD4R
800
680
680
mA
IDD4W
760
620
620
mA
IDD5
720
660
660
mA
Normal
12
12
12
mA
Low power
6
6
6
mA
1400
1200
1200
mA
IDD7A
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC Operating Conditions
Parameter/Condition
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
Max
Unit
Note
V
3
VREF - 0.31
V
3
0.7
VDDQ+0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input Levels(V IH /V IL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
(V DD =2.5V, V DDQ=2.5V, T A= 0 to 70 °C )
Value
Unit
0.5 * V DDQ
V
1.5
V
V REF+0.3 1/V REF -0.3 1
V
V REF
V
V tt
V
Note
See Load Circuit
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
V tt =0.5*V DDQ
RT =50Ω
Output
Z0=50Ω
CLOAD =30pF
V REF
=0.5*V DDQ
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE
(V DD =2.5V, V DDQ =2.5V, TA = 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A 0 ~ A 1 2, BA 0 ~ BA 1,RAS,CAS, WE )
C IN1
29
34
pF
Input capacitance(CKE 0)
C IN2
29
34
pF
Input capacitance( CS 0 )
C IN3
26
30
pF
Input capacitance( CLK 1, CLK 2 )
C IN4
30
32
pF
Data & DQS input/output capacitance(DQ0 ~DQ 63)
COUT
8
9
pF
Input capacitance(DM 0~DM 8)
C IN5
8
9
pF
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
AC Timming Parameters & Specifications
Parameter
(These AC charicteristics were tested on the Component)
-TCB3
(DDR333)
Symbol
Min
Row cycle time
Max
-TCA2
(DDR266A)
Min
Max
-TCB0
(DDR266B)
Min
Unit
tRC
60
65
65
Refresh row cycle time
tRFC
72
75
75
Row active time
tRAS
42
RAS to CAS delay
tRCD
18
20
20
ns
tRP
18
20
20
ns
tRRD
12
15
15
ns
tWR
15
15
15
ns
tWTR
1
1
1
tCK
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
tCCD
CL=2.0
Clock cycle time
CL=2.5
Clock high level width
Clock low level width
70K
1
45
120K
1
45
ns
ns
120K
1
ns
tCK
7.5
12
7.5
12
10
12
ns
5
6
12
7.5
12
7.5
12
ns
5
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/ CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45
-
0.5
-
0.5
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
DQS-in hold time
DQS-out access time from CK/CK
Note
Max
5
2
tWPRE
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tDSC
0.9
Address and Control Input setup time(fast)
tIS
0.75
0.9
0.9
ns
6
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
ns
6
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
ns
6
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
ns
6
Data-out high impedence time from CK/ CK
tHZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data-out low impedence time from CK/ CK
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
DQS-in cycle time
Input Slew Rate(for input only pins)
1.1
0.9
1.1
0.9
tCK
1.1
tCK
tSL(I)
0.5
0.5
0.5
V/ns
Input Slew Rate(for I/O pins)
tSL(IO)
0.5
0.5
0.5
V/ns
6
7
Output Slew Rate(x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
10
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
Parameter
-TCB3
(DDR333)
Symbol
Min
-TCA2
(DDR266A)
Max
Min
-TCB0
(DDR266B)
Max
Min
Unit
Note
Max
Mode register set cycle time
tMRD
12
15
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
ns
7,8,9
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
ns
7,8,9
Control & Address input pulse width
tIPW
2.2
2.2
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
ns
Power down exit time
tPDEX
6
7.5
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
ns
Exit self refresh to read command
tXSRD
200
200
200
tCK
tREFI
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
5
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
Refresh interval time
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
tQHS
0.55
0.6
0.75
tWPST
0.4
0.4
0.6
0.4
tRAP
20
20
20
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
4
0.75
ns
0.6
tCK
3
tCK
11
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with t RCD satisfied after this command.
5. For registered DIMMs, t CL and t CH are ≥ 45% of the period including both the half period jitter (t JIT(HP) ) of the PLL and the half period
jitter due to crosstalk (t JIT(crosstalk) ) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase t IS /tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tDS
∆tDH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+75
+75
0.3
+150
+150
This derating table is used to increase t DS /tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
8. I/O Setup/Hold Plateau Derating
I/O Input Level
∆tDS
∆tDH
(mV)
(ps)
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
∆tDS
∆tDH
(ns/V)
(ps)
(ps)
0
0
0
±0.25
+50
+50
±0.5
+100
+100
This derating table is used to increase t DS /tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cyc le time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
CK slew rate
(Single ended)
∆tIH/tIS
(ps)
∆tDSS/tDSH
(ps)
∆tAC/tDQSCK
(ps)
∆tLZ(min)
(ps)
∆tHZ(max)
(ps)
1.0V/ns
0
0
0
0
0
0.75V/ns
+50
+50
+50
-50
+50
0.5V/ns
+100
+100
+100
-100
+100
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
(V=Valid, X=Don ′t Care, H=Logic High, L=Logic Low)
Command Truth Table
COMMAND
CKEn
CS
RAS
CAS
WE
X
L
L
L
L
OP CODE
1, 2
X
L
L
L
L
OP CODE
1, 2
L
L
L
H
X
L
H
H
H
Register
Extended MRS
H
Register
Mode Register Set
H
Auto Refresh
H
Entry
Refresh
Self
Refresh
Exit
H
BA 0,1
A 10/AP
3
3
H
Bank Active & Row Addr.
H
Read &
Column Address
Auto Precharge Disable
H
Auto Precharge Enable
H
Write &
Column Address
Auto Precharge Disable
L
Burst Stop
Precharge
Bank Selection
X
X
X
X
L
L
H
H
V
X
L
H
L
H
V
X
L
H
L
L
H
X
L
H
H
L
X
L
L
H
L
All Banks
Active Power Down
Entry
H
L
Exit
L
H
Entry
H
L
Precharge Power Down Mode
Exit
DM
No operation (NOP) : Not defined
L
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
H
X
H
H
H
X
X
Note
3
L
L
Auto Precharge Enable
A11 ,A 12
A9 ~ A0
CKEn-1
V
Row Address
L
H
X
X
X
L
H
H
H
Column
Address
(A 0~A 8)
4
Column
Address
(A 0~A 8)
4
X
V
L
X
H
4
4, 6
7
X
5
X
X
X
H
3
X
8
9
9
Note : 1. OP Code : Operand Code. A 0 ~ A12 & BA 0 ~ BA 1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA 1 : Bank select addresses.
If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA 0 and BA 1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t RP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.1 May. 2002
184pin Unbuffered DDR SDRAM MODULE
M368L1624DTL
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118
(3.00)
5.077
(128.950)
B
0.10 0 Min
A
0.7
(17.80 )
(10 .0 0)
( 2.30 Min)
0.39 3
(4 .0 0)
( 2X) 0.15 7
1.25 ± 0.006
(31.75 ± 0.15)
2.500
0.10 M
2.55
1.95
(64.77)
(49.53)
C
B A
0.098 Max
(2.47 Max)
0.050 ± 0.0039
0.157
(4.00)
(2.50 )
0.26
(6.62)
0.250
(6.350)
0 .1 00
(1.270 ± 0.10)
0.118
(3.00)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80 )
Detail A
0.050
(1.270)
Detail B
0.1575
(4.00)
0.10 M
C AM B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 16Mx16 DDR SDRAM, TSOP.
SDRAM Part NO : K4H561638D
Rev. 0.1 May. 2002