CAT93C76 (Rev. A) 8K-Bit Microwire Serial EEPROM FEATURES DESCRIPTION High speed operation: 3MHz @ VCC ≥ 2.5V The CAT93C76 is an 8K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC or Not Connected) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C76 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin PDIP, SOIC, TSSOP and 8-pad TDFN packages. Low power CMOS technology 1.8 to 5.5 volt operation Selectable x8 or x16 memory organization Self-timed write cycle with auto-clear Software write protection Power-up inadvertant write protection 1,000,000 Program/erase cycles 100 year data retention Industrial and extended temperature ranges Sequential read “Green” package option available PIN CONFIGURATION FUNCTIONAL SYMBOL VCC PDIP (L), SOIC (V) TSSOP (Y), TDFN (ZD4) CS 1 8 VCC ORG SK 2 7 NC CS DI 3 6 ORG DO 4 5 GND DI DO SK GND PIN FUNCTION Pin Name Function CS Chip Select SK Serial Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground ORG Memory Organization NC No Connection For Ordering Information details, see page 12. Note: When the ORG pin is connected to VCC, x16 organization is selected. When it is connected to ground, x8 organization is selected. If the ORG pin is left unconnected, then an internal pull-up device will select x16 organization. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) ABSOLUTE MAXIMUM RATINGS (1) Parameters Ratings Units –55 to +125 ºC –65 to 150 ºC -2.0 to +VCC +2.0 V -2.0 to +7.0 V 300 ºC 100 mA Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground (2) VCC with Respect to Ground Lead Soldering Temperature (10 seconds) Output Short Circuit Current (3) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR(4) VZAP(4) ILTH(4)(5) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Units Cycles/Byte Years V mA D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V unless otherwise specified. Symbol Parameter ICC1 Power Supply Current (Write) ICC2 Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current ISB1 ISB2 ILI ILO Test Conditions Min Typ Max Units fSK = 1MHz; VCC = 5.0V 1 3 mA fSK = 1MHz; VCC = 5.0V 300 500 µA 2 10 µA CS = 0V ORG = Float or VCC 0(6) 10 µA VIN = 0V to VCC 0(6) 10 µA (6) 10 µA 1 10 µA CS = 0V ORG = GND 0 Output Leakage Current VOUT = 0V to VCC, CS = 0V ILORG ORG Pin Leakage Current ORG = GND or ORG = VCC VIL1 Input Low Voltage 4.5V ≤ VCC ≤ 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC ≤ 5.5V 2 VCC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC + 1 V VOL1 Output Low Voltage 4.5V ≤ VCC ≤ 5.5V; IOL = 2.1mA 0.4 V VOH1 Output High Voltage 4.5V ≤ VCC ≤ 5.5V; IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V; IOL = 100µA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V; IOH = -100µA 2.4 V 0.1 VCC - 0.2 V V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns. (3) Output shorted for no more than one second. (4) These parameters are tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1V to VCC +1V. (6) 0µA is defined as less than 900nA. Doc. No. MD-1090 Rev. B 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) PIN CAPACITANCE (1) Symbol COUT CIN Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Min Typ Max Units VOUT = 0V 5 pF VIN = 0V 5 pF INSTRUCTION SET (2) Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A10-A0 A9-A0 x8 Comments x16 Read Address AN– A0 ERASE 1 11 A10-A0 A9-A0 WRITE 1 01 A10-A0 A9-A0 Clear Address AN– A0 EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write Enable EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Write Disable ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Clear All Addresses WRAL 1 00 01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0 D7-D0 Write Address AN– A0 D15-D0 Write All Addresses A.C. CHARACTERISTICS Limits Symbol Parameter Test Conditions VCC = 1.8V - 2.5V Min Max VCC = 2.5V - 5.5V Min Units Max tCSS CS Setup Time 100 50 ns tCSH CS Hold Time 0 0 ns tDIS DI Setup Time 100 50 ns tDIH DI Hold Time 100 50 ns tPD1 Output Delay to 1 tPD0 Output Delay to 0 tHZ(1) Output Delay to High-Z tEW Program/Erase Pulse Width CL = 100pF (3) 250 150 ns 250 150 ns 150 100 ns 5 5 ms tCSMIN Minimum CS Low Time 200 150 ns tSKHI Minimum SK High Time 250 150 ns tSKLOW Minimum SK Low Time 250 150 ns tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 250 DC 1000 DC 100 ns 3000 kHz (1)(4) POWER-UP TIMING Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter. (2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ, WRITE and ERASE commands. (3) The input levels and timing reference points are shown in the “AC Test Conditions” table. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V Input Pulse Voltages 0.2VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V Timing Reference Voltages 0.5VCC 1.8V ≤ VCC ≤ 4.5V DEVICE OPERATION Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C76 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). The CAT93C76 is a 8192-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C76 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13-bit instructions control the read, write and erase operations of the device. When organized as X8, seven 14-bit instructions control the read, write and erase operations of the device. The CAT93C76 operates on a single power supply and will generate on chip, the high voltage required during any write operation. For the CAT93C76, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). The most significant bit of the address is “don’t care” but it must be present. Doc. No. MD-1090 Rev. B 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) Figure 1. Sychronous Data Timing tSKHI tSKLOW tCSH SK tDIS tDIH VALID DI VALID tCSS CS tDIS tPD0,tPD1 DO tCSMIN DATA VALID Figure 2. Read Instruction Timing SK CS Don't Care AN DI 1 1 AN-1 A0 0 HIGH-Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Write Instruction Timing SK tCSMIN AN DI STANDBY STATUS VERIFY CS 1 0 AN-1 A0 DN D0 1 tSV DO tHZ BUSY HIGH-Z READY HIGH-Z tEW © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Erase/Write Enable and Disable The CAT93C76 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C76 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Note 1: After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the selftimed high voltage cycle. This is important because if CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Power-On Reset (POR) The CAT93C76 incorporates Power-On Reset (POR) circuitry which protects the device against malfunctioning while VCC is lower than the recommended operating voltage. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be The device will power up into a read-only state and will power-down into a reset state when VCC crosses the POR level of ~1.3 V. Figure 4. Erase Instruction Timing SK STATUS VERIFY CS AN DI DO 1 1 tCS A0 AN-1 STANDBY 1 tSV HIGH-Z tHZ BUSY READY HIGH-Z tEW Doc. No. MD-1090 Rev. B 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) Figure 5. EWEN/EWDS Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE=11 DISABLE=00 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCS DI 1 0 1 0 0 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY STANDBY tCSMIN DI 1 0 0 0 DN 1 D0 tSV tHZ DO BUSY READY HIGH-Z tEW © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) PACKAGE OUTLINE DRAWING PDIP 8-Lead 300mils (L) (1)(2) SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 e PIN # 1 IDENTIFICATION MAX 2.54 BSC E1 6.10 eB 7.87 L 2.92 6.35 7.11 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-001. Doc. No. MD-1090 Rev. B 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) SOIC 8-Lead 150mils (V) (1)(2) E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 MAX c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 e PIN # 1 IDENTIFICATION NOM 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) TSSOP 8-Lead (Y) (1)(2) b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.20 3.10 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.75 8° e TOP VIEW D A2 A A1 c θ1 L1 SIDE VIEW L END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. Doc. No. MD-1090 Rev. B 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) TDFN 8-Pad 3 x 3mm (ZD4) (1)(2) PIN#1 IDENTIFICATION SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 0.50 0.55 0.60 A3 0.20 REF b 0.23 0.30 0.37 D 2.90 3.00 3.10 D2 2.20 2.30 2.40 E 2.90 3.00 3.10 E2 1.40 1.50 1.60 e L 0.65 TYP 0.20 0.30 0.40 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-229. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) EXAMPLE OF ORDERING INFORMATION (1) Prefix Device # Suffix CAT 93C76 V Company ID Product Number 93C76 L: V: Y: ZD4: Package PDIP SOIC, JEDEC TSSOP TDFN (3 x 3mm) I -G Temperature Range I = Industrial (-40ºC to 85ºC) E = Extended (-40ºC to 125ºC) Lead Finish Blank: Matte-Tin G: NiPdAu T3 Tape & Reel T: Tape & Reel (5) 2: 2000 units/Reel 3: 3000 units/Reel Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a 93C76VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel) (4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA.) For additional information, please contact your Catalyst sales office. (5) For TDFN 3 x 3mm package Tape and Reel = 2000 pcs/reel, all others = 3000 pcs/reel. (6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Doc. No. MD-1090 Rev. B 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date Rev. Comments 08/11/2004 A Initial Issue 09/21/2007 B Added Package Outline Drawings Updated the Example of Ordering Information Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™ and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: MD-1090 Revision: B Issue date: 09/21/07