SN54AHC541, SN74AHC541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS261M – DECEMBER 1995 – REVISED JULY 2003 SN54AHC541 . . . J OR W PACKAGE SN74AHC541 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND description/ordering information The ’AHC541 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout. The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A2 A1 OE1 VCC SN54AHC541 . . . FK PACKAGE (TOP VIEW) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 Y3 Y4 Y5 A8 GND Y8 Y7 Y6 A3 A4 A5 A6 A7 OE2 D D ORDERING INFORMATION PDIP – N SN74AHC541N Tube SN74AHC541DW Tape and reel SN74AHC541DWR SOP – NS Tape and reel SN74AHC541NSR AHC541 SSOP – DB Tape and reel SN74AHC541DBR HA541 Tube SN74AHC541PW Tape and reel SN74AHC541PWR TSSOP – PW –55°C to 125°C TOP-SIDE MARKING Tube SOIC – DW –40°C 40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74AHC541N AHC541 HA541 TVSOP – DGV Tape and reel SN74AHC541DGVR HA541 CDIP – J Tube SNJ54AHC541J SNJ54AHC541J CFP – W Tube SNJ54AHC541W SNJ54AHC541W LCCC – FK Tube SNJ54AHC541FK SNJ54AHC541FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHC541, SN74AHC541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS261M – DECEMBER 1995 – REVISED JULY 2003 FUNCTION TABLE (each buffer/driver) INPUTS A OUTPUT Y OE1 OE2 L L L L L L H H H X X Z X H X Z logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 Y1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC541, SN74AHC541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS261M – DECEMBER 1995 – REVISED JULY 2003 recommended operating conditions (see Note 3) SN54AHC541 VCC Supply voltage VIH VCC = 2 V VCC = 3 V High-level input voltage Low-level input voltage VI VO 2 5.5 Output voltage ∆t/∆v 5.5 2.1 V V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC –50 0 VCC –50 mA VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V Input transition rise or fall rate 2 UNIT 1.5 3.85 VCC = 2 V VCC = 3.3 V ± 0.3 V Low-level output current MAX 2.1 VCC = 5 V ± 0.5 V VCC = 2 V IOL MIN 3.85 VCC = 3 V VCC = 5.5 V High-level output current SN74AHC541 0.5 Input voltage IOH MAX 1.5 VCC = 5.5 V VCC = 2 V VIL MIN VCC = 5 V ± 0.5 V –4 –4 –8 –8 50 50 4 4 8 8 100 100 20 20 V mA mA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 IOH = –4 mA 3V 2.58 2.48 2.48 IOH = –8 mA 4.5 V 3.94 3.8 3.8 TEST CONDITIONS VCC IOH = –50 mA VOH IOL = 50 mA VOL IOL = 4 mA II IOL = 8 mA VI = 5.5 V or GND IOZ† VO = VCC or GND, VI (OE) = VIL or VIH ICC Ci VI = VCC or GND, VI = VCC or GND IO = 0 SN54AHC541 MIN MAX SN74AHC541 MIN MAX UNIT V 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 V 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1* ±1 mA 5.5 V ±0.25 ±2.5 ±2.5 mA 4 40 40 mA 10 pF 5.5 V 5V 2 Co 10 VO = VCC or GND 5V 4 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † For input and ouput, IOZ includes the input leakage current. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF 3 SN54AHC541, SN74AHC541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS261M – DECEMBER 1995 – REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC541 SN74AHC541 MIN MAX MIN MAX 5* 7* 1* 8.5* 1 8.5 5* 7* 1* 8.5* 1 8.5 6* 10.5* 1* 11* 1 11 6* 10.5* 1* 11* 1 11 7* 11* 1* 12* 1 12 7* 11* 1* 12* 1 12 7.5 10.5 1 12 1 12 7.5 10.5 1 12 1 12 8 14 1 16 1 16 8 14 1 16 1 16 9 15.4 1 17.5 1 17.5 9 15.4 1 17.5 1 17.5 tsk(o) CL = 50 pF ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. ∗∗ On products compliant to MIL-PRF-38535, this parameter does not apply. 1.5** 1.5 UNIT ns ns ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25°C TYP MAX POST OFFICE BOX 655303 SN74AHC541 MIN MAX MIN MAX 3.5* 5* 1* 6* 1 6 3.5* 5* 1* 6* 1 6 4.7* 7.2* 1* 8.5* 1 8.5 4.7* 7.2* 1* 8.5* 1 8.5 5* 7.5* 1* 8* 1 8 5* 7.5* 1* 8* 1 8 5 7 1 8 1 8 5 7 1 8 1 8 6.2 9.2 1 10.5 1 10.5 6.2 9.2 1 10.5 1 10.5 6 8.8 1 10 1 10 6 8.8 1 10 1 10 tsk(o) CL = 50 pF ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. ∗∗ On products compliant to MIL-PRF-38535, this parameter does not apply. 4 SN54AHC541 • DALLAS, TEXAS 75265 1** 1 UNIT ns ns ns ns ns ns ns SN54AHC541, SN74AHC541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS261M – DECEMBER 1995 – REVISED JULY 2003 noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHC541 PARAMETER MIN MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.8 V Quiet output, minimum dynamic VOL –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.7 High-level dynamic input voltage 3.5 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V V 1.5 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 12 pF 5 SN54AHC541, SN74AHC541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS261M – DECEMBER 1995 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL VCC Output Control Output Waveform 1 S1 at VCC (see Note B) 50% VCC 0V tPZL VOH 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9685701Q2A ACTIVE LCCC FK 20 1 TBD 5962-9685701QRA ACTIVE CDIP J 20 1 TBD 1 Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type TBD A42 N / A for Pkg Type TBD Call TI 5962-9685701QSA ACTIVE CFP W 20 SN74AHC541DBLE OBSOLETE SSOP DB 20 SN74AHC541DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541DGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AHC541NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AHC541NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541NSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541PWLE OBSOLETE TSSOP PW 20 SN74AHC541PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC541PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54AHC541FK ACTIVE LCCC FK 20 1 TBD SNJ54AHC541J ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SNJ54AHC541W ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type TBD (1) Call TI Call TI Call TI POST-PLATE N / A for Pkg Type The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2006 a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 30-Apr-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AHC541DBR DB 20 MLA 330 16 8.2 7.5 2.5 12 16 Q1 SN74AHC541DGVR DGV 20 MLA 330 12 7.0 5.6 1.6 8 12 Q1 SN74AHC541DWR DW 20 MLA 330 24 10.8 13.0 2.7 12 24 Q1 SN74AHC541NSR NS 20 MLA 330 24 8.2 13.0 2.5 12 24 Q1 SN74AHC541PWR PW 20 MLA 330 16 6.95 7.1 1.6 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74AHC541DBR DB 20 MLA 333.2 333.2 28.58 SN74AHC541DGVR DGV 20 MLA 338.1 340.5 20.64 SN74AHC541DWR DW 20 MLA 333.2 333.2 31.75 SN74AHC541NSR NS 20 MLA 333.2 333.2 31.75 SN74AHC541PWR PW 20 MLA 333.2 333.2 28.58 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2007 Pack Materials-Page 3 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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