[ /Title (CD74 HC280 , CD74 HCT28 0) /Subject (High Speed CMOS Logic 9-Bit Odd/E ven Parity CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 Data sheet acquired from Harris Semiconductor SCHS175D High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker November 1997 - Revised October 2003 Features Description • Typical Propagation Delay = 17ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator checker devices. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (ΣE output is high) when an even number of data inputs is high. Odd parity is indicated (ΣO output is high) when an odd number of data inputs is high. Parity checking for words larger than 9 bits can be accomplished by tying the ΣE output to any input of an additional HC/HCT280 parity checker. • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Replaces LS180 Types • Easily Cascadable • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH TEMP. RANGE (oC) CD54HC280F3A -55 to 125 14 Ld CERDIP CD54HCT280F3A -55 to 125 14 Ld CERDIP CD74HC280E -55 to 125 14 Ld PDIP CD74HC280MT -55 to 125 14 Ld SOIC CD74HC280M96 -55 to 125 14 Ld SOIC CD74HCT280E -55 to 125 14 Ld PDIP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout Functional Diagram CD54HC280, CD54HCT280 (CERDIP) CD74HC280 (PDIP, SOIC) CD74HCT280 (PDIP) TOP VIEW I0 I1 I2 I3 I6 1 14 VCC I7 2 13 I5 NC 3 12 I4 I8 4 11 I3 ΣE 5 10 I2 ΣO 6 9 I1 GND 7 8 I0 8 9 10 5 11 I5 I7 I8 6 13 1 ∑ ODD 1 2 4 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. © 2003, Texas Instruments Incorporated ∑ EVEN 12 I4 I6 Copyright PACKAGE GND = 7 VCC = 14 NC = 3 CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 2 CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 200 250 300 ns 4.5 - 40 50 60 ns 6 - 34 43 51 ns CL = 15pF 5 17 - - - ns CL = 50pF 2 - 200 250 300 ns 4.5 - 40 50 60 ns 6 - 34 43 51 ns 5 17 - - - ns HC TYPES Propagation Delay, Any Input to ΣO Propagation Delay, Any Input to ΣE tPLH, tPHL CL = 15pF 3 CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 Switching Specifications PARAMETER Output Transition Time Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tTLH, tTHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns Input Capacitance CI - - - 10 10 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 58 - - - pF CL = 50pF 4.5 - 45 56 68 ns CL = 15pF 5 19 - - - ns CL = 50pF 4.5 - 42 53 63 ns CL = 15pF 5 18 - - - ns CL = 50pF 4.5 - 15 19 22 ns HCT TYPES Propagation Delay, Any Input to ΣO tPLH, tPHL Propagation Delay, Any Input to ΣE tPLH, tPHL Output Transition Time tTLH, tTHL Input Capacitance CIN - - - 10 10 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 58 - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 4 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 8607701CA ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC CD54HC280F3A ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC CD54HCT280F3A ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC CD74HC280E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC280EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC280M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC280M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC280MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC280MTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT280E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT280EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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