FREESCALE MC100ES60T22DT

MC100ES60T22
Rev 2, 2/2005
Freescale Semiconductor
Technical Data
3.3 V Dual LVTTL/LVCMOS to
Differential LVPECL Translator
MC100ES60T22
The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential
LVPECL translator. The low voltage PECL levels, small package, and dual gate
design are ideal for clock translation applications.
Features
•
•
•
•
•
280 ps typical propagation delay
100 ps max output-to-output skew
LVPECL operating range: VCC = 3.135 V to 3.8 V
8-lead SOIC and 8-lead TSSOP packages
Ambient temperature range –40°C to +85°C
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 1640-01
Q0
1
8
ORDERING INFORMATION
VCC
Device
Q0
2
7
LVPECL
Q1
D0
LVTTL/LVCMOS
3
6
SOIC-8
MC100ES60T22DR2
SOIC-8
MC100ES60T22DT
TSSOP-8
MC100ES60T22DTR2
TSSOP-8
PIN DESCRIPTION
D1
Pin
Q1
4
5
GND
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Package
MC100ES60T22D
Function
D0, D1
LVTTL/LVCMOS Inputs
Qn, Qn
LVPECL Differential Outputs
VCC
Positive Supply
GND
Negative Supply
Table 1. General Specifications
Characteristics
Value
Internal Input Pulldown Resistor
75 kΩ
Internal Input Pullup Resistor
75 kΩ
ESD Protection
Human Body Model
Machine Model
> 2000 V
> 200 V
θJA Thermal Resistance (Junction-to-Ambient)
0 LFPM, 8 SOIC
500 LFPM, 8 SOIC
0 LFPM, 8 TSSOP
500 LFPM, 8 TSSOP
190°C/W
130°C/W
185°C/W
140°C/W
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Table 2. Absolute Maximum Ratings(1)
Symbol
Rating
Conditions
Rating
Units
3.9
V
VCC + 0.3
VEE – 0.3
V
V
50
100
mA
mA
Power Supply Voltage
Difference between VCC & VEE
VIN
Input Voltage
VCC – VEE ≤ 3.6 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
–40 to +85
°C
Storage Temperature Range
–65 to +150
°C
VSUPPLY
TSTG
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 3. DC Characteristics (VCC = 3.135 V to 3.8 V; VEE = 0 V)
-40°C
Symbol
(1)
VOL(1)
VOH
Characteristic
Min
Typ
Output HIGH Voltage
VCC – 1150
Output LOW Voltage
VCC – 1950
0°C to 85°C
Max
Min
VCC – 1020
VCC – 800
VCC – 1200
VCC – 1620
VCC – 1250
VCC – 2000
Typ
Max
Unit
VCC – 970
VCC – 750
mV
VCC – 1680
VCC – 1300
mV
Max
Unit
1. Outputs are terminated through a 50 Ω resistor to VCC – 2 volts.
Table 4. LVTTL / LVCMOS Input DC Characteristics (VCC = 3.135 V to 3.8 V)
-40°C
Symbol
Characteristic
Condition
Min
Typ
0°C to 85°C
Max
Min
Typ
IIN
Input Current
VIN = VCC
±150
±150
µA
VIK
Input Clamp Voltage
IIN = –18 mA
–1.2
–1.2
V
VIH
Input HIGH Voltage
VCC+0.3
V
VIL
Input LOW Voltage
0.8
V
2.0
VCC+0.3
0.8
2.0
MC100ES60T22
2
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 5. AC Characteristics (VCC = 3.134 V to 3.8 V; VEE = 0 V)
-40°C
Symbol
Characteristic
fmax
Maximum Toggle Frequency
tPLH,
tPHL
Propagation Delay
tSKEW
Skew
Min
Max
Min
Typ
1
100
260
400
85°C
Max
Min
Typ
1
100
280
400
100
280
Max
Unit
1
GHz
450
ps
part-to-part
300
300
350
ps
RMS (1σ)
1
1
1
ps
tJITTER Cycle-to-Cycle Jitter
VoutPP Output Peak-to-Peak Voltage
tr / tf
Typ
25°C
350
Output Rise/Fall Times (20% – 80%)
750
50
350
400
750
50
Q
350
400
50
750
mV
400
ps
D
Driver
Device
Receiver
Device
Qb
Db
50Ω
50Ω
V TT
Figure 2. Typical Termination for Output Driver and Device Evaluation
MC100ES60T22
Advanced Clock Drivers Devices
Freescale Semiconductor
3
PACKAGE DIMENSIONS
D
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
B
e
X 45˚
θ
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
θ
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0˚
7˚
SOIC-8
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
ISSUE T
MC100ES60T22
4
Advanced Clock Drivers Devices
Freescale Semiconductor
PACKAGE DIMENSIONS
2X
3
0.20 C
3.00
1.95
1.5
A
D
8
2
0.60
1
0.60 2.45
B
1.5
3
3.00
H
4.90
B
2X
SEE VIEW C
0.20 C D
VIEW A-A
0.65
0.325
B
8X
0.18
0.13
8
0.38
0.25
0.13
0.23
0.13
BASE METAL
C A-B D
M
0.48 MAX
TOP VIEW
DETAIL "B"
A
0.38
0.25
0.33
0.25
0.25 C
8
SECTION B-B
SEE NOTE 6
DAMBAR PROTRUSION
DETAIL "B"
0.95
0.75
8X
0.10 C
1.10 MAX
SEATING PLANE
0.15
0.05
C
A
SIDE VIEW
4X
15˚
5˚
0.07 MIN
0.25
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND ARE MEASURED AT DATUM H, MOLD FLASH OR PROTRUSIONS,
SHALL NOT EXCEED 0.15mm PER SIDE.
4. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A
SUBSTRATE.
5. THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS
OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD
FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.14mm SEE DETAIL "B" AND SECTION B-B.
6. SECTION B-B TO BE DETERMINED AT 0.10 TO 0.25mm FROM THE LEAD TIP.
7. THIS PART IS COMPLIANT WITH JEDEC REGISTRATION MO-187 AA.
8. DATUMS A AND B TO BE DETERMINED DATUM PLANE H.
GAUGE PLANE
SEATING PLANE
6˚
0˚
0.70
0.40
4
4X
15˚
5˚
C
(0.95)
VIEW C
TSSOP-8
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 1640-01
ISSUE O
MC100ES60T22
Advanced Clock Drivers Devices
Freescale Semiconductor
5
NOTES
MC100ES60T22
6
Advanced Clock Drivers Devices
Freescale Semiconductor
NOTES
MC100ES60T22
Advanced Clock Drivers Devices
Freescale Semiconductor
7
NOTES
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MC100ES60T22
Rev. 2
2/2005
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