Product Preview GS8150V18/36AB-357/333/300/250 119-Bump BGA Commercial Temp Industrial Temp 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 250 MHz–357 MHz 1.8 V VDD 1.5 V or 1.8 V HSTL I/O Features Functional Description • Register-Register Late Write mode, Pipelined Read mode • 1.8 V +150/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • ZQ controlled programmable output drivers • Dual Cycle Deselect • Fully coherent read and write pipelines • Byte write operation (9-bit bytes) • Differential HSTL clock inputs, K and K • Asynchronous output enable • Sleep mode via ZZ • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • JEDEC-standard 119-bump BGA package • Pb-Free 119-bump BGA package available Because GS8150V18/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally selftimed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. GS8150V18/36A support pipelined reads utilizing a risingedge-triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. GS8150V18/36A are implemented with high performance HSTL technology and are packaged in a 119-bump BGA. Family Overview GS8150V18/36A are 18,874,368-bit (18Mb) high performance SRAMs. This family of wide, very low voltage HSTL I/O SRAMs is designed to operate at the speeds needed to implement economical high performance cache systems. Mode Control There are two mode control select pins (M1 and M2), which allow the user to set the correct read protocol for the design. The GS8150V18/36A support single clock Pipeline mode, which directly affects the two mode control select pins. In order for the part to fuction correctly, and as specified, M1 must be tied to VSS and M2 must be tied to VDD or VDDQ. This must be set at power-up and should not be changed during operation. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Parameter Synopsis Pipeline Rev: 1.04 4/2005 -357 -333 -300 -250 Unit Cycle tKHQV 2.8 1.4 3.0 1.5 3.3 1.6 4.0 2.0 ns ns Curr (x18) Curr (x36) 600 650 550 600 500 550 450 500 mA mA 1/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 GS8150V36 Pinout—119-Bump BGA—Top View (Package B) Rev: 1.04 4/2005 1 2 3 4 5 6 7 A VDDQ A A NC A A VDDQ B NC A A NC A A NC C NC A A VDD A A NC D DQC DQC VSS ZQ VSS DQB DQB E DQC DQC VSS SS VSS DQB DQB F VDDQ DQC VSS G VSS DQB VDDQ G DQC DQC BC NC BB DQB DQB H DQC DQC VSS NC VSS DQB DQB J VDDQ VDD VREF VDD VREF VDD VDDQ K DQD DQD VSS CK VSS DQA DQA L DQD DQD BD CK BA DQA DQA M VDDQ DQD VSS SW VSS DQA VDDQ N DQD DQD VSS A VSS DQA DQA P DQD DQD VSS A VSS DQA DQA R NC A M1 VDD M2 A NC T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ 2/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 GS8150V18 Pinout—119-Bump BGA—Top View (Package B) Rev: 1.04 4/2005 1 2 3 4 5 6 7 A VDDQ A A NC A A VDDQ B NC A A NC A A NC C NC A A VDD A A NC D DQB NC VSS ZQ VSS DQA NC E NC DQB VSS SS VSS NC DQA F VDDQ NC VSS G VSS DQA VDDQ G NC DQB BB NC NC NC DQA H DQB NC VSS NC VSS DQA NC J VDDQ VDD VREF VDD VREF VDD VDDQ K NC DQB VSS CK VSS NC DQA L DQB NC NC CK BA DQA NC M VDDQ DQB VSS SW VSS NC VDDQ N DQB NC VSS A VSS DQA NC P NC DQB VSS A VSS NC DQA R NC A M1 VDD M2 A NC T NC A A NC A A ZZ U VDDQ TMS TDI TCK TDO NC VDDQ 3/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 GS8150V18/36 BGA Pin Description Symbol Type Description A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I Clock Input Signal; active high CK I Clock Input Signal; active low SW I Write Enable; active low G I Output Enable; active low ZZ I Sleep mode control; active high M1 I Read Operation Protocol Select—Selects Register-Register read operations; must be tied low in this device M2 I Read Operation Protocol Select—Selects Register-Register read operations; must be tied high in this device ZQ I FLXDrive-II™ Output Impedance Control SS I Synchronous Select Input TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock VREF I Input Reference Voltage VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply Read Operations Pipelined Read A read cycle begins when the RAM captures logic 0 on SS and logic 1 on SW at the rising edge of K (and the falling edge of K). Address inputs captured on that clock edge are propigated into the RAM, which delivers data to the input of the output registers. The second rising edge of K fires the output registers and releases read data to the output drivers. If G is held active low, the drivers drive the data onto the output pins. Read data is sustained on the output pins as long as G is held low or until the next rising edge of K, at which point the outputs may update to new data or deselect, depending on what control command was registered at the second rising edge of K. Dual Cycle Deselect Chip deselect (SS = logic 1) is pipelined to the same degree as read data. Therefore, a deselect command entered on the rising edge of K is acted upon in response to the next rising edge of K. Rev: 1.04 4/2005 4/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Write Operations Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge of the K clock (and falling edge of the K clock). Late Write In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT SRAMs. Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control inputs are captured by the same clock edge used to capture SW. Example of x36 Byte Write Truth Table Function SW Ba Bb Bc Bd Read H X X X X Write Byte A L L H H H Write Byte B L H L H H Write Byte C L H H L H Write Byte D L H H H L Write all Bytes L L L L L Write Abort L H H H H FLXDrive-II™ HSTL Output Driver Impedance Control HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired SRAM driver impedance. The allowable range of RQ to guarantee impedance matching with specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance occurs automatically because driver impedance is affected by drifts in supply voltage and die temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up clock cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output driver impedance. Rev: 1.04 4/2005 5/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Register-Register Late Write, Pipelined Read Truth Table CK ZZ SS SW Bx G Current Operation DQ (tn) DQ (tn+1) X 1 X X X X Sleep (Power Down) mode Hi-Z Hi-Z ↑ 0 1 X X X Deselect *** Hi-Z ↑ 0 0 1 X 1 Read Hi-Z/ Hi-Z ↑ 0 0 1 X 0 Read *** Q(tn) ↑ 0 0 0 0 X Write All Bytes *** D(tn) ↑ 0 0 0 X X Write Bytes with Bx = 0 *** D(tn) ↑ 0 0 0 1 X Write (Abort) *** Hi-Z Notes: 1. If one or more Bx = 0, then B = “T” else B = “F”. 2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”. 3. “***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation. 4. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled. 5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled. 6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address. Rev: 1.04 4/2005 6/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.5 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VI/O Voltage on I/O Pins –0.5 to VDDQ + 0.5 (≤ 2.5 V max.) V VIN Voltage on Other Input Pins –0.5 to VDDQ + 0.5 (≤ 2.5 V max.) V IIN Input Current on Any Pin +/–100 mA dc IOUT Output Current on Any I/O Pin +/–100 mA dc TJ Maximum Junction Temperature 125 oC TSTG Storage Temperature –55 to 125 ºC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 1.7 1.8 1.95 V 1.5 V I/O Supply Voltage VDDQ 1.4 1.5 1.6 V 1.8 V I/O Supply Voltage VDDQ 1.7 1.8 1.9 V Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C Notes 1 Note: The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Rev: 1.04 4/2005 7/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 HSTL I/O DC Input Characteristics Parameter Symbol Min Typ Max Units Notes DC Input Logic High VIH (dc) VREF + 100 — VDDQ + 300 mV DC Input Logic Low VIL (dc) –300 — VREF – 100 mV DC Clock Input Differential Voltage VDIF (dc) 100 — VDDQ + 300 mV 2 VREF DC Voltage VREF (dc) VDDQ /2 – 0.1 — VDDQ /2 + 0.1 V 1 Clock Input Voltag VCK (dc) –300 — VDDQ + 300 V Clock Input Commone Mode Voltage VCM (dc) 600 750 900 V Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. SRAM performance is a function of clock input differential voltage (VDIF). 3. To guarantee AC characteristics, VIH,VIL,Trise and Tfall of inputs and clocks must be within 10% of each other. 4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers. 5. See AC Input Definition drawing below. HSTL I/O AC Input Characteristics Parameter Symbol Min Max Units Notes AC Input Logic High VIH (ac) VREF + 200 — mV 3,4 AC Input Logic Low VIL (ac) — VREF – 200 mV 3,4 AC Clock Input Differential Voltage VDIF (ac) 800 — mV 2,3 VREF Peak to Peak AC Voltage VREF (ac) — 5% VREF (DC) mV 1 Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. SRAM performance is a function of clock input differential voltage (VDIF). The RAM can be operated with a single ended clocking with either CK or CK tied to VREF. 3. To guarantee AC characteristics, VIH,VIL,Trise and Tfall of inputs and clocks must be within 10% of each other. 4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers. 5. See AC Input Definition drawing below. Rev: 1.04 4/2005 8/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 HSTL I/O AC Input Definitions VDDQ VIH (AC) VIH (DC) VREF VIL (DC) VIH (AC) VSS Differential Voltage and Common Mode Voltage Common Mode and Differential Voltage 1.8 1.6 1.4 1.2 1 0.8 0.6 VCM 0.4 K K# VCM VDIF Volts 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 0 20 40 60 80 100 120 Time Rev: 1.04 4/2005 9/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 1.0 V VSS 50% 50% VDD VSS – 1.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 1.8 V) Parameter Symbol Test conditions Max. Unit Input Capacitance CIN VIN = 0 V 4 pF Output Capacitance COUT VOUT = 0 V 5 pF Output Capacitance (Clock) CIN(CK) VIN = 0 V 5 pF Note: This parameter is sample tested. AC Test Conditions Rev: 1.04 4/2005 Parameter Conditions Input high level 1.25 V Input low level 0.25 V Input rise/fall time (10% to 90%) 0.5 ns/0.5 ns Input reference level VDDQ/2 Clock input reference level Differential cross point Output reference level VDDQ/2 Clock (VDIF) 0.75 V Clock (VCM) 0.75 V VDDQ 1.5 V RQ 250Ω 10/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 AC Test Load Diagram 50Ω VDDQ/2 50Ω Device Under Test VDDQ = 1.5 V 5pF 25Ω DQ VDDQ/2 50Ω ZQ 50Ω VDDQ/2 5pF RQ = 250Ω Input and Output Leakage Characteristics Parameter Symbol Test Conditions Min. Max Notes Input Leakage Current (except mode pins) IIL VIN = 0 to VDDQ –2 uA 2 uA — ZQ, MCH, MCL, EP2, EP3 Pin Input Current IINM VIN = 0 to VDDQ –50 uA 50 uA — Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA 2 uA — Operating Currents -357 HSTL Deselect Current Rev: 1.04 4/2005 -300 -250 Symbol 0°C to 70°C –40°C to +85°C 0°C to 70°C –40°C to +85°C 0°C to 70°C –40°C to +85°C 0°C to 70°C –40°C to +85°C Test Conditions x36 IDD 650 mA 660 mA 600 mA 610 mA 550 mA 560 mA 500 mA 510 mA x18 IDD 600 mA 610 mA 550 mA 560 mA 500 mA 510 mA 450 mA 460 mA SS ≤ VIL Max. tKHKH ≥ tKHKH Min. All other inputs VIL ≥ VIN ≥ VIH Parameter Operating Current -333 IDD3 150 mA 160 mA 150 mA 160 mA 150 mA 160 mA 150 mA 11/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 160 mA Device Deselected All inputs VSS + 0.10 V ≥ VIN ≥ VDD – 0.10 V © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 AC Electrical Characteristics Parameter Symbol Clock Cycle Time -357 -333 -300 -250 Unit Notes — ns — 1.5 — ns — — 1.5 — ns — — 0.5 — ns 1 1.6 — 2.0 ns — — 0.5 — ns — 1.6 — 2.0 ns 1 0.7 — 0.8 — ns — — 0.4 — 0.5 — ns — 0.6 — 0.7 — 0.8 — ns — — 0.4 — 0.4 — 0.5 — ns — 0.5 — 0.6 — 0.7 — 0.8 — ns — tKHWX 0.4 — 0.4 — 0.4 — 0.5 — ns — Byte Write Valid to Clock High tBVKH 0.5 — 0.6 — 0.7 — 0.8 — ns — Clock High to Byte Write Don’t Care tKHBX 0.4 — 0.4 — 0.4 — 0.5 — ns — Data In Valid to Clock High tDVKH 0.5 — 0.5 — 0.5 — 0.5 — ns — Clock High to Data In Don’t Care tKHDX 0.4 — 0.4 — 0.4 — 0.5 — ns — Output Enable Low to Output Data Valid tGLQV — 1.4 — 1.5 1.6 — 2.0 ns — Output Enable Low to Output Data Low-Z tGLQX 0 — 0 — — 0 — ns — Output Enable High to Output Data High-Z tGHQZ — 1.4 — 1.5 1.6 — 2.0 ns — Sleep Mode Enable Time tZZE — 15 — 15 — 15 — 15 ns — Sleep Mode Recovery Time tZZR 20 — 20 — 20 — 20 — ns — Min Max Min Max Min Max Min Max tKHKH 2.8 — 3.0 — 3.3 — 4.0 Clock High Time tKHKL 1.1 — 1.2 — 1.3 — Clock Low Time tKLKH 1.1 — 1.2 — 1.3 Clock High to Output Low-Z tKHQX1 0.5 — 0.5 — 0.5 Clock High to Output Valid tKHQV — 1.4 — 1.5 Clock High to Output Invalid tKHQX 0.5 — 0.5 — Clock High to Output High-Z tKHQZ — 1.4 — 1.5 Address Valid to Clock High tAVKH 0.5 — 0.6 — Clock High to Address Don’t Care tKHAX 0.4 — 0.4 Enable Valid to Clock High tEVKH 0.5 — Clock High to Enable Don’t Care tKHEX 0.4 Write Valid to Clock High tWVKH Clock High to Write Don’t Care 0.5 0 Notes: 1. Measured at 100 mV from steady state. Not 100% tested. 2. Guaranteed by design. Not 100% tested. Rev: 1.04 4/2005 12/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 G Controlled Read-Write Read A1 Read A2 Read A0 Write A3 Write A4 Read A5 Read A4 Read A6 Read A7 KHKL KHKH KLKH K tAVKH tKHAX A A1 A2 A0 A3 A4 A5 A4 A6 A7 G tWVKH tKHWX SW tWVKH tKHWX BWx KHQX GLQV GLQX DQn Q1 DVKH KHDX GHQZ Q2 D3 KHQV KHQX1 D4 Q5 Q4 Q6 Note: K is not shown; assumes K tied to VREF or out of phase with K SS Controlled Read-Write Read A1 Read A2 Deselect Write A3 Write A4 Read A5 Read A4 Read A6 Read A7 KHKL KHKH KLKH K tAVKH tKHAX A A1 A2 A3 A4 A5 A4 A6 A7 tEVKH tKHEX SS tWVKH tKHWX SW tBVKH tKHBX BWx KHQZ KHQX1 DQn Q1 tDVKH tKHDX KHQV Q2 D3 D4 KHQX Q5 Q4 Note: K is not shown; assumes K tied to VREF or out of phase with K Rev: 1.04 4/2005 13/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 ZZ Timing Read A1 Read A2 Deselect Clock is a Don't care during Sleep ModeRead A1 Read A2 Read A3 KHKL KHKH KLKH K tAVKH tKHAX A A1 A2 A1 A2 A3 tEVKH tKHEX SS tWVKH tKHWX SW SWx Begin ISB ZZR ZZ ZZE KHQX KHQX1 DQn Q1 KHQV Q2 Q1 Note: K is not shown; assumes K tied to VREF or out of phase with K JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.04 4/2005 14/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 JTAG Port Registers JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.04 4/2005 15/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 JTAG TAP Block Diagram · · · · · · Boundary Scan Register · · 0 Bypass Register 0 108 · 1 · · 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · · · 2 1 0 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.04 4/2005 16/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Die Revision Code GSI Technology JEDEC Vendor ID Code I/O Configuration Not Used Presence Register Tap Controller Instruction Set ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.04 4/2005 17/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 1 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 1.04 4/2005 18/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.04 4/2005 19/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 JTAG Port AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 JTAG Port AC Test Load DQ 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.04 4/2005 20/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns Rev: 1.04 4/2005 21/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Package Dimensions—119-Bump FPBGA (Package B, Variation 2) TOP VIEW A1 1 2 3 4 5 6 BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) 7 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U 20.32 22±0.10 1.27 A B C D E F G H J K L M N P R T U B 0.15 C 7.62 C Rev: 1.04 4/2005 SEATING PLANE A 0.20(4x) 14±0.10 0.50~0.70 1.86.±0.13 0.56±0.05 0.70±0.05 0.15 C 1.27 22/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Ordering Information Org Part Number Type I/O Speed (MHz) TA 1M x 18 GS8150V18AB-357 Register-Register Late Write SRAM HSTL 357 MHz C 1M x 18 GS8150V18AB-333 Register-Register Late Write SRAM HSTL 333 MHz C 1M x 18 GS8150V18AB-300 Register-Register Late Write SRAM HSTL 300 MHz C 1M x 18 GS8150V18AB-250 Register-Register Late Write SRAM HSTL 250 MHz C 512K x 36 GS8150V36AB-357 Register-Register Late Write SRAM HSTL 357MHz C 512K x 36 GS8150V36AB-333 Register-Register Late Write SRAM HSTL 333 MHz C 512K x 36 GS8150V36AB-300 Register-Register Late Write SRAM HSTL 300 MHz C 512K x 36 GS8150V36AB-250 Register-Register Late Write SRAM HSTL 250 MHz C 1M x 18 GS8150V18AB-357I Register-Register Late Write SRAM HSTL 357 MHz I 1M x 18 GS8150V18AB-333I Register-Register Late Write SRAM HSTL 333 MHz I 1M x 18 GS8150V18AB-300I Register-Register Late Write SRAM HSTL 300 MHz I 1M x 18 GS8150V18AB-250I Register-Register Late Write SRAM HSTL 250 MHz I 512K x 36 GS8150V36AB-357I Register-Register Late Write SRAM HSTL 357 MHz I 512K x 36 GS8150V36AB-333I Register-Register Late Write SRAM HSTL 333 MHz I 512K x 36 GS8150V36AB-300I Register-Register Late Write SRAM HSTL 300 MHz I 512K x 36 GS8150V36AB-250I Register-Register Late Write SRAM HSTL 250 MHz I 1M x 18 GS8150V18AGB-357 Pb-Free Register-Register Late Write SRAM HSTL 357 MHz C 1M x 18 GS8150V18AGB-333 Pb-Free Register-Register Late Write SRAM HSTL 333 MHz C 1M x 18 GS8150V18AGB-300 Pb-Free Register-Register Late Write SRAM HSTL 300 MHz C 1M x 18 GS8150V18AGB-250 Pb-Free Register-Register Late Write SRAM HSTL 250 MHz C 512K x 36 GS8150V36AGB-357 Pb-Free Register-Register Late Write SRAM HSTL 357MHz C 512K x 36 GS8150V36AGB-333 Pb-Free Register-Register Late Write SRAM HSTL 333 MHz C 512K x 36 GS8150V36AGB-300 Pb-Free Register-Register Late Write SRAM HSTL 300 MHz C 512K x 36 GS8150V36AGB-250 Pb-Free Register-Register Late Write SRAM HSTL 250 MHz C 1M x 18 GS8150V18AGB-357I Pb-Free Register-Register Late Write SRAM HSTL 357 MHz I 1M x 18 GS8150V18AGB-333I Pb-Free Register-Register Late Write SRAM HSTL 333 MHz I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8150V36AB-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.04 4/2005 23/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 Ordering Information Org Part Number Type I/O Speed (MHz) TA 1M x 18 GS8150V18AGB-300I Pb-Free Register-Register Late Write SRAM HSTL 300 MHz I 1M x 18 GS8150V18AGB-250I Pb-Free Register-Register Late Write SRAM HSTL 250 MHz I 512K x 36 GS8150V36AGB-357I Pb-Free Register-Register Late Write SRAM HSTL 357 MHz I 512K x 36 GS8150V36AGB-333I Pb-Free Register-Register Late Write SRAM HSTL 333 MHz I 512K x 36 GS8150V36AGB-300I Pb-Free Register-Register Late Write SRAM HSTL 300 MHz I 512K x 36 GS8150V36AGB-250I Pb-Free Register-Register Late Write SRAM HSTL 250 MHz I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8150V36AB-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.04 4/2005 24/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Product Preview GS8150V18/36AB-357/333/300/250 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet 8150VxxA_r1 8150VxxA_r1; 8150VxxA_r1_01 Content/Format • Corrected L3 from VSS to NC • Updated entire format • Placed corrected BGA diagram in document 8150VxxA_r1_01; 8150VxxA_r1_02 Content/Format • Updated format • Added variation information to 119 BGA mechanical drawing 8150VxxA_r1_02; 8150VxxA_r1_03 Content 8150VxxA_r1_03; 8150VxxA_r1_04 Content Rev: 1.04 4/2005 • Updated AC Characteristics table • Updated /G Controlled Read-Write timing diagram • Pb-Free information added 25/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology