Preliminary GS8162V72CC-333/300/250/200/150 209-Bump BGA Commercial Temp Industrial Temp 333 MHz–150 MHz 1.8 V VDD 1.8 V I/O 256K x 72 18Mb S/DCD Sync Burst SRAMs Features Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 1.8 V +10%/–10% core power supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 209-bump BGA package • Pb-Free 209-bump BGA package available SCD and DCD Pipelined Reads The GS8162V72CC is an SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Functional Description Applications The GS8162V72CC is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS8162V72CC operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.01 2/2005 -333 -300 -250 -200 -150 Unit tKQ tCycle 2.8 3.0 2.8 3.3 3.0 4.0 3.0 5.0 3.8 6.7 ns ns Curr 545 495 425 345 270 mA tKQ tCycle 4.5 4.5 5.0 5.0 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr 380 345 315 275 250 mA 1/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 GS8162V72C Pad Out—209-Bump BGA—Top View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB B DQG DQG BC BG NC B A BB BF DQB DQB C DQG DQG BH BD NC E1 NC BE BA DQB DQB D DQG DQG VSS NC NC G GW NC VSS DQB DQB E DQPG DQPC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPF DQPB F DQC DQC VSS VSS VSS ZQ VSS VSS VSS DQF DQF G DQC DQC VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF DQF H DQC DQC VSS VSS VSS MCL VSS VSS VSS DQF DQF J DQC DQC VDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQF DQF K NC NC CK NC VSS MCL VSS NC NC NC NC L DQH DQH VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA DQA M DQH DQH VSS VSS VSS MCL VSS VSS VSS DQA DQA N DQH DQH VDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQA DQA P DQH DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA R DQPD DQPH VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA DQPE T DQD DQD VSS NC NC LBO NC NC VSS DQE DQE U DQD DQD NC A A A A A NC DQE DQE V DQD DQD A A A A1 A A A DQE DQE W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE Rev 10 Rev: 1.01 2/2005 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch 2/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 GS8162V72C BGA Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs. A I Address Inputs DQA DQB DQC DQD DQE DQF DQG DQH I/O Data Input and Output pins BA, BB, BC,BD, BE, BF, BG,BH I Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low NC — No Connect CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E1, E3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control MCH I Must Connect High Must Connect Low MCL BW I Byte Enable; active low ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply BPR1999.05.18 Rev: 1.01 2/2005 3/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 GS8162V72C Block Diagram Register A0–An D Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q 36 36 Register D Q BB 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D 36 Q 36 Register D E1 E3 E2 Q 36 Register D Q FT G ZZ 36 Power Down SCD DQx1–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.01 2/2005 4/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Power Down Control ZZ Single/Dual Cycle Deselect Control SCD FLXDrive Output Impedance Control ZQ State Function L Linear Burst H Interleaved Burst L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L High Drive (Low Impedance) H or NC Low Drive (High Impedance) Note: There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.01 2/2005 5/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x36 version. Rev: 1.01 2/2005 6/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 E2 ADSP ADSC ADV W3 DQ4 Deselect Cycle, Power Down None X H X X L X X High-Z Read Cycle, Begin Burst External R L F L X X X Q Read Cycle, Begin Burst External R L F H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X T H H L F Q Read Cycle, Continue Burst Next CR H T X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.01 2/2005 7/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.01 2/2005 8/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.01 2/2005 9/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 3.6 V VDDQ Voltage in VDDQ Pins –0.5 to 3.6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 3.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 3.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 oC TBIAS Temperature Under Bias –55 to 125 oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 1.8 V Supply Voltage VDD 1.6 1.8 2.0 V 1.8 V VDDQ I/O Supply Voltage VDDQ 1.6 1.8 2.0 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.01 2/2005 10/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Rev: 1.01 2/2005 11/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 30pF* 50Ω VDDQ/2 * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 100 uA Input Current IIN2 VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH1 IOH = –4 mA, VDDQ = 1.6 V VDDQ – 0.4 V — Output Low Voltage VOL1 IOL = 4 mA, VDD = 1.6 V — 0.4 V Rev: 1.01 2/2005 12/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Operating Currents -333 Parameter Test Conditions Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open (x72) Standby Current ZZ ≥ VDD – 0.2 V — Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL — -300 -250 -200 -150 Symbol 0 to 70°C –40 to 85°C 0 to °C –40 to 85°C 0 to 70°C –40 to 85°C 0 to °C –40 to 85°C 0 to 70°C –40 to 85°C Pipeline IDD IDDQ 460 85 470 85 415 80 425 80 350 75 360 75 290 55 300 55 230 40 240 40 mA Flow Through IDD IDDQ 320 60 330 60 290 55 300 55 265 50 275 50 230 45 240 45 210 40 220 40 mA Pipeline ISB 40 50 40 50 40 50 40 50 40 50 mA Flow Through ISB 40 50 40 50 40 50 40 50 40 50 mA Pipeline IDD 85 90 85 90 85 90 85 90 85 90 mA Flow Through IDD 60 65 60 65 60 65 50 55 50 55 mA Mode Unit Notes: 1. IDD and IDDQ apply to any combination of VDD and VDDQ operation. 2. All parameters listed are worst case scenario. Rev: 1.01 2/2005 13/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time tKC -333 -300 -250 -200 -150 Unit Min Max Min Max Min Max Min Max Min Max 3.0 — 3.3 — 4.0 — 5.0 — 6.7 — ns Clock to Output Valid tKQ — 2.8 — 2.8 — 3.0 — 3.0 — 3.8 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 1 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ Setup time tS 1.0 — 1.0 — 1.2 — 1.5 — 1.5 — ns Hold time tH 0.1 — 0.1 — 0.2 — 0.4 — 0.5 — ns Clock Cycle Time tKC 4.5 — 5.0 — 5.5 — 6.5 — 7.5 — ns Clock to Output Valid tKQ — 4.5 — 5.0 — 5.5 — 6.5 — 7.5 ns Clock to Output Invalid tKQX 2.0 — 2.0 — 2.0 — — 6.5 — 7.5 ns Clock to Output in Low-Z tLZ1 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns Setup time tS 1.3 — 1.4 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.3 — 0.4 — 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.0 — 1.0 — 1.3 — 1.3 — 1.5 — ns Clock LOW Time tKL 1.2 — 1.2 — 1.5 — 1.5 — 1.7 — ns Clock to Output in High-Z tHZ1 1.5 2.8 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 ns G to Output Valid tOE — 2.8 — 2.8 — 3.0 — 3.0 — 3.8 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.8 — 2.8 — 3.0 — 3.0 — 3.8 ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.01 2/2005 14/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Pipeline Mode Timing (SCD) Begin Read A Cont Cont Single Read Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC Deselect Burst Read CK ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An A B C tS GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH E3 G tS tOE DQa–DQd Rev: 1.01 2/2005 tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) 15/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+1) Q(C+2) Q(C+3) © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Flow Through Mode Timing (SCD) Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKH tKC CK ADSP Fixed High tS tH tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An A B C tS tH GW tS tH BW tS tH Ba–Bd tS Deselected with E1 tH E1 tS tH E2 and E3 only sampled with ADSC E2 tS tH E3 G tH tS tOE DQa–DQd Rev: 1.01 2/2005 tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) 16/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+3) Q(C) © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Pipeline Mode Timing (DCD) Begin Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect Deselect tKL tKH tKC CK ADSP tS ADSC initiated read tH ADSC tS tH ADV tS tH Ao–An A B C tS GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 tS E2 and E3 only sampled with ADSC tH E2 tS tH E3 G tS tOE DQa–DQd Hi-Z Rev: 1.01 2/2005 tOHZ Q(A) tKQ tH D(B) tHZ tLZ tKQX Q(C) Q(C+1) 17/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+2) Q(C+3) © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Flow Through Mode Timing (DCD) Begin Read A Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C Deselect tKL tKH tKC CK ADSP Fixed High tS tH tS tH ADSC initiated read ADSC tH tS tS tH ADV tS tH Ao–An A B C tS tH GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH E1 masks ADSP E3 G tH tS tOE tKQ DQa–DQd Rev: 1.01 2/2005 tOHZ Q(A) tKQX tHZ tLZ D(B) Q(C) Q(C+1) Q(C+2) 18/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+3) Q(C) © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing tKH tKC tKL CK Setup Hold ADSP ADSC tZZR tZZS tZZH ZZ Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.01 2/2005 19/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Port Registers JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the Rev: 1.01 2/2005 20/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram · · · · · · Boundary Scan Register · · 0 Bypass Register 0 108 · 1 · · 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · · · 2 1 0 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.01 2/2005 21/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Die Revision Code GSI Technology JEDEC Vendor ID Code I/O Configuration Not Used Presence Register Tap Controller Instruction Set ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.01 2/2005 22/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 1 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 1.01 2/2005 23/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. JTAG TAP Instruction Set Summary Instruction Code Description EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.01 2/2005 24/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Notes 1 © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 JTAG Port AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 JTAG Port AC Test Load DQ 30pF* 50Ω VDDQ/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes 1.8 V Test Port Input High Voltage VIHJ 0.6 * VDD VDD +0.3 V 1 1.8 V Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V 1 TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3 TDO Output Leakage Current IOLJ –1 1 uA 4 Test Port Output High Voltage VOHJ 1.7 — V 5, 6 Test Port Output Low Voltage VOLJ — 0.4 V 5, 7 Test Port Output CMOS High VOHJC VDDQ – 100 mV — V 5, 8 VOLJC — 100 mV V 5, 9 Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA Test Port Output CMOS Low Rev: 1.01 2/2005 25/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: [email protected]. Rev: 1.01 2/2005 26/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 209 BGA Package Drawing (Package C) 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array C A1 A Side View D aaa D1 ∅b E E1 e Bottom View e Symbol Min Typ Max Units Symbol Min Typ Max Units A — — 1.70 mm D1 — 18.0 (BSC) — mm A1 0.40 0.50 0.60 mm E 13.9 14.0 14.1 mm ∅b 0.50 0.60 0.70 mm E1 — 10.0 (BSC) — mm c 0.31 0.36 0.38 mm e — 1.00 (BSC) — mm D 21.9 22.0 22.1 mm aaa — 0.15 — mm Rev 1.0 Rev: 1.01 2/2005 27/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 256K x 72 GS8162V72CC-333 Pipeline/Flow Through 209 BGA 333/4.5 C 256K x 72 GS8162V72CC-300 Pipeline/Flow Through 209 BGA 300/5 C 256K x 72 GS8162V72CC-250 Pipeline/Flow Through 209 BGA 250/5.5 C 256K x 72 GS8162V72CC-200 Pipeline/Flow Through 209 BGA 200/6.5 C 256K x 72 GS8162V72CC-150 Pipeline/Flow Through 209 BGA 150/7.5 C 256K x 72 GS8162V72CC-333I Pipeline/Flow Through 209 BGA 333/4.5 I 256K x 72 GS8162V72CC-30I Pipeline/Flow Through 209 BGA 300/5 I 256K x 72 GS8162V72CC-250I Pipeline/Flow Through 209 BGA 250/5.5 I 256K x 72 GS8162V72CC-200I Pipeline/Flow Through 209 BGA 200/6.5 I 256K x 72 GS8162V72CC-150I Pipeline/Flow Through 209 BGA 150/7.5 I 256K x 72 GS8162V72CGC-333 Pipeline/Flow Through Pb-Free 209 BGA 333/4.5 C 256K x 72 GS8162V72CGC-300 Pipeline/Flow Through Pb-Free 209 BGA 300/5 C 256K x 72 GS8162V72CGC-250 Pipeline/Flow Through Pb-Free 209 BGA 250/5.5 C 256K x 72 GS8162V72CGC-200 Pipeline/Flow Through Pb-Free 209 BGA 200/6.5 C 256K x 72 GS8162V72CGC-150 Pipeline/Flow Through Pb-Free 209 BGA 150/7.5 C 256K x 72 GS8162V72CGC-333I Pipeline/Flow Through Pb-Free 209 BGA 333/4.5 I 256K x 72 GS8162V72CGC-30I Pipeline/Flow Through Pb-Free 209 BGA 300/5 I 256K x 72 GS8162V72CGC-250I Pipeline/Flow Through Pb-Free 209 BGA 250/5.5 I 256K x 72 GS8162V72CGC-200I Pipeline/Flow Through Pb-Free 209 BGA 200/6.5 I 256K x 72 GS8162V72CGC-150I Pipeline/Flow Through Pb-Free 209 BGA 150/7.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162V36CC-250IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.01 2/2005 28/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology Preliminary GS8162V72CC-333/300/250/200/150 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content • Creation of new datasheet 8162VxxC_r1 8162VxxC_r1; 8162VxxC_r1_01 Rev: 1.01 2/2005 Page;Revisions;Reason Content • Added 200 & 150 MHz speed bins • Corrected block diagram (added references to E2 & E3) • Corrected truth table (addded references to E2 & E3) • Added Pb-free information 29/29 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology