Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Description The M32170 and M32174 Group are 32-bit single chip RISC 64-channel multijunction timers (MJT) Multifunction timers are incorporated that support various microcomputers designed for use in general industrial and household equipment. purposes of use. 16-bit output related timers ....................................... 35ch These microcomputers contains a variety of peripheral functions ranging from16-channel A-D converters to 64chan- 16-bit input/output related timers .............................. 10ch 16-bit input related timers ......................................... 11ch nel multifunction timers, 10-channel DMAs, 6-channel serial I/Os, 1-channel real time debugger, 1-channel Full-CAN, and 32-bit input related timers .......................................... 8ch • Flexible configuration is possible through interconnection JTAG (boundary scan facility). With lower power consumption and low noise characteristics of timers. • The internal DMAC and A-D converter can be started by a also considered, these microcomputers are ideal for embed- timer. ded equipment applications. Real-time Debugger Features • Includes dedicated clock-synchronized serial I/O that can read and write the contents of the internal RAM independently M32R RISC CPU core • Uses the M32R family RISC CPU core (Instruction set common to all microcomputers in the M32R family) of the CPU. • Can look up and update the data table in real time while the • Five-stage pipelined processing • Sixteen 32-bit general-purpose registers program is running. • Can generate a dedicated interrupt based on RTD commu- • 16-bit/32-bit instructions implemented • DSP function instructions (sum-of-products calculation nication. using 56-bit accumulator) • Built-in flash memory Abundant internal peripheral functions • Built-in flash programming boot program • Built-in RAM computer contains the following peripheral functions. • DMAC .............................................................. 10 channels • PLL clock generating circuit ........... Built-in × 4 PLL circuit • Maximum operating frequency of the CPU clock • Two independent A-D converter .............. (10-bit converter × 16 channels) × 2 In addition to the timers and real-time debugger, the micro- 40MHz(when operating at -40 to +85oC) 32MHz(when operating at -40 to +125oC) Table 1 32170 Group Name List by type • Serial I/O ............................................................ 6 channels • Interrupt controller ........... 31 interrupt sources, 8 priority levels • Wait controller • Full CAN .............................................................. 1 channel Type Name RAM Size ROM Size Package M32170F6VFP 40K bytes 768K bytes 240QFP M32170F4VFP 32K bytes 512K bytes 240QFP Designed to operate at high temperatures M32170F3VFP 32K bytes 384K bytes 240QFP M32170F6VWG 40K bytes 768K bytes 255FBGA To meet the need for use at high temperatures, the microcomputer is designed to be able to operate in the temperature M32170F4VWG 32K bytes 512K bytes 255FBGA M32170F3VWG 32K bytes 384K bytes 255FBGA • JTAG (boundary scan function) range of -40 to +125oC when CPU clock operating frequency = 32 MHz. When CPU clock operating frequency = 40 MHz, the microcomputer can be used in the temperature Note: 255FBGA is currently under development. range of -40 to +85oC. Note: This does not guarantee continuous operation at Table 2 32170 Group Name List by type Type Name RAM Size ROM Size Package M32174F4VFP 40K bytes 512K bytes 240QFP M32174F3VFP 40K bytes 384K bytes 240QFP M32174F4VWG 40K bytes 512K bytes 255FBGA M32174F3VWG 40K bytes 384K bytes 255FBGA Note: 255FBGA is currently under development. 125oC. If you are considering use of the microcom puter at 125oC, please consult Mitsubishi. Applications Automobile equipment control (e.g., Engine, ABS, AT), industrial equipment system control, and high-function OA equipment (e.g., PPC) Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 P217/TO44 P216/TO43 P215/TO42 P214/TO41 P213/TO40 P212/TO39 P211/TO38 P210/TO37 VSS VCCI VDD P102/TO10 P101/TO9 P100/TO8 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 VSS VCCE FP MOD1 MOD0 RESET P97/TO20 P96/TO19 P95/TO18 P94/TO17 P93/TO16 P77/RTDCLK P76/RTDACK P75/RTDRXD P74/RTDTXD P73/ HACK P72/ HREQ P71/WAIT P70/BCLK/WR VCCE VSS VCCI P67/ADTRG P66/SCLKI5/SCLKO5 P65/SCLKI4/SCLKO4 P64/SBI P63 P62 P61 VSS FVCC VSS VCCI P203/RXD5 P202/TXD5 P201/RXD4 P200/TXD4 P87/SCLKI1/SCLKO1 Pin Assignment(top view) 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 M32170F3VFP M32170F4VFP M32170F6VFP M32174F3VFP M32174F4VFP AD1IN12 AD1IN13 AD1IN14 AD1IN15 AVSS1 P43/RD P44/CS0 P45/CS1 P46/A13 P47/A14 P220/CTX P221/CRX P222 P223 (Note) P224/A11 (Note) P225/A12 VSS OSC-VSS XIN XOUT OSC-VCC VSS VCNT VSS P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 P20/A23 P21/A24 P22/A25 P23/A26 VCCE VSS P24/A27 P25/A28 P26/A29 P27/A30 P00/DB0 P01/DB1 P02/DB2 P03/DB3 P04/DB4 P05/DB5 P06/DB6 P07/DB7 VCCE VSS P10/DB8 P11/DB9 P12/DB10 P13/DB11 P14/DB12 P15/DB13 P16/DB14 P17/DB15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 JTMS JTCK JTRST JTDO JTDI P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 P124/TCLK0 P125/TCLK1 P126/TCLK2 P127/TCLK3 VCCI VSS P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 VCCE VSS P140/TIN8 P141/TIN9 P142/TIN10 P143/TIN11 P144/TIN12 P145/TIN13 P146/TIN14 P147/TIN15 P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P41/BLW/BLE P42/BHW/BHE VCCI VSS VREF1 AVCC1 AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 AD1IN8 AD1IN9 AD1IN10 AD1IN11 Package 240P6Y-A Note: Use caution when using these pins because they nave a debug event function. Figure 1 Pin Layout Diagram of the 240QFP 2 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P86/RXD1 P85/TXD1 P84/SCLKI0/SCLKO0 P83/RXD0 P82/TXD0 VSS VCCE P177/RXD3 P176/TXD3 P175/RXD2 P174/TXD2 P173/TIN25 P172/TIN24 P167/TO28 P166/TO27 P165/TO26 P164/TO25 P163/TO24 P162/TO23 P161/TO22 P160/TO21 VSS VCCI P197/TIN33 P196/TIN32 P195/TIN31 P194/TIN30 P193/TIN29 P192/TIN28 P191/TIN27 P190/TIN26 P187/TO36 P186/TO35 P185/TO34 P184/TO33 P183/TO32 P182/TO31 P181/TO30 P180/TO29 VSS VCCE AVSS0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AVCC0 VREF0 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Pin Assignment(top view) 20 JTMS P216 /TO43 P214 /TO41 P210 /TO37 P102 /TO10 P116 TRDATA /TO6 6 P112 /TO2 VCCE RESET P96 P77/ P73 /TO19 RTDCLK /HACK VCCE P66 /SCLK5 P62 VSS P202 /TXD5 19 JTCK P217 /TO44 P215 /TO42 P211 /TO38 VDD P117 TRDATA /TO7 7 P113 /TO3 VSS MOD0 P95 P76/ P72 /TO18 RTDACK /HREQ VSS P65 /SCLK4 P61 VCCI P200 /TXD4 18 JEVENT 0 JDBI P213 /TO40 P212 /TO39 VCCI P100 /TO8 P110 /TO0 MOD1 P94 P75/ P71 /TO17 RTDRXD /WAIT VCCI P64 /SBI VSS P203 /RXD5 P87 TRDATA TRDATA 2 0 /SCLK1 17 JEVENT JTRST 1 JTDO VSS P101 /TO9 P115 /TO5 FP P97 /TO20 P70 P93 P74/ P67 /TO16 RTDTXD /BCLK /ADTRG P63 FVCC P83 /RXD0 P84 /SCLK0 P86 /RXD1 P85 /TXD1 P114 TRDATA /TO4 4 TRDATA 5 P111 /TO1 P201 TRDATA /RXD4 3 N.C TRDATA 1 16 P104 /TO12 P103 /TO11 P105 /TO13 JTDI P177 /RXD3 VCCE P82 /TXD0 VSS 15 P124 /TCLK0 P107 /TO15 P125 /TCLK1 P106 /TO14 P173 /TIN25 P174 /TXD2 P176 /TXD3 P175 /RXD2 14 VCCI P127 /TCLK3 VSS P126 /TCLK2 P165 /TO26 P166 /TO27 P172 /TIN24 P167 /TO28 13 P132 /TIN18 P131 /TIN17 P133 /TIN19 P130 /TIN16 P161 /TO22 P162 /TO23 P164 /TO25 P163 /TO24 12 P136 /TIN22 P135 /TIN21 P137 /TIN23 P134 /TIN20 P197 /TIN33 VCCI P160 /TO21 VSS 11 P140 /TIN8 VSS P141 /TIN9 VCCE P193 /TIN29 P194 /TIN30 P196 /TIN32 P195 /TIN31 10 P144 /TIN12 P145 /TIN13 P143 /TIN11 P142 /TIN10 P187 /TO36 P192 /TIN28 P190 /TIN26 P191 /TIN27 9 P150 /TIN0 P151 /TIN1 P147 /TIN15 P146 /TIN14 P183 /TO32 P186 /TO35 P184 /TO33 P185 /TO34 8 P154 /TIN4 P155 /TIN5 P153 /TIN3 P152 /TIN2 VSS P182 /TO31 P180 /TO29 P181 /TO30 7 P41 /BLW P42 /BHW P157 /TIN7 P156 /TIN6 AD0IN14 VCCE AD0IN15 AVSS0 6 VREF1 AVCC1 VSS VCCI AD0IN10 AD0IN13 AD0IN11 AD0IN12 5 AD1IN2 AD1IN3 AD1IN1 AD1IN0 4 AD1IN6 AD1IN7 AD1IN5 AD1IN15 P45 /CS1 P221 /CRX P225 /A12 XOUT VSS P33 /A18 TRSYNC P21 /A24 VSS P27 /A30 P03 /DB3 P07 /DB7 P11 /DB9 AD0IN5 AD0IN3 AD0IN4 3 AD1IN8 AD1IN10 AD1IN4 AVSS1 P46 /A13 P222 VSS OSCVCC P30 /A15 P34 /A19 P20 /A23 VCCE P26 /A29 P02 /DB2 P06 /DB6 P10 /DB8 P14 /DB12 AD0IN1 AD0IN0 AD0IN2 2 AD1IN9 AD1IN11 AD1IN13 P43 /RD P47 /A14 P223 OSCVSS VSS P31 /A16 P35 /A20 P37 /A22 P23 /A26 P25 /A28 P01 /DB1 P05 /DB5 VSS P13 /DB11 P17 /DB15 VREF0 AVCC0 1 AD1IN12 AD1IN14 P44 /CS0 P220 /CTX P224 /A11 XIN VCNT P32 /A17 TRCLK P36 /A21 P22 /A25 P24 /A27 P00 /DB0 P04 /DB4 VCCE P12 /DB10 P15 /DB13 P16 /DB14 N.C D E G H J K L M N P R T U V W Y A B C M32170F3VWG M32170F4VWG M32170F6VWG M32174F3VWG M32174F4VWG AD0IN6 AD0IN9 AD0IN7 AD0IN8 F Package 255FBGA Note 1: NC pin (W19, Y1) shows non-connect. Be open state. Note 2: Use caution when using P224/A11 and P225/A12 because they have a debug event function. Note 3: 255FBGA is currently under development. Figure 2 Pin Layout Diagram of the 255FBGA 3 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 32170/32174 Internal bus interface M32R CPU core (max 40MHz) DMAC (10 channels) Multiplieraccumulator (32 × 16 + 56) Internal RAM ( M32170F6 : 40KB ) ( M32170F4 : 32KB ) ( M32170F3 : 32KB ) ( M32174F4 : 40KB ) ( M32174F3 : 40KB ) Internal 16-bit bus Internal flash memory ( M32170F6 : 768KB ) ( M32170F4 : 512KB ) ( M32170F3 : 384KB ) ( M32174F4 : 512KB ) ( M32174F3 : 384KB ) Internal 32-bit bus Multijunction timer (MJT : 64 channels) A-D converter (10-bit, 16 channels) × 2 Serial I/O (6 channels) Interrupt controller (31 sources, 8 levels) Wait controller Full CAN (1 channel) Real-time debugger (RTD) PLL clock generation circuit External bus interface Address Data Input/output port(JTAG) 157 lines Figure 3 Block diagram 4 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 3 Outline Performance (1/2) Functional Block Features M32R CPU core M32R family CPU core, internally configured in 32 bits Built-in multiplier-accumulator (32 × 16 + 56) Basic bus cycle : 25 ns (Internal CPU clock frequency at 40 MHz, Internal peripheral clock frequency at 20 MHz) Logical address space : 4G bytes, linear General-purpose register : 32-bit register × 16, Control register: 32-bit register × 5 accumulator : 56 bits External data bus 16 bits data bus Instruction set 16-bit/32-bit instruction formats 83 instructions/ 9 addressing modes Internal flash memory M32170F6 : 768K bytes M32170F4, M32174F4 : 512K bytes M32170F3, M32174F3 : 384K bytes Rewrite durability : 100 times Internal RAM M32170F6, M32174F4, M32174F3 : 40K bytes M32170F4, M32170F3 : 32K bytes DMAC 10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral I/O and internal RAM, and between internal RAMs) Channels can be cascaded and can operate in combination with internal peripheral I/O Multijunction timer 64 channels of multijunction timers. • 16-bit output-related timers × 35 channels (single-shot, delayed single-shot, PWM, single-shot PWM) • 16-bit input/output-related timers × 10 channels (event count mode, single-shot, PWM, measurement) • 16-bit input-related timers × 11 channels (measurement, event count mode, multiply-by-4 count 3 channels) • 32-bit input-related timers × 8 channels (measurement) Flexible timer configuration is possible through interconnection of channels using the event bus. A-D converter 2 independent 10-bit multifunction A-D converters • Input 16 channels × 2 • Scan-based conversion can be switched with 4, 8, and 16 • Capable of interrupt conversion during scan • 8-bit/10-bit readout function available Serial I/O 6 channels (The serial I/Os can be set for synchronous serial I/O or UART. SIO2,3 are UART mode only) Real-time debugger (RTD) 1-channels dedicated clock-synchronized serial The entire internal RAM can be read or rewritten from the outside without CPU intervention. Interrupt controller Controls interrupts from internal peripheral I/Os (Priority can be set to one of 8 levels including interrupt disabled) Wait controller Controls wait when accessing external extended area (1 to 4 wait cycles inserted + prolonged by external WAIT signal input) CAN 16-channels message slots JTAG Boundary-Scan function 5 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 4 Outline Performance (2/2) Function Block Features Clock Maximum internal CPU memory clock : 40MHz (access to CPU, internal ROM, and internal RAM) Maximum internal peripheral clock : 20MHz (access to internal peripheral module) Maximum external input clock : 10.0MHz, Built-in multiply-by-4 PLL circuit Power Supply Voltage External I/O : 5V (±0.5V) or 3.3V (±0.3V) Internal logic : 3.3V (±0.3V) Operating temperature rang -40 to +125°C(Internal CPU memory clock 32MHz, internal peripheral clock 16MHz) -40 to +85°C(Internal CPU memory clock 40MHz, internal peripheral clock 20MHz) Package 0.5mm pitches / 240-pin plastic QFP, 0.8mm pitches / 255-pin FBGA (Note) Note: 255-pin FBGA is currently under development. 6 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Outline of the CPU core Three operation modes The M32170 and M32174 Group uses the M32R RISC CPU The M32170 and M32174 Group has three operation modes: core, and has an instruction set which is common to all micro- single-chip mode, external extended mode, and processor computers in the M32R family. mode. These operation modes are changed from one to an- Instructions are processed in five pipelined stages consisting other by setting the MOD0 and MOD1 pins. of instruction fetch, decode, execution, memory access, and write back. Thanks to its “out-of-order-completion” mechanism, Address space the M32R CPU allows for clock cycle efficient, instruction ex- The M32170 and M32174 Group’s logical addresses are al- ecution control. ways handled in 32 bits, providing 4 Gbytes of linear address The M32R CPU internally has sixteen 32-bit general-purpose space. The M32170 and M32174 Group’s address space registers. The instruction set consists of 83 discrete instruc- consists of the following. tions, which come in either a 16-bit instruction or a 32-bit instruction format. Use of the 16-bit instruction format helps to User space reduce the code size of a program. Also, the availability of 32- A 2-Gbyte area from H’0000 0000 to H’7FFF FFFF is the user bit instructions facilitates programming and increases the per- space. Located in this space are the user ROM area, external formance at the same clock speed, as compared to extended area, internal RAM area, and SFR (Special Function architectures with segmented address spaces. Register) area (internal peripheral I/O registers). Of these, the user ROM area and external extended area are located differ- Sum-of-products instructions comparable to DSP ently depending on mode settings. The M32R CPU contains a multiplier/accumulator that can execute 32 bits × 16 bits in one cycle. Therefore, it executes a Boot program space 32 bit × 32 bit integer multiplication instruction in three cycles. A 1-Gbyte area from H’8000 0000 to H’BFFF FFFF is the boot Also, the M32R CPU supports the following four sum-of-prod- program area. This space contains the on-board programming ucts instructions (or multiplication instructions) for DSP func- program (boot program) used in blank state by the internal flash tion use. memory. (1) 16 high-order register bits × 16 high-order register bits (2) 16 low-order register bits × 16 low-order register bits (3) All 32 register bits × 16 high-order register bits (4) All 32 register bits × 16 low-order register bits System space A 1-Gbyte area from H’C000 0000 to H’FFFF FFFF is the system area. This space is reserved for use by development Furthermore, the M32R CPU has instructions for rounding the tools such as an in-circuit emulator and debug monitor, and value stored in the accumulator to 16 or 32 bits, and instruc- cannot be used by the user. tions for shifting the accumulator value to adjust digits before storing in a register. Because these instructions also can be executed in one cycle, DSP comparable data processing capability can be obtained by using them in combination with high-speed data transfer instructions such as Load & Address Update or Store & Address Update. Built-in clock multiplier circuit The clock multiplier circuit multiplies the frequency of the input clock signal by 4 to produce the internal operating clock. When the maximum CPU memory clock frequency = 40 MHz, the input clock frequency is 10.0 MHz. 7 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER OSC-VSS P70/BCLK/WR Mode Port 22 CAN MOD0 MOD1 FP P220/CTX P221/CRX P190-P197/TIN26-TIN33 P172, P173/TIN24, TIN25 P150-P157/TIN0-TIN7 P140-P147/TIN8-TIN15 P130-P137/TIN16-TIN23 Port 19 Port 17 Port 15 Port 14 Port 13 Port 12 RESET Multijunction timer P124-P127/ TCLK0-TCLK 3 34 4 45 P210-P217/TO37-TO44 P180-P187/TO29-TO36 P160-P167/TO21-TO28 P110-P117/TO0-TO7 P100-P107/TO8-TO15 P93-P97/TO16-TO20 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 5V Reset 16 AD0IN0-AD0IN15 AD1IN0-AD1IN15 A-D converter P67/ADTRG AVCC0, AVCC1 AVSS0, AVSS1 AVREF0, AVREF1 Port 6 Port 22 Port 6 Interrupt controller 2 2 2 3 P61-P63 P222, P223 6 VCCI P224/A11 (Note 2) P225/A12 (Note 2) 20 P20-P27/A23-A30 P30-P37/A15-A22 P46, P47/A13, A14 P00-P07/DB0-DB7 P10-P17/DB8-DB15 Port 22 Port 2 Port 3 Port 4 Data bus Port 0 Port 1 Serial I/O Port 6 Port 8 Port 17 Port 20 Real-time debugger Port 7 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTMS JTCK JTRST JTDO JTDI VDD FVCC 3.3V : Operates with a 3.3V power supply. 5V : Operates with a 3.3V or 5V power supply. Note 2: Use caution when using this port because it has a debug event function. 8 Address bus 16 16 Figure 4 Pin Function Diagram of 240QFP Port 7 P73/HACK VSS Note 1: Bus control P72/HREQ 7 VCCE Port 4 P71/WAIT P64/SBI 3.3V Port 6 16 P41/BLW/BLE 3.3V Port 7 P43/RD P42/BHW/BHE 5V OSC-VCC P44/CS0 M32170F6VFP , M32170F4VFP , M32170F3VFP , M32174F4VFP , M32174F3VFP Clock P45/CS1 3.3V (Note 1) XIN XOUT VCNT JTAG Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER OSC-VSS P70/BCLK/WR Mode Port 22 CAN MOD0 MOD1 FP P220/CTX P221/CRX P190-P197/TIN26-TIN33 P172, P173/TIN24, TIN25 P150-P157/TIN0-TIN7 P140-P147/TIN8-TIN15 P130-P137/TIN16-TIN23 Port 19 Port 17 Port 15 Port 14 Port 13 Port 12 RESET Multijunction timer P124-P127/ TCLK0-TCLK 3 34 4 45 P210-P217/TO37-TO44 P180-P187/TO29-TO36 P160-P167/TO21-TO28 P110-P117/TO0-TO7 P100-P107/TO8-TO15 P93-P97/TO16-TO20 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 5V Reset 16 AD0IN0-AD0IN15 AD1IN0-AD1IN15 A-D converter P67/ADTRG AVCC0, AVCC1 AVSS0, AVSS1 AVREF0, AVREF1 Port 6 Port 22 Port 6 2 2 2 3 P61-P63 P222, P223 Interrupt controller P64/SBI DEBUG TRCLK TRSYNC TRDATA JDBI JEVENTO JEVENT1 P72/HREQ Port 7 P73/HACK P224/A11 (Note 2) P225/A12 (Note 2) 20 P20-P27/A23-A30 P30-P37/A15-A22 P46, P47/A13, A14 Address bus Port 22 Port 2 Port 3 Port 4 Data bus Port 0 Port 1 Serial I/O Port 6 Port 8 Port 17 Port 20 16 P00-P07/DB0-DB7 P10-P17/DB8-DB15 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P74/RTDTXD P75/RTDRXD P76/RTDACK Real-time debugger Port 7 P77/RTDCLK JTMS JTCK JTRST JTDO JTDI 8 JTAG 7 VCCE 6 VCCI 3.3V Port 6 16 P41/BLW/BLE Port 4 Bus control P71/WAIT 3.3V Port 7 P43/RD P42/BHW/BHE 5V OSC-VCC P44/CS0 M32170F6VWG , M32170F4VWG , M32170F3VWG , M32174F4VWG , M32174F3VWG Clock P45/CS1 3.3V (Note 1) XIN XOUT VCNT VDD FVCC 16 VSS Note 1: 3.3V 5V : Operates with a 3.3V power supply. : Operates with a 3.3V or 5V power supply. Note 2: Use caution when using this port because it has a debug event function. Note 3: 255FBGA is currently under development. Figure 5 Pin Function Diagram of 255FBGA 9 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 5 Description of Pin Function (1/5 ) Type Pin Name Description Input/Output Function Power VCCE Power supply — Supplies power (5 V or 3.3V) to external I/O ports. supply VCCI Power supply — Supplies power (3.3 V) to the internal logic. VDD RAM power supply — nternal RAM backup power supply (3.3 V). FVCC Flash power supply — Internal flash memory backup power supply (3.3 V). VSS Ground — Connect all VSS pins to ground (GND). XIN, Clock Input Clock input/output pins. These pins contain a PLL-based Output frequency multiply-by-4, so input the clock whose frequency is quarter Clock XOUT the operating frequency. (XIN input = 10 MHz when CPU clock operates at 40 MHz) BCLK / System clock Output When this signal is System Clock(BCLK), it outputs a clock whose is twice that of ______ WR external inpout clock. (BCLK output = 20 MHz when CPU clock operates at 40 MHz). Use this clock when circuits are synchronized externally. ______ When this signal is Write(WR),during external write access it indicates the valid data on the data bus to transfer. Reset Mode OSC-VCC Power supply — Power supply to the PLL circuit. Connect OSC-VCC to the power supply(3.3V) OSC-VSS Ground — Connect OSC-VSS to ground. VCNT ______ RESET PLL control Input This pin controls the PLL circuit. Connect a resistor and capacitor to this pin. Reset Input This pin resets the internal circuits. MOD0 Mode Input These pins set an operation mode. MOD1 MOD0 0 MOD1 0 0 Single-chip mode 0 1 Expanded external mode 1 0 Processor mode 0 (Boot mode) (Note) 1 Address bus A11-A30 Address bus Output Mode 1 (Reserved) 20 lines of address bus (A11-A30) are provided to accommodate two channels of 2 MB memory space (max.) connected external to the chip. A31 is not output. In the write cycle, of the 16-bit data bus the valid byte positions to write are _________ ________ ________ _______ output as BHW/ BHE and BLW/ BLE. In read cycle, data on the entire 16-bit data bus is read. However, only the data at the valid byte positions are transferred to the M32R’s internal circuit. Data bus DB0-DB15 Data bus Note: FP pin should be “H” level in Boot Mode. 10 Input/output This 16-bit data bus connects to external device. Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 6 Description of Pin Function (2/5) Type Pin type Description Input/Output Function Output Chip select signals for external devices. Read Output This signal is output when reading external devices. Byte high Output ___ Bus CS0, Chip control CS1 select __ RD ___ _______ BHW/ BHE Indicates the byte positions to which valid are transferred when writing to ________ write _______ ________ _______ external devices.BHW/ BHE and BLW/ BLE correspond to the upper address ___ _______ BLW/ BLE Byte low Output side(D0-D7 effective) and the lower address side(D8-D15 effective),respectivel. Input If WAIT input is low when the M32R accesses external devices, the wait cycle write ____ WAIT _________ Wait extended. _____ HREQ Hold Input This pin is used by an external device to request control of the external bus. __________ request The M32R goes to a hold state when HREQ input is pulled low. ____ HACK Hold Output acknowledge Multijunction TIN0 timer This signal indicates to the external device that the M32R has entered a hold state and relinquished control of the external bus. Timer input Input Input pins for multijunction timer. Timer output Output Output pins for multijunction timer. Timer clock Input Clock input pins for multijunction timer. -TIN33 TO0 -TO44 TCLK0 -TCLK3 A-D AVCC0, Analog power – AVCC0 is the power supply for the A-D0 converters. AVCC1 is the power converter AVCC1 upply supply for the A-D1 converters. Connect AVCC0 and AVCC1 to the power supply (5V or 3.3V). AVSS0, Analog ground – AVSS1 AVSS0 is the analog ground for the A-D0 converters. AVSS1 is the analog ground for the A-D1 converters. Connect AVCC0 and AVCC1 to ground. AD0IN0 Analog input Input One block of 16-channel analog input pin for A-D0 converter. -AD0IN15 AD1IN0 Two blocks of 16-channel analog input pin for A-D1 converter. -AD1IN15 VREF0, Reference VREF1 _____ ADTRG voltage input Conversion Input VREF0 is the reference voltage input pin (5V or 3.3V) for the A-D0 converters. VREF1 is the reference voltage input pin (5V or 3.3V) for the A-D1 converters. Input Hardware trigger input pin to start A-D conversion. Input System break interrupt(SBI) input pin of the interrupt controller. trigger Interrupt controller ___ SBI System break interrupt 11 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 7 Description of Pin Functions (3/5) Type Pin name Description Input/output Function Serial I/O SCLKI0/ UART transmit/ Input/output When channel 0 is in UART mode: SCLKO0 receive clock Clock output derived from BRG output by dividing it by 2 output or CSIO transmit/receive When channel 0 is in CSIO mode: clock Transmit/receive clock input when external clock is selected input/output Transmit/receive clock output when internal clock is selected SCLKI1/ UART transmit/ SCLKO1 receive clock Input/output When channel 1 is in UART mode: Clock output derived from BRG output by dividing it by 2 output or CSIO transmit/receive SCLKI4/ SCLKO4 When channel 1 is in CSIO mode: clock Transmit/receive clock input when external clock is selected input/output Transmit/receive clock output when internal clock is selected UART transmit/ Input/output receive clock When channel 4 is in UART mode: Clock output derived from BRG output by dividing it by 2 output or CSIO transmit/receive SCLKI5 SCLKO5 When channel 4 is in CSIO mode: clock Transmit/receive clock input when external clock is selected input/output Transmit/receive clock output when internal clock is selected UART transmit/ Input/output receive clock When channel 5 is in UART mode: Clock output derived from BRG output by dividing it by 2 output or CSIO transmit/receive 12 When channel 5 is in CSIO mode: clock Transmit/receive clock input when external clock is selected input/output Transmit/receive clock output when internal clock is selected TXD0 Transmit data Outpt Transmit data output pin for serial I/O channel 0 RXD0 Receive data Input Receive data input pin for serial I/O channel 0 TXD1 Transmit data Output Transmit data output pin for serial I/O channel 1 RXD1 Receive data Input Receive data input pin for serial I/O channel 1 TXD2 Transmit data Output Transmit data output pin for serial I/O channel 2 RXD2 Receive data Input Receive data input pin for serial I/O channel 2 TXD3 Transmit data Output Transmit data output pin for serial I/O channel 3 RXD3 Receive data Input Receive data input pin for serial I/O channel 3 TXD4 Transmit data Output Transmit data output pin for serial I/O channel 4 RXD4 Receive data Input Receive data input pin for serial I/O channel 4 TXD5 Transmit data Output Transmit data output pin for serial I/O channel 5 RXD5 Receive data Input Receive data input pin for serial I/O channel 5 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 8 Description of Pin Functions (4/5) Type Pin name Description Input/output Function Real-Time RTDTXD Transmit data Output Serial data output pin of the real-time debugger RTDRXD Receive data Input Serial data input pin of the real-time debugger RTDCLK Clock input Input Serial data transmit/receive clock input pin of the real-time debugger RTDACK Acknowledge Output This pin outputs a low pulse synchronously with the real-time debugger’s Debugger first clock of serial data output word. The low pulse width indicates the type of the command/data the realtime debugger has received. Flashonly FP Flash protect Input This pin protects the flash memory against E/W in hardware. CAN CTX Transmit data Output Data output pin from CAN module. CRX Receive data Input Data input pin to CAN module. JTMS Test mode Input Test select input for controlling the test circuit’s state transition JTCK Clock Input Clock input to the debugger module and test circuit. JTRST Test reset Input Test reset input for initializing the test circuit asynchronously. JTDO Serial output Output Serial output of test instruction code or test data. JTDI Serial input Input Serial input of test instruction code or test data. P00-P07 Input/output port 0 Input/output Programmable input/output port. P10-P17 Input/output port 1 Input/output Programmable input/output port. P20-P27 Input/output port 2 Input/output Programmable input/output port. P30-P37 Input/output port 3 Input/output Programmable input/output port. P41-P47 Input/output port 4 Input/output Programmable input/output port. P61-P67 Input/output port 6 Input/output Programmable input/output port. JTAG Input/ output port (Note) (However, P64 is an input-only port) P70-P77 Input/output port 7 Input/output Programmable input/output port. P82-P87 Input/output port 8 Input/output Programmable input/output port. P93-P97 Input/output port 9 Input/output Programmable input/output port. P100 Input/output port 10 Input/output Programmable input/output port. -P107 Note: Input/output port 5 is reserved for future use. 13 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 9 Description of Pin Functions (5/5) Type Pin name Description Input/output Function Input/ output port P110 Input/output port 11 Input/output Programmable input/output port. Input/output port 12 Input/output Programmable input/output port. Input/output port 13 Input/output Programmable input/output port. Input/output port 14 Input/output Programmable input/output port. Input/output port 15 Input/output Programmable input/output port. Input/output port 16 Input/output Programmable input/output port. Input/output port 17 Input/output Programmable input/output port. Input/output port 18 Input/output Programmable input/output port. Input/output port 19 Input/output Programmable input/output port. Input/output port 20 Input/output Programmable input/output port. Input/output port 21 Input/output Programmable input/output port. Input/output port 22 Input/output Programmable input/output port. (Note) -P117 P124 -P127 P130 -P137 P140 -P147 P150 -P157 P160 -P167 P172 -P177 P180 -P187 P190 -P197 P200 -P203 P210 -P217 P220 -P225 (However, P221 is an input-only port) Note: Use caution when using P224 and P225 because they have a debug event function. 14 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32170F6 > Expanded external area (4M bytes) EIT vector entry Logical address H'0000 0000 H'0000 0000 Internal ROM area 768K bytes (16M bytes) Reserved area (256K bytes) H'000B FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space H'001F FFFF H'0020 0000 Ghost area in units of 16M bytes CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) 1G bytes H'003F FFFF H'0040 0000 H'8000 0000 H'8000 1FFF H'8000 2000 Ghost area in units of 4M bytes H'8000 3FFF H'8000 4000 SFR area (16K bytes) Boot program space Ghost area in units of 16K bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM (40K bytes) H'0080 DFFF H'0080 E000 Reserved area (72K bytes) H'BFFF FFFF H'C000 0000 1G bytes H'BFFF FFFF System space H'FFFF FFFF H'0081 FFFF H'0082 0000 Ghost area in units of 128K bytes H'00FF FFFF Figure 6 Address Space of the M32170F6 15 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32170F4 > Expanded external area (4M bytes) EIT vector entry Logical address H'0000 0000 H'0000 0000 Internal ROM area 512K bytes (16M bytes) Reserved area (512K bytes) H'0007 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space H'001F FFFF H'0020 0000 Ghost area in units of 16M bytes CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) 1G bytes Boot program space H'003F FFFF H'0040 0000 H'8000 0000 H'8000 1FFF H'8000 2000 Ghost area in units of 4M bytes H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM (32K bytes) H'0080 BFFF H'0080 C000 Reserved area (80K bytes) H'BFFF FFFF H'C000 0000 1G bytes H'BFFF FFFF System space H'FFFF FFFF Figure 7 Address Space of the M32170F4 16 H'0081 FFFF H'0082 0000 Ghost area in units of 128K bytes H'00FF FFFF Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32170F3 > Expanded external area (4M bytes) EIT vector entry Logical address H'0000 0000 H'0000 0000 Internal ROM area 384K bytes (16M bytes) Reserved area (640K bytes) H'0005 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space H'001F FFFF H'0020 0000 Ghost area in units of 16M bytes CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) 1G bytes H'003F FFFF H'0040 0000 H'8000 0000 H'8000 1FFF H'8000 2000 Ghost area in units of 4M bytes H'8000 3FFF H'8000 4000 SFR area (16K bytes) Boot program space Ghost area in units of 16K bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM (32K bytes) H'0080 BFFF H'0080 C000 Reserved area (80K bytes) H'BFFF FFFF H'C000 0000 1G bytes H'BFFF FFFF System space H'FFFF FFFF H'0081 FFFF H'0082 0000 Ghost area in units of 128K byte H'00FF FFFF Figure 8 Address Space of the M32170F3 17 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32174F4 > Expanded external area (4M bytes) EIT vector entry Logical address H'0000 0000 H'0000 0000 Internal ROM area 512K bytes (16M bytes) Reserved area (512 bytes) H'0007 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space H'001F FFFF H'0020 0000 Ghost area in units of 16M bytes CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) 1G bytes H'003F FFFF H'0040 0000 H'8000 0000 H'8000 1FFF H'8000 2000 Ghost area in units of 4M bytes H'8000 3FFF H'8000 4000 SFR area (16K bytes) Boot program space Ghost area in units of 16K bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM (40K bytes) H'0080 DFFF H'0080 E000 Reserved area (72K bytes) H'BFFF FFFF H'BFFF FFFF H'C000 0000 1G bytes System space H'FFFF FFFF Figure 9 Address Space of the M32174F4 18 H'0081 FFFF H'0082 0000 Ghost area in units of 128K bytes H'00FF FFFF Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32174F3 > Expanded external area (4M bytes) EIT vector entry Logical address H'0000 0000 H'0000 0000 Internal ROM area 384K bytes (16M bytes) Reserved area (640K bytes) H'0005 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space H'001F FFFF H'0020 0000 Ghost area in units of 16M bytes CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) 1G bytes H'003F FFFF H'0040 0000 H'8000 0000 H'8000 1FFF H'8000 2000 Ghost area in units of 4M bytes H'8000 3FFF H'8000 4000 SFR area (16K bytes) Boot program space Ghost area in units of 16K bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM (40K bytes) H'0080 DFFF H'0080 E000 Reserved area (72K bytes) H'BFFF FFFF H'C000 0000 1G bytes H'BFFF FFFF System space H'FFFF FFFF H'0081 FFFF H'0082 0000 Ghost area in units of 128K bytes H'00FF FFFF Figure 10 Address Space of the M32174F3 19 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0 7 8 +0 address 15 0 +1 address H'0080 0000 to H'0080 007E H'0080 0080 to H'0080 00EE H'0080 078C H'0080 078E H'0080 0790 Interrupt controller (ICU) to H'0080 0200 to H'0080 023E H'0080 0240 to H'0080 07E0 to H'0080 07F2 Serial I/O to H'0080 0A26 Flash control Serial I/O Wait controller H'0080 0A80 to H'0080 0B8C H'0080 0B8E H'0080 0B90 MJT (TOP) to MJT (TIO) MJT (TMS) H'0080 03D8 A-D1 converter H'0080 0AEE MJT (common part) H'0080 03BE H'0080 03C0 to MJT (TOD0) Multijunction timer (MJT) MJT (TID1) MJT (TOD1) H'0080 0BDE H'0080 0C8C H'0080 0C8E H'0080 0C90 to MJT (TID2) MJT (TOM) H'0080 0CDE H'0080 03E0 to H'0080 03FE H'0080 0400 to H'0080 0478 H'0080 0700 to H'0080 077E MJT (TML0) H'0080 0FE0 DMAC to H'0080 0FFE H'0080 1000 to Input/output ports MJT (TML1) CAN H'0080 11FE H'0080 3FFE Note: The Real-time debugger (RTD) is an independent module operated from external circuits, and is transparent to the CPU. Figure 11 SFR Area 20 Multijunction timer (MJT) H'0080 0A00 H'0080 02FE H'0080 0300 to MJT (TID0) A-D0 converter H'0080 0146 H'0080 0180 15 +1 address H'0080 07DE H'0080 0100 to 7 8 +0 address Multijunction timer (MJT) Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in Flash Memory and RAM 32170 and 32174 Group contain Flash Memory and RAM stated as follows. The internal flash memory can be programmed on-board (i.e., while being mounted on the printed circuit board). This means that the same chip as will be used in mass-production can be used directly from the development stage on, allowing for system development without having to change the printed circuit board when proceeding from trial production to mass-production. Table 10 Flash memory and RAM Size (32170 Group) Type Name ROM Size RAM Size M32170F6VFP 768K bytes 40K bytes M32170F4VFP 512K bytes 32K bytes M32170F3VFP 384K bytes 32K bytes M32170F6VWG 768K bytes 40K bytes M32170F4VWG 512K bytes 32K bytes M32170F3VWG 384K bytes 32K bytes Table 11 Flash memory and RAM Size (32174 Group) Type Name ROM Size RAM Size M32174F4VFP 512K bytes 40K bytes M32174F3VFP 384K bytes 40K bytes M32174F4VWG 512K bytes 40K bytes M32174F3VWG 384K bytes 40K bytes Built-in Virtual-flash Emulation Function Internal flash memory, which is divided from the first address in units of 8 Kbyte (L banks), can be replaced in 8 -Kbyte blocks (H70080 4000-H’0080 5FFF) of the internal RAM. And also the internal flash memory, which is divided from the first address in units of 4-Kbyte areas (S banks), can be replaced in 4 Kbytes areas. This function allows parts of the program which are frequently changed during development to be altered or evaluated without having to reset the microcomputer each time. What’s more, when combined with the realtime debugger, this function helps to reduce the program evaluation period, because data in the RAM can be rewritten without requiring any CPU load. 21 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Internal flash > H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8K bytes) L bank 1 (8K bytes) L bank 2 (8K bytes) < Internal RAM > H'0080 4000 8K bytes H'0080 6000 8K bytes H'0080 8000 H'0006 4000 H'0006 6000 L bank 50 (8K bytes) L bank 51 (8K bytes) 8K bytes H'0080 A000 8K bytes 4K bytes 4K bytes H'000B C000 H'000B E000 L bank 94 (8K bytes) L bank 95 (8K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-3, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 12 Virtual-Flash Emulation Areas of the M32170F6VFP (Replaced in Units of 8 Kbytes) < Internal flash > H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes) < Internal RAM > H'0080 4000 8K bytes 8K bytes 8K bytes 8K bytes 4K bytes 4K bytes H'000B E000 H'000B F000 H'0080 C000 H'0080 D000 S bank 190 (4K bytes) S bank 191 (4K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 13 Virtual-Flash Emulation Areas of the M32170F6VFP (Replaced in Units of 4 Kbytes) 22 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Internal flash > H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8K bytes) L bank 1 (8K bytes) L bank 2 (8K bytes) < Internal RAM > 8K bytes H'0080 4000 8K bytes H'0080 6000 8K bytes H'0080 8000 4K bytes 4K bytes H'0007 C000 H'0007 E000 L bsnk 62 (8K bytes) L bank 63 (8K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-2, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 14 Virtual-Flash Emulation Areas of the M32170F4VFP (Replaced in Units of 8 Kbytes) < Internal flash > H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes) < Internal RAM > H'0080 4000 8K bytes 8K bytes 8K bytes H'0007 E000 H'0007 F000 4K bytes S bank 126 (4K bytes) S bank 127 (4K bytes) 4K bytes H'0080 A000 H'0080 B000 Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 15 Virtual-Flash Emulation Areas of the M32170F4VFP (Replaced in Units of 4 Kbytes) The table below shows Virtual-Flash Emulation Areas of the M32170F4 and M32170F3. Table 12 Virtual-Flash Emulation Areas of the M32170F4 and M32170F3 Type Virtual-Flash Emulation Areas M32170F4VFP,M32170F4VWG H’ 0000 0000 - H’ 0007 FFFF M32170F3VFP,M32170F3VWG H’ 0000 0000 - H’ 0005 FFFF 23 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Internal flash > H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8K bytes) L bank 1 (8K bytes) L bank 2 (8K bytes) < Internal RAM > H'0080 4000 8K bytes H'0080 6000 8K bytes H'0080 8000 8K bytes 4K bytes 4K bytes H'0007 C000 H'0007 E000 H'0080 C000 8K bytes L bank 62 (8K bytes) L bank 63 (8K bytes) H'0080 DFFF Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-2, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Note 3: Internal RAM area (H’0080 C000-H’0080 DFFF) cannot be used as Virtual Flash Emulation area. Figure 16 Virtual-Flash Emulation Areas of the M32174F4VFP (Replaced in Units of 8 Kbytes) < Internal flash > H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes) < Internal RAM > H'0080 4000 8K bytes 8K bytes 8K bytes H'0007 E000 H'0007 F000 4K bytes S bank 126 (4K bytes) S bank 127 (4K bytes) 4K bytes H'0080 A000 H'0080 B000 H'0080 C000 8K bytes H'0080 DFFF Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Note 3: Internal RAM area (H’0080 C000-H’0080 DFFF) cannot be used as Virtual Flash Emulation area. Figure 17 Virtual-Flash Emulation Areas of the M32174F4VFP (Replaced in Units of 4 Kbytes) The table below shows Virtual-Flash Emulation Areas of the M32174F4 and M32174F3. Table 13. Virtual-Flash Emulation Areas of the M32174F4 and M32174F3 Type Name Virtual-Flash Emulation Areas M32174F4VFP,M32174F4VWG H’ 0000 0000 - H’ 0007 FFFF M32174F3VFP,M32174F3VWG H’ 0000 0000 - H’ 0005 FFFF 24 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Input/output Ports otherinternal peripheral I/O or external extended bus signal The microcomputer has a total of 157 input/output ports lines. These pin functions are selected by using the chip operation mode select or the input/output port operation mode P0-P22. (However, P5 is reserved for future use.) The input/ output ports can be used as input ports or output ports by setting up their direction registers. Each input/output port is a dual-function pin shared with registers. These input/output ports are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5V or 3.3V. Table 14 Outline of Input/output Ports Item Specification Number of Port Total 157 ports P0 : P00 - P07 (8 lines) P1 : P10 - P17 (8 lines) P2 : P20 - P27 (8 lines) P3 : P30 - P37 (8 lines) P4 : P41 - P47 (7 lines) P6 : P61 - P67 (7 lines) P7 : P70 - P77 (8 lines) P8 : P82 - P87 (6 lines) P9 : P93 - P97 (5 lines) P10 : P100 - P107 (8 lines) P11 : P110 - P117 (8 lines) P12 : P124 - P127 (4 lines) P13 : P130 - P137 (8 lines) P14 : P140 - P147 (8 lines) P15 : P150 - P157 (8 lines) P16 : P160 - P167 (8 lines) P17 : P172 - P177 (6 lines) P18 : P180 - P187 (8 lines) P19 : P190 - P197 (8 lines) P20 : P200 - P203 (4 lines) P21 : P210 - P217 (8 lines) P22 : P220 - P225 (6 lines) Port function The input/output ports can be set for input or output ___ mode bitwise by using the input/output port direction control register. (However, P64 is an SBI input-only port, and P221 is CAN input-only port.) Pin function Dual-functions shared with peripheral I/O or external extended signals (or multi-functions shared with peripheral I/Os which have multiple functions.) Pin function changeover P0-4, P225, P225 : Changed by setting CPU operation mode (MOD0 and MOD1 pins) P6-22 : Changed by setting the input/output port operation mode register. (However, peripheral I/O pin functions are selected using the peripheral I/O register.) Table 15 CPU Operation Modes and P0-P4, P224, and P225 Pin Functions MOD0 MOD1 Operation mode Pin functions of P0-P4, P224, P225 VSS VSS Single-chip mode nput/output port pin VSS VCCE External extended mode VCCE VSS Processor mode (FP pin = VSS) VCCE VCC Reserved (use inhibited) External extended signal pin – Note: VCC and VSS are connected to +5 V and GND, respectively. 25 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CPU operation mode settings (Note1) 0 1 2 3 4 5 6 7 P0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 P1 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 P2 A23 A24 A25 A26 A27 A28 A29 A30 P3 A15 A16 A17 A18 A19 A20 A21 A22 BLW BHW RD CS0 CS1 A13 A14 (P61) (P62) (P63) SBI SCLKI4/ SCLKO4 SCLKI5/ SCLKO5 ADTRG WAIT HREQ HACK TXD0 RXD0 SCLKI0/ SCLKO0 TXD1 RXD1 SCLKI1/ SCLKO1 TO16 TO17 TO18 TO19 TO20 P4 (Reserved) P5 P6 P7 BCLK P8 P9 P10 TO8 TO9 TO10 TO11 TO12 TO13 TO14 TO15 P11 TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TCLK0 TCLK1 TCLK2 TCLK3 P12 Input/output port operation mode register settings RTDTXD RTDRXD RTDACK RTDCLK P13 TIN16 TIN17 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 P14 TIN8 TIN9 TIN10 TIN11 TIN12 TIN13 TIN14 TIN15 P15 TIN0 TIN1 TIN2 TIN3 TIN4 TIN5 TIN6 TIN7 P16 TO21 TO22 TO23 TO24 TO25 TO26 TO27 TO28 TIN24 TIN25 TXD2 RXD2 TXD3 RXD3 P17 P18 TO29 TO30 TO31 TO32 TO33 TO34 TO35 TO36 P19 TIN26 TIN27 TIN28 TIN29 TIN30 TIN31 TIN32 TIN33 P20 TXD4 RXD4 TXD5 RXD5 P21 TO37 TO38 TO39 TO40 TO41 TO42 TO43 TO44 P22 CTX CRX (P222) (P223) A11 A12 (Note2) (Note2) Note 1: The pin function are selected by setting the MOD0 and MOD1 pins. Note 2: The pin function are selected by setting the MOD0 and MOD1 pins. Also, use of this pin requires caution because it has a debug event function. Figure 18 Input/output Ports and Pin Function Assignments 26 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in 10-Channel DMAC The microcomputer also supports cascaded connection be- The microcomputer contains 10 channels of DMAC, allowing tween DMA channels (starting DMA transfer on a channel at end of transfer on another channel). This makes advanced for data transfer between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs. DMA transfer requests can be issued from the user-cre transfer processing possible without causing any additional CPU load. ated software, as well as can be triggered by a signal generated by the internal peripheral I/O (A-D converter, MJT, or serial I/O). Table 16 Outline of the DMAC Item Content Number of channels 10 channels Transfer request • Software trigger • Request from internal peripheral I/O: A-D converter, multijunction timer, or serial I/O (reception completed, transmit buffer empty) • Cascaded connection between DMA channels possible (Note) Maximum number of times transferred 256 times Transferable address space • 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO, Transfer data size 16 bits or 8 bits Transfer method Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Transfer mode Single transfer mode Direction of transfer One of three modes can be selected for the source and destination of transfer: • Address fixed • Address increment • 32-channel ring buffer Channel priority Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (Fixed priority) Maximum transfer rate 13.3 Mbytes per second (when internal peripheral clock = 20 MHz) Interrupt request Group interrupt request can be generated when each transfer count register underflows Transfer area 64 Kbytes from H’0080 0000 to H’0080 FFFF (Transfer is possible in the entire internal and between internal RAMs are supported RAM/SFR area) Note: The following DMA channels can be cascaded. DMA transfer on channel 1 started at end of one DMA transfer on channel 0 DMA transfer on channel 2 started at end of one DMA transfer on channel 1 DMA transfer on channel 0 started at end of one DMA transfer on channel 2 DMA transfer on channel 4 started at end of one DMA transfer on channel 3 DMA transfer on channel 6 started at end of one DMA transfer on channel 5 DMA transfer on channel 7 started at end of one DMA transfer on channel 6 DMA transfer on channel 5 started at end of one DMA transfer on channel 7 DMA transfer on channel 9 started at end of one DMA transfer on channel 8 DMA transfer on channel 5 started at end of all DMA transfers on channel 0 (underflow of transfer count register) 27 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group Internal bus SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER DMA channel 0 Software start Source One DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) DMA request selector Destination Transfer count MJT (input event bus 2) udf DMA channel 1 Software start MJT (output event bus 0) MJT (TIN13 input signal) One DMA0 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 2 Software start MJT (output event bus 0) MJT (TIN18 input signal) One DMA1 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 3 Software start Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) DMA request selector Source Destination Transfer count udf DMA channel 4 Software start One DMA3 transfer completed Serial I/O0 (reception completed) DMA request selector MJT (TIN19 input signal) Source Interrupt request Destination Transfer count udf DMA start Internal bus arbitration Determination block Software start One DMA7 transfer completed All DMA0 transfer completed (udf) Serial I/O2 (reception completed) MJT (TIN20 input signal) DMA channel 5 DMA request selector Source Destination Transfer count udf DMA channel 6 Software start Serial I/O1 (transmit buffer empty) MJT (TIN1 input signal) DMA request selector One DMA5 transfer completed Source Destination Transfer count udf DMA channel 7 Software start Serial I/O2 (transmit buffer empty) MJT (TIN2 input signal) One DMA6 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 8 Software start MJT (intput event bus 0) Serial I/O3 (reception completed) MJT (TIN7 input signal) DMA request selector Source Destination Transfer count udf DMA channel 9 Software start Serial I/O3 (transmit buffer empty) MJT (TIN8 input signal) One DMA8 transfer completed DMA request selector Source Interrupt request Destination Transfer count udf DMA start Determination block Figure 19 Block Diagram of the DMAC 28 Internal bus arbitration Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in 64-Channel Multijunction Timers (MJT) The microcomputer contains a total of 64 channels of multijunction timers consisting of 35 channels of 16-bit output related timers, 10 channels of 16-bit input/output related timers, 11 channels of 16-bit input related timers, eight channels of 32-bit input related timers. Each timer has multiple operation modes to choose from, depending on the purposes of use. Also, the maltijunction timers internally have a clock bus, input event bus, and an output event bus, so that multiple timers can be used in combination allowing for a flexible timer configuration. The output related timers have a correcting function that allows the timer’s count value to be incremented or decremented as necessary while count is in progress, mak- E/L CLK 1/2 internal peripheral clock E/L To DMAC, A-D converter Interrupt output TO pin F/F Timer PRS Interrupt output CLK TIN pin EN Output event bus TCLK pin Output related timer : 35ch Input/output related timer : 10ch 16-bit input related timer : 11ch 32-bit input related timer : 8ch · · · Input event bus Clock bus ing real time output control possible. EN F/F Timer · · · · E/L TO pin : Edge/Level selector PRS : Prescaler : Junction box (Selector) F/F : Output flip-flop Note: This is a conceptual diagram and does not show the actual timer configuration. Figure 20 Conceptual Diagram of the Multijunction Timer (MJT) 29 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 17 Outline of Multijunction Timers (1/2) Name Type Number of channels Content TOP Output-related 11 One of three input modes can be selected in software. (Timer Output) 16-bit timer < With correction function > (down-counter) • Single-shot output mode • Delayed single-shot output mode < Without correction function > • Continuous output mode TIO Input/output-related 10 One of three input modes or four output modes can be (Timer Input Output) 16-bit timer selected by software. (down-counter) < Input modes > • Measure clear input mode • Measure free-run input mode • Noise processing input mode < Output mode without correction function • PWM output mode • Single-shot output mod • Delayed single-shot output mode • Continuous output mode TMS Input-related (Timer Measure Small) 16-bit timer 8 16-bit input measure timer. 8 32-bit input measure timer. 3 One of three input modes can be selected in software. (up counter) TML Input-related (Timer Measure Large) 32-bit timer TID Input-related (Timer Input Derivation) 16-bit timer • Fixed cycle mode (up counter) • Event count mode (up counter) • Multiply-by-4 event count mode 30 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 18 Outline of Multijunction Timers (2/2) Name Type Number of channels Content TOD output-related 16 One of four output modes can be selected in software. (Timer output Modification) 16-bit timer < No correction function > (down-counter) • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TOM output-related (Timer output Modification) 16-bit timer (down-counter) 8 One of four output modes can be selected in software. < No correction function > • PWM output mode • Single-shot PWM output mode • One-shot output mode • Continuous output mode 31 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus Output event bus Input event bus 3210 3210 IRQ2 clk S en TOP 0 0123 F/F0 TO 0 F/F1 TO 1 F/F2 TO 2 F/F3 TO 3 F/F4 TO 4 F/F5 TO 5 S F/F6 TO 6 S F/F7 TO 7 S F/F8 TO 8 S F/F9 TO 9 S F/F10 TO 10 S F/F11 TO 11 S F/F12 TO 12 S F/F13 TO 13 S F/F14 TO 14 S F/F15 TO 15 S F/F16 TO 16 S F/F17 TO 17 S F/F18 TO 18 S F/F19 TO 19 F/F20 TO 20 udf IRQ2 TCLK0 clk TCLK0S en TOP 1 udf IRQ2 clk IRQ9 TIN0 en TOP 2 udf IRQ2 TIN0S clk S en TOP 3 udf IRQ2 DRQ7 clk en TOP 4 udf IRQ2 clk en TOP 5 udf IRQ1 TIN1 clk S IRQ9 TIN1S clk S DRQ8 en TOP 6 udf IRQ1 en TOP 7 udf S IRQ9 TIN2 TIN2S S clk S clk clk DRQ9 TIN3S TIN4 TIN4S TIN5 TIN5S en TOP 8 udf en TOP 9 udf IRQ6 IRQ5 en TOP 10 udf IRQ0 IRQ12 TIN3 IRQ6 S clk IRQ12 S IRQ12 S en/cap TIO 0 udf IRQ0 clk en/cap TIO 1 udf IRQ0 clk udf en/cap TIO 2 en/cap TIO 3 udf en/cap TIO 4 udf IRQ0 S clk IRQ4 IRQ12 TIN6 1/2 internal peripheral clock TCLK1 TIN7 clk S TIN6S S PRS0 PRS1 S PRS2 TCLK1S IRQ4 S IRQ8 TIN7S clk en/cap TIO 5 udf en/cap TIO 6 udf S DRQ10 TCLK2 TIN8 TCLK2S IRQ4 S IRQ8 TIN8S clk S IRQ4 DRQ11 TIN9S en/cap TIO 7 udf S IRQ8 TIN10 clk S IRQ8 TIN9 clk S TIN10S DRQ0 IRQ3 en/cap TIO 8 udf en/cap TIO 9 udf S IRQ3 IRQ8 TIN11 clk S TIN11S S 3210 3210 PRS0-5 0123 : Prescaler F/F Figure 21 Block Diagram of Multijunction Timers (MJT) (1/4) 32 : Output flip-flop S : Selector Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 TCLK3 Input event bus Output event bus 3210 TCLK3S 0123 clk S cap3 IRQ10 TIN12 TMS 0 cap2 cap1 IRQ7 cap0 ovf S TIN12S IRQ10 TIN13 S TIN13S DRQ3 IRQ10 TIN14 TIN14S TIN15 TIN15S S IRQ10 S clk S cap3 IRQ10 TIN16 TIN16S TIN17 TIN17S TIN18 TIN18S TMS 1 cap2 cap1 IRQ7 cap0 ovf S IRQ10 S IRQ10 S DRQ5 IRQ10 TIN19 S TIN19S DRQ6 1/2 internal peripheral clock S clk DRQ12 cap3 IRQ11 TIN20 TIN20S TIN21 TIN21S TIN22 TIN22S TML0 cap2 cap1 cap0 S IRQ11 S IRQ11 S IRQ11 TIN23 S TIN23S 1/2 internal peripheral clock S clk cap3 IRQ18 TIN30 TIN30S TIN31 TIN31S TIN32 TIN32S TML1 cap2 cap1 S cap0 AD0TRG (To A-D converter) IRQ18 S IRQ18 DRQ2 S IRQ18 TIN33 3210 S DRQ4 S TIN33S 3210 0123 : Serector Figure 22 Block Diagram of Multijunction Timers (MJT) (2/4) 33 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus IRQ13 3210 clk TOD0_0 udf clk TOD0_1 udf TOD0_2 udf clk Output event bus 0123 IRQ13 F/F21 TO21 F/F22 TO22 F/F23 TO23 F/F24 TO24 F/F25 TO25 F/F26 TO26 F/F27 TO27 F/F28 TO28 F/F29 TO29 F/F30 TO30 F/F31 TO31 F/F32 TO32 F/F33 TO33 F/F34 TO34 F/F35 TO35 F/F36 TO36 IRQ13 IRQ13 clk TOD0_3 udf IRQ13 1/2 internal peripheral clock clk PRS3 TOD0_4 udf IRQ13 TOD0_5 clk udf IRQ13 clk TOD0_6 clk TOD0_7 udf IRQ13 clk CLK1 CLK2 TID0 udf ovf udf TIN24 TIN25 IRQ14 IRQ16 clk EN TOD1_0 udf IRQ16 clk clk clk 1/2 internal peripheral clock clk PRS4 clk EN EN TOD1_1 udf IRQ16 TOD1_2 udf IRQ16 EN TOD1_3 EN TOD1_4 EN TOD1_5 udf IRQ16 udf IRQ16 udf IRQ16 clk clk TOD1_6 EN TOD1_7 udf IRQ16 udf IRQ15 clk CLK1 CLK2 TID1 TIN26 TIN27 AD1TRG (To A-D converter) ovf udf IRQ16 clk clk clk clk 1/2 internal peripheral clock EN clk PRS5 clk EN TOM0_0 EN TOM0_1 EN udf F/F37 TO37 F/F38 TO38 F/F39 TO39 F/F40 TO40 F/F41 TO41 F/F42 TO42 F/F43 TO43 F/F44 TO44 IRQ16 udf IRQ16 TOM0_2 udf IRQ16 EN TOM0_3 EN TOM0_4 EN TOM0_5 udf IRQ16 udf IRQ16 udf IRQ16 clk clk EN TOM0_6 EN TOM0_7 udf IRQ16 clk CLK1 CLK2 TID2 udf ovf udf IRQ17 TIN28 TIN29 3210 3210 Figure 23 Block Diagram of Multijunction Timers (MJT) (3/4) 34 0123 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus Output event bus 3210 0123 AD0 completed S DMA0 udf end DMAIRQ0 TIN13 S DMA1 udf end DMAIRQ0 TIN18 S DMA2 udf udf end DMAIRQ0 SIO0-TXD SIO1-RXD S DMA3 udf end DMAIRQ0 SIO0-RXD S DMA4 udf DMAIRQ0 SIO2-RXD S DMA5 udf end DMAIRQ1 SIO1-TXD S DMA6 udf end DMAIRQ1 SIO2-TXD S DMA7 udf end DMAIRQ1 S DMA8 udf end DMAIRQ1 S DMA9 udf DMAIRQ1 TIO8-udf TIN0 TIN19 TIN20 TIN1 TIN2 SIO3-RXD TIN7 SIO3-TXD TIN8 3210 3210 0123 S : Selector Figure 24 Block Diagram of Multijunction Timers (MJT) (4/4) 35 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in Two Independent A-D Converters In addition to ordinary A-D conversion, the converters sup- The microcomputer contains two 16-channel converters with port comparator mode in which the set value and A-D converted value are compared to determine which is larger or 10-bit resolution (A-D0 converter and A-D1 converter). In addition to single conversion on each channel, continuous A-D conversion on a combined group of 4, 8, and 16 channels is possible. The A-D converted value can be read out in either 10 bits or 8 bits. smaller than the other. When A-D conversion is finished, the converters can generated a DMA transfer request (A-D0 converter only), as well as an interrupt. The A-D converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5 V or 3.3V. Table 19 Outline of the A-D Converters Item Content Analog input 16 channels × 2 A-D conversion method Successive approximation method. Resolution 10 bits (Conversion results can be read out in either 10 or 8 bits.) Absolute accuracy (Note 1) Normal rate mode +2 LSB (Conditions: Ta = -40 ~ +125°C, AVCC0,1 = VREF0,1 = 5.12V) Double rate mode +2 LSB Conversion mode A-D conversion mode,comparator mode Operation mode Single mode, scan mode Scan mode Single -shot scan mode, continuous scan mode. Conversion start trigger Software start Started by setting A-D conversion start bit to 1. Hardware start A-D0 converter started by MJT output event bus 3, A-D1 converter started by TID1 overflow or underflow. _____ Started by external ADTRG pin input. Conversion rate f(BCLK) : Internal peripheral clock operating frequency Interrupt request generation During single mode Normal 299 × 1/ f (BCLK) (Note 2) (Shortest time ) Double speed 173 × 1/ f (BCLK) During comparator mode Normal 47 × 1/ f (BCLK) (Shortest time ) Double speed 29 × 1/ f (BCLK) When A-D conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. DMA transfer request generation (Note 3) When A-D conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. Note 1: The rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when the microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the board. Note 2: When BCLK = 20 MHz, this is1/f (BCLK) = 50ns. Note 3: The DMA transfer request generation function is available for only the A-D0 converter. The A-D1 converter does not have this function. 36 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal data bus 8-bit readout 10-bit readout Shifter AD0DT0 10-bit A-D0 Data Register 0 AD0DT1 10-bit A-D0 Data Register 1 AD0SIM0,1 Single Mode Register AD0DT2 10-bit A-D0 Data Register 2 AD0SCM0,1 Scan Mode Register AD0DT3 10-bit A-D0 Data Register 3 AD0DT4 10-bit A-D0 Data Register 4 AD0DT5 10-bit A-D0 Data Register 5 AD0DT6 10-bit A-D0 Data Register 6 AD0DT7 10-bit A-D0 Data Register 7 AD0DT8 10-bit A-D0 Data Register 8 AD0DT9 10-bit A-D0 Data Register 9 AD0DT10 10-bit A-D0 Data Register 10 AD0DT11 10-bit A-D0 Data Register 11 AD0DT12 10-bit A-D0 Data Register 12 AD0DT13 10-bit A-D0 Data Register 13 AD0DT14 10-bit A-D0 Data Register 14 AD0DT15 10-bit A-D0 Data Register 15 AD0CMP Output event bus 3 (Multijunction timer) A-D comparate Data Register P67/ADTRG A-D Control Circuit AVCC0 AVSS0 10-bit A-D Successive Approximation Register (AD0SAR) VREF0 10-bit D-A Converter Comparator AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0N10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 • Mode selection • Channel selection Interrupt request • Conversion time selection • Flag control DMA transfer request • Interrupt control Selector Successive Approximation -type A-D Converter Unit Figure 25 Block Diagram of the A-D0 Converter 37 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal data bus 8-bit readout 10-bit readout Shifter AD1DT0 10-bit A-D1 Data Register 0 AD1DT1 10-bit A-D1 Data Register 1 AD1SIM0,1 Single Mode Register AD1DT2 10-bit A-D1 Data Register 2 AD1SCM0,1 Scan Mode Register AD1DT3 10-bit A-D1 Data Register 3 AD1DT4 10-bit A-D1 Data Register 4 AD1DT5 10-bit A-D1 Data Register 5 AD1DT6 10-bit A-D1 Data Register 6 AD1DT7 10-bit A-D1 Data Register 7 AD1DT8 10-bit A-D1 Data Register 8 AD1DT9 10-bit A-D1 Data Register 9 AD1DT10 10-bit A-D1 Data Register 10 AD1DT11 10-bit A-D1 Data Register 11 AD1DT12 10-bit A-D1 Data Register 12 AD1DT13 10-bit A-D1 Data Register 13 AD1DT14 10-bit A-D1 Data Register 14 AD1DT15 10-bit A-D1 Data Register 15 AD1CMP A-D Comparate Data Register TID1 underflow /overflow P67/ADTRG A-D Control Circuit AVCC1 AVSS1 10-bit A-D Successive Approximation Register (AD1SAR) VREF1 10-bit D-A Converter Comparator AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 AD1IN8 AD1IN9 AD1N10 AD1IN11 AD1IN12 AD1IN13 AD1IN14 AD1IN15 • Mode selection • Channel selection Interrupt request • Conversion time selection • Flag control • Interrupt control Selector Successive Approximation -type A-D Converter Unit Note: The A-D converter does not have DMA transfer request generation function. Figure 26 Block Diagram of the A-D1 Converter 38 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 6-channel High-speed Serial I/Os The microcomputer contains six channels of serial I/Os consisting of four channels that can be set for CSIO mode (clock-synchronized serial I/O) or UART mode (asynchronous serial I/O) and two other channels that can only be set for UART mode. The SIO has the function to generate a DMA transfer request when data reception is completed or the transmit register becomes empty, and is capable of high-speed serial communication without causing any additional CPU load. Table 20 Outline of Serial I/O Item Content Number of channels CSIO/UART: 4 channels (SIO0,SIO1,SIO4,SIO5) UART only : 2 channels (SIO2,SIO3) Clock During CSIO mode : Internal clock / external clock, selectable (Note1) During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count sourcef (BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected) (Note2) Data format CSIO mode : Data length = Fixed to 8 bits Order of transfer = Fixed to LSB first UARTmode : Start bit = 1 bit Character length = 7, 8, or 9 bits Parity bit = Added or not added (When added, selectable between odd and even parity) Stop bit = 1 or 2 bits Order of transfer = Fixed to LSB first Baud rate Error detection CSIO mode : 152 bits per second to 2 Mbits per second (when operating with f(BCLK) = 20 MHz) UARTmode : 19 bits per second to 156 Kbits per second (when operating with f(BCLK) = 20 MHz) CSIO mode : Overrun error only UARTmode : Overrun, parity, and framing errors (The error-sum bit indicates which error has occurred) Fixed cycle clock When SIO0, SIO1, SIO4, or SIO5 is in UART mode, this function outputs a 1/2 BRG clock from the SCLK pin. output function Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16. Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations. 39 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER SIO0 SIO0 Transmit Buffer Register Transmit interrupt TXD0 SIO0 Transmit Shift Register RXD0 SIO0 Receive Shift Register To interrupt controller Receive interrupt Transmit/ receive control circuit Transmit DMA transfer request To DMAC3 Receive DMA transfer request To DMAC4 SIO0 Receive Buffer Register UART Mode CSIO Mode When extended clock selected When internal clock selected BCLK Clock divider 1/16 1 (Set value + 1) Baud rate generator (BRG) SCLKI0/ SCLKO0 1/2 CSIO Mode When internal clock selected When UART mode selected SIO1 TXD1 RXD1 SIO1 Transmit Shift Register SIO1 Receive Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request Internal data bus BCLK, BCLK/8, BCLK/32, BCLK/256 To interrupt controller To DMAC6 To DMAC3 SCLKI1/ SCLKO1 SIO2 TXD2 RXD2 SIO2 Transmit Shift Register SIO2 Receive Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To DMAC7 To DMAC5 SIO3 TXD3 SIO3 Transmit Shift Register RXD3 SIO3 Receive Shift Register Transmit/ receive control circuit Transmit interrupt Receive interrupt Transmit DMA transfer request Receive DMA transfer request To interrupt controller To DMAC9 To DMAC8 SIO4 TXD4 RXD4 SIO4 Transmit Shift Register SIO4 Receive Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt SCLKI4 / SCLKO4 SIO5 TXD5 RXD5 SIO5 Transmit Shift Register SIO5 Receive Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt Note 1: When BCLK is selected, the BRG set value is subject to limitations. Note 2: SIO2 and SIO3 do not have the SCLKI/SCLKO function. Figure 27 Block Diagram of Serial I/O 40 To interrupt controller SCLKI5 / SCLKO5 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CAN Module The M32170 and M32174 Group contains two Full CAN modules compliant with CAN Specification V2.0B (CAN0 and CAN1), each of which has 16-channel message slots and three mask registers. Data bus CAN0 Status Register CAN0 REC Register CAN0 TEC Register CAN0 Message Slot 0-15 Control Register CAN0 Extended Register CAN0 Configuration Register CAN0 Control Register Acceptance Filtering CTX CRX CAN0 Protocol Controller 2.0B active 16-bit Timer CAN0 Time Stamp Register CAN0 Global Mask Register CAN0 Local Mask Register A CAN0 Local Mask Register B Message Memory (1) Message ID (2) Data length code (3) Message data (4) Time stamp CAN0 Slot Status Register CAN0 Slot Interrupt Control Register CAN0 Error Interrupt Control Register Interrupt Control Circuit CAN0 Transmit/Receive & Error Interrupt Figure 28 Block Diagram of the CAN Module 41 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 8-level Interrupt Controller Realtime Debugger (RTD) The Interrupt Controller controls interrupt requests from each internal peripheral I/O (31 sources) by using eight pri- The Realtime Debugger (RTD) provides a function for accessing directly from the outside to the internal RAM. It uses ority levels assigned to each interrupt source, including interrupts disabled. In addition to these interrupts, it handles a dedicated clock-synchronized serial I/O to communicate with the outside. System Break Interrupt (SBI), Reserved Instruction Exception (RIE), and Address Exception (AE) as nonmaskable in- Use of the RTD communicating via dedicated serial lines allows the internal RAM to be read out and rewritten without terrupts. having to halt the CPU. Wait Controller The Wait Controller supports access to external devices. For access to an external extended area of up to 1 Mbytes (during external extended or processor mode), the Wait Controller controls bus cycle extension by inserting one to ____ four wait cycles or using external WAIT signal input. 32170, 32174 Group RTDCLK RTDRXD M32R CPU Internal RAM Real-Time Debugger (RTD) Virtual-DPRAM structure RTDTXD RTDACK R/W without CPU intervention Data Bus(CPU) Data Bus(RTD) Figure 29 Conceptual Diagram of the Realtime Debugger (RTD) 42 Command address Data Data Data Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CPU Instruction Set • Arithmetic operation The M32R employs a RISC architecture, supporting a total of 83 discrete instructions. ADD ADD3 ADDI ADDV ADDV3 ADDX NEG SUB SUBV SUBX (1) Load/store instructions Perform data transfer between memory and registers. LD LDB LDUB LDH LDUH LOCK ST STB STH UNLOCK Load Load byte Load unsigned byte Load halfword Load unsigned halfword Load locked Store Store byte Store halfword Store unlocked (2) Transfer instructions Perform register to register transfer or register to immediate transfer. LD24 LDI MV MVFC MVTC SETH Load 24-bit immediate Load immediate Move register Move from control register Move to control register Set high-order 16-bit Add Add 3-operand Add immediate Add (with overflow checking) Add 3-operand Add with carry Negate Subtract Subtract (with overflow checking) Subtract with borrow • Multiplication/division DIV DIVU MUL REM REMU Divide Divide unsigned Multiply Remainder Remainder unsigned • Shift SLL SLL3 SLLI SRA SRA3 SRAI SRL SRL3 SRLI Shift Shift Shift Shift Shift Shift Shift Shift Shift left logical left logical 3-operand left logical immediate right arithmetic right arithmetic 3-operand right arithmetic immediate right logical right logical 3-operand right logical immediate (5) Instructions for the DSP function (3) Branch instructions Used to change the program flow. BC Branch on C-bit BEQ Branch on equal BEQZ Branch on equal zero BGEZ Branch on greater than or equal zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal zero BLTZ Branch on less than zero BNC Branch on not C-bit BNE Branch on not equal BNEZ Branch on not equal zero BRA Branch JL Jump and link JMP Jump NOP No operation Perform 32 bit × 16 bit or 16 bit × 16 bit multiplication or sumof-products calculation. These instructions also perform rounding of the accumulator data or transfer between accumulator and general-purpose register. MACHI MACLO MACWHI MACWLO MULHI MULLO MULWHI (4) Arithmetic/logic instructions MULWLO Perform comparison, arithmetic/logic operation, multiplica- MVFACHI MVFACLO MVFACMI tion/division, or shift between registers. • Comparison CMP CMPI CMPU CMPUI Compare Compare immediate Compare unsigned Compare unsigned immediate MVTACHI MVTACLO RAC RACH Multiply-accumulate high-order halfwords Multiply-accumulate low-order halfwords Multiply-accumulate word and high-order halfword Multiply-accumulate word and low-order halfword Multiply high-order halfwords Multiply low-order halfwords Multiply word and high-order halfword Multiply word and low-order halfword Move from accumulator high-order word Move from accumulator low-order word Move from accumulator middle-order word Move to accumulator high-order word Move to accumulator low-order word Round accumulator Round accumulator halfword • Logical operation (6) EIT related instructions AND AND3 NOT OR OR3 XOR XOR3 Start trap or return from EIT processing. AND AND 3-operand Logical NOT OR OR 3-operand Exclusive OR Exclusive OR 3-operand RTE TRAP Return from EIT Trap 43 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Multiply instruction > 63 0 < Multiply-accumulate instruction > ACC Rsrc1 15 16 0 H 31 Rsrc2 15 16 0 L H 31 Rsrc1 15 16 0 L H L 31 H × L × × MULHI instruction 0 Rsrc2 15 16 0 31 × MULLO instruction 63 + + ACC Rsrc1 0 Rsrc2 15 16 0 31 32 bit MACHI instruction 0 H MACLO instruction 63 31 ACC L 0 63 × ACC × MULWHI instruction 0 MULWLO instruction 63 Rsrc1 0 Rsrc2 15 16 0 31 ACC 31 H 32 bit L × × + + < Ropund off instruction > MACWHI instruction 0 63 0 ACC ACC RAC instruction 0 sign MACWLO instruction 63 63 data < Accumulator - register transfer instruction > 0 0 63 0 15 16 MVFACMI instruction 31 32 47 48 0 63 31 Rsrc ACC ACC MVFACHI instruction RACH instruction 0 63 sign data 0 Figure 30 Instructions for the DSP Function 44 MVFACLO instruction 0 1 Rdest MVTACHI instruction 0 MVTACLO instruction 31 32 ACC 63 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Package Dimensions Diagram 240P6Y-A Plastic 240pin 32✕32mm body QFP Weight(g) JEDEC Code – Lead Material Cu Alloy MD e EIAJ Package Code QFP240-P-3232-0.50 b2 181 240 ME HD D 180 1 I2 Symbol HE E Recommended Mount Pad A A1 A2 b c D E e HD HE L L1 y 121 60 120 61 F A L1 b y A1 c A2 e Detail F L b2 I2 MD ME Dimension in Millimeters Max Nom Min 4.1 – – 0.35 0.45 0.25 3.6 – – 0.3 0.2 0.15 0.2 0.15 0.13 32.1 32.0 31.9 32.1 32.0 31.9 0.5 – – 34.8 34.6 34.4 34.8 34.6 34.4 0.7 0.5 0.3 1.3 – – 0.1 – – 10° 0° – – 0.225 – – – 1.2 – 32.6 – – 32.6 – 45 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 255F7F EIAJ Package Code – 255pin 17✕17mm body FBGA JEDEC Code – Weight(g) 17TYP (16.6) Under Development 0.20 C A 0.8✕19=15.2 0.35±0.05 0.8TYP 0.20 C B ✕4 0.2 Note: 255FBGA is currently under development. 46 0.8TYP 0.8✕19=15.2 0.1 C (16.6) 17TYP A Y W V U T R P N M L K J H G F E D C B A B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C 255-φ0.45±0.05 1.2MAX φ0.08 M C AB 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER MEMO 47 Mitsubishi Microcomputers 2001-5-14 Rev.1.0 32170Group, 32174Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • • © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective May 2001. Specifications subject to change without notice. Revision Description List Rev. No. Page 1.0 32170 Group, 32174 Group Data Sheet Revision Description Point First Edition Rev. date 010514 (1/1)