Order this document by MC141627/D SEMICONDUCTOR TECHNICAL DATA Product Preview The Advanced PAL Comb Filter–II is a video signal processor for VCRs, LDPs, and TVs. It separates the Luminance Y and Chrominance C signal from the NTSC/PAL composite signal by using digital signal processing techniques which minimize dot–crawl and cross–color. The built–in 4xFSC PLL circuit allows a subcarrier signal input, which generates 4xFSC clock for video signal processing. This filter allows a video signal input of an extended frequency bandwidth by using a 4xFSC clock. The built–in vertical enhancer circuit reduces noise and dot crawl on the Luminance Y signal. The built–in A/D and D/A converters allow easy connection to analog video circuits. • • • • • • • • • • FT SUFFIX QFP PACKAGE CASE 898 48 1 ORDERING INFORMATION MC141627FT Quad Flat Package (QFP) Built–In High Speed 8–Bit A/D Converter Four Line Memories (4540 Bytes) Advanced Comb–II Process Built–In Vertical Enhancer Vertical Dot Reduction Process Two Built–In High Speed 8–Bit D/A Converters Built–In 4xFSC PLL Circuit Built–In Clamp Circuit Digital Interface Mode On–Chip Reference Voltage for A/D Converter D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7 PIN ASSIGNMENT 37 48 25 24 36 13 12 1 TE1 TE0 MODE1 MODE0 CLK(AD) GND(D) NC CLC CLout Vin RBT RTP PCO OVCC BIAS FILIN GND(DA) Yout VCC(DA) Cout REF(DA) I bias GND(AD) VCC(AD) D3 D2 D1 D0 BYPASS VH GND(D) VCC(D) FSC N/M PAL/NTSC Comb/BPF NC = NO CONNECTION This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 0.1 8/96 Motorola, Inc. 1996 MOTOROLA MC141627 1 NOISE LEVEL 1 (D4) NOISE LEVEL 2 (D5) NOISE LEVEL 3 (D6) NOISE LEVEL 4 (D7) WHITE LEVEL 1 (C0) WHITE LEVEL 2 (C1) WHITE LEVEL 3 (C2) WHITE LEVEL 4 (C3) BLACK LEVEL 1 (C4) BLACK LEVEL 2 (C5) BLACK LEVEL 3 (C6) BLACK LEVEL 4 (C7) BLOCK DIAGRAM 36 35 34 33 32 31 30 29 28 27 26 25 24 TE1 NC (D3) 37 PORT PORT 23 TE0 NC (D2) 38 NC (D1) 39 MODE 1H/2H 21 MODE0 NC (D0) 40 ACF–II PROCESSING BYPASS 41 ADAPTIVE VERTICAL ENHANCER VH 42 CLKBUF CONTROL LOGIC VERTICAL DOT PROCESSING 20 CLK(AD) 19 GND(D) 18 NC GND(D) 43 VCC(D) 44 22 MODE1 1H/2H MEMORY MODE CONTROL LOGIC 17 CLC FSC 45 CLAMP N/M 46 15 Vin CLKBUF PAL/NTSC 47 14 RBT ADC 4 5 6 7 8 FILIN GND(DA) Yout VCC(DA) Cout 9 10 11 12 VCC(AD) 3 GND(AD) 2 13 RTP I bias 1 BIAS Ibias OVCC DAC PCO DAC REF(DA) CLOCK GEN COMB/BPF 48 16 CLout *( ): Digital input mode MC141627 2 MOTOROLA ABSOLUTE MAXIMUM RATINGS* Characteristic Symbol Value Unit VCC – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) Vin – 1.5 to VCC + 1.5 V DC Output Voltage (Referenced to GND) Vout – 0.5 to VCC + 0.5 V Iin ± 20 mA DC Output Current (per Pin) Iout ± 25 mA Power Dissipation PD 750 mW Storage Temperature Tstg – 65 to + 150 °C DC Supply Voltage (Referenced to GND) DC Input Current (per Pin) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND ≤ (Vin or Vout) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. GENERAL ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C, Unless Otherwise Noted) Characteristic Symbol Min Typ Max Unit VCC* 4.75 5.0 5.25 V Operating Supply Current (at Normal Mode) ICC — 65 100 mA Operating Power Dissipation (at Normal Mode) PD — 325 525 mW Ambient Operating Temperature TA – 20 — 75 °C Supply Voltage Notes *VCC(AD), VCC(DA), VCC(D) voltage. CLOCK INPUT ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C, Unless Otherwise Noted) Symbol Min Typ Max Unit Notes fc — 4.43618 — MHz 1 Clock Frequency CLK — 17.734475 — MHz 2 FSC Clock Input Level Vfc 1 — — V p–p 3 Characteristic Subcarrier Input Frequency High Level Input Voltage CLK(AD) VICH 3.5 — — V 4 Low Level Input Voltage CLK(AD) VICL — — 1.1 V 4 Dty 45 50 55 % 4 Clock Duty Cycle CLK/CLK(AD) NOTES: 1. Color subcarrier input [FSC = (455/2) fh] locked on the burst signal of the input video signal. AC coupling input by external capacitor. 2. The internal circuit operates by 4 times clock using FSC pin input at normal (FSC) mode. The internal circuit operates by FSC pin input clock at expected normal (FSC) mode. 3. Sine wave input. 4. CLK(AD) is available only during digital input comb filter mode. MOTOROLA MC141627 3 ADC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Symbol Min Typ Max Unit Resolution — — — 8 Bits Integral Nonlinearity INL — ± 1.0 ± 1.5 LSB Characteristic DNL — ± 0.5 ± 1.0 LSB Top Reference Level VTPS 2.4 2.5 2.6 V Bottom Reference Level VBTS 0.4 0.5 0.6 V Vins 1.9 2.0 2.1 V p–p Symbol Min Typ Max Unit Differential Nonlinearity Maximum Analog Input Range During Self Reference DIGITAL ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic High Level Input Voltage MODE0, MODE1, TE0, TE1, BK, VH, C0 – C7, D0 – D7 VIH 3.15 — — V Low Level Input Voltage MODE0, MODE1, TE0, TE1, BK, VH, C0 – C7, D0 – D7 VIL — — 1.1 V Input Leakage Current [Vin = VCC(D) or GND(D)] MODE0, MODE1, TE0, TE1, BK, VH, C0 – C7, D0 – D7 Iinl — — ± 10 µA Data Setup Time (at Digital Input Comb Filter Mode) D0 – D7 tds 0 — — ns Data Hold Time (at Digital Input Comb Filter Mode) D0 – D7 tdh 20 — — ns Data Input Rise Time (at Digital Input Comb Filter Mode) D0 – D7 tr — — 10 ns Data Input Fall Time (at Digital Input Comb Filter Mode) D0 – D7 tf — — 10 ns Symbol Min Typ Max Unit Y/C Separation — 40 — — dB Band–Pass Filter Bandwidth (at – 3 dB) [( ): NTSC] — — ± 0.90 (± 0.75) — MHz Symbol Min Typ Max Unit — — — 8 Bits Integral Nonlinearity INL — — ±1 LSB Differential Nonlinearity DNL — — ± 0.5 LSB Analog Output Voltage, Yout VYO 1.1 1.2 1.3 V p–p Analog Output Voltage, Cout VCO 1.1 1.2 1.3 V p–p Full Scale Voltage, Yout VYFS 1.3 1.5 1.7 V Full Scale Voltage, Cout VCFS 1.3 1.5 1.7 V Zero Scale Voltage, Yout VYZS 0.1 0.3 0.5 V Zero Scale Voltage, Cout VCZS 0.1 0.3 0.5 V ZO — 100 300 Ω FILTERING CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic DAC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic Resolution Output Impedance MC141627 4 MOTOROLA ADC – DAC GENERAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Symbol Min Typ Max Unit Voltage Gain — – 4.4 — dB Output Bandwidth (at – 3 dB at PAL) 6.4 7.3 — MHz Characteristic Differential Gain DG — — 5 % Differential Phase DP — — 5 Deg Ibias — 135 — µA Symbol Min Typ Max Unit Vclys — 0.6 — V Symbol Min Typ Max Unit Bypass Switching Time, at Normal Mode — 9 — Clock VH Switching Time, at Normal Mode — 4 — Clock Comb/BPF Switching Time, at Normal Mode — 16 — Clock Min Typ Max Unit Noise Slice Level, at Normal Mode 0 6 15 Bits White Enhance Level, at Normal Mode 0 10 15 Bits Black Enhance Level, at Normal Mode 0 11 15 Bits Min Typ Max Unit PAL B/G/H/I Mode (2299.5 Clock) — 129.66 — µs NTSC Mode (939.5 Clock) — 65.62 — µs PAL N Mode (1867.5 Clock) — 130.34 — µs PAL M Mode (1851.5 Clock) — 129.45 — µs Bias Current (at Ibias = 10 kΩ) CLAMP CIRCUIT CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic Clamp Mode Output Voltage* * Output of CLout when connecting Vin – CLout. BK/VH CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic VERTICAL ENHANCER LEVEL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Symbol Characteristic GENERAL SIGNAL DELAY (VCC = 5.0 V, TA = 25°C ± 3°C) Symbol Characteristic CLOCK INPUT DATA (D0 – D7) tds tdh tr tf Figure 1. Digital Signal Input Timing Diagram (During Digital Input Comb Filter Mode) Clamp Circuit Characteristics (VCC = 5.0 V, TA = 25°C ± 3°C) Clamp Mode Output Voltage, Vcly (Non–input when connecting Vin – CLout) Vcly = (VTP – VBT) (N + 1) / 256 + VBT ± 50 mV where N = Clamp Code Input (N < 255) • If the calculated value of the output voltage, Vcly > Vclys, then Vcly = Vclys • Clamp Value N is fixed, N = 4. MOTOROLA MC141627 5 PIN DESCRIPTIONS Pin Pin Name Function 1 PCO 2 OVCC 3 BIAS Reference for VCO. Generally connected to GND(D) through an external resistor. 4 FILIN VCO controlled voltage input. Generally connected to PCO through an external loop filter. 5 GND(DA) 6 Yout 7 VCC(DA) 8 Cout 9 REF(DA) 10 Ibias 11 GND(AD) GND for A/D converter. 12 VCC(AD) Power supply for A/D converter. 13 RTP Top reference for A/D converter. Supplies top reference voltage internally. 14 RBT Bottom reference for A/D converter. Supplies bottom reference voltage internally. 15 Vin A/D converter input. 16 CLout 17 CLC Clamp time constant setting pin. 18 NC No connection. 19 GND(D) GND for digital circuit. 20 CLK(AD) CLK input for A/D converter. Available only during digital input comb filter mode and a portion of test mode. Input level is CMOS level. 21, 22 MODE0, MODE1 23, 24 TE0, TE1 25 C7 Vertical enhancer level at normal mode. Generally VCC(D) level. 26 – 28 C6 – C4 Vertical enhancer level at normal mode. Generally GND(D) level. 29 C3 Vertical enhancer level at normal mode. Generally VCC(D) level. 30 – 32 C2 – C0 Vertical enhancer level at normal mode. Generally GND(D) level. Phase comparator output. Power supply for VCO. GND for D/A converter. Luminance signal output. Power supply for D/A converter. Chrominance signal output. Reference for D/A converter. Generally connected to GND(DA) through a multi–layer ceramic capacitor (0.1 µF). Bias circuit current control for A/D, D/A converters. Generally connected to GND(DA) through an external resistor. Voltage output for clamp. Clamps an input signal by connecting with Vin and inputs the video signal by ac coupling. Mode inputs. GND level during normal (FSC) mode. Test mode inputs. Generally GND level. 33 D7 Vertical enhancer level at normal mode. Generally VCC(D) level. 34 – 36 D6 – D4 Vertical enhancer level at normal mode. Generally GND(D) level. 37 – 40 D3 – D0 NC pin at normal mode. Generally GND(D) level. 41 Bypass Non–YC separation processing mode. Generally GND(D) level. 42 VH 43 GND(D) GND for digital circuit. 44 VCC(D) Power supply for digital circuit. 45 FSC CLK input. ac coupling input by external capacitor. Normal (FSC) mode: Subcarrier. Normal (4xFSC) mode: 4*Subcarrier. 46 N/M PAL N/PAL M setting pin. Generally GND level. 47 PAL/NTSC PAL/NTSC setting pin. Generally GND level (PAL mode). 48 Comb/BPF Comb/BPF setting pin. Generally GND level (comb filter mode). MC141627 6 Vertical enhancer circuit mode. Generally GND(D) level. MOTOROLA DEVICE DESCRIPTION INTRODUCTION The Advanced PAL Comb Filter–II is a video signal processor for VCRs, LDPs, and TVs. It separates the Luminance Y and Chrominance C signal from the NTSC/PAL composite signal by using digital signal processing techniques which minimize dot–crawl and cross–color. The built– in 4xFSC PLL circuit allows a subcarrier signal input, which generates a 4xFSC clock for video signal processing. This filter allows a video signal input of an extended frequency bandwidth by using a 4xFSC clock. The built–in vertical enhancer circuit reduces noise and dot crawl on the Luminance Y signal. The built–in A/D and D/A converters allow easy connection to analog video circuits. DESCRIPTION The simplified block diagram of the Advanced Comb Filter–II chip is shown at the beginning of this data sheet. There are five major functions represented in this block diagram. The first block is the A/D conversion block. The high speed 8–bit binary analog–to–digital converter converts the incoming analog video signal to an 8–bit binary data stream. The conversion frequency is 14.3 MHz/17.7 MHz for NTSC/ PAL, which is four times the color subcarrier frequency. The second block contains the Advanced Comb Filter–II algorithm. The digital data from the A/D converter is processed by the algorithm of the Advanced Comb Filter–II. The composite video is filtered by the band–pass filter (BPF) and separated into the Luminance Y and Chrominance C signals. The third block is the vertical enhancer circuit block. By comparing pixel information from the vertical dot processing block, the vertical enhancer emphasizes the vertical picture outline. The fourth block is the digital–to–analog conversion block. Two 8–bit D/A converters convert the luminance and chrominance into analog outputs. The conversion frequency is four times the subcarrier signal (14.3 MHz/17.7 MHz). The chrominance analog output is biased with a dc offset of half the value of the D/A converter reference. The fifth block is a 4xFSC PLL CLK generation circuit. This block generates a clock signal that is four times the subcarrier signal. This signal is locked to the signal input on the FSC pin. This signal may be selected to equal FSC or 4xFSC. A/D Converter The composite video signal input is converted to the digital code by the high speed 8–bit A/D converter. The A/D converter reference has a self–bias function which generates VTP = 2.5 V, VBT = 0.5 V. This allows the A/D converter to function without an external reference circuit. Clamp Voltage Regulating Circuit The input video signal may be either dc or ac coupled. By connecting Vin to CLout, the internal clamp circuit will provide MOTOROLA dc restoration. The clamp voltage regulating circuit sync tip clamps the input video signal and compares it to the digital value of the clamp level ($04) with the A/D converter output code. The clamp voltage, CLout, sets the dc input level when Vin and CLout are interconnected. Advanced Comb Filter–II The Advanced PAL Comb Filter–II is a digital comb filter developed for use in the NTSC/PAL system. The vertical correlation circuit provides high picture quality and high resolution and requires no adjustment for its Y/C separation. The clock frequency is 14.3 MHz, which is four times the NTSC subcarrier. The BYPASS pin can be used to select between the composite signal output without Y/C separation and the Y/C signal output. Table 1 shows the relationship of the BYPASS pin and each output. Table 1. BYPASS Function BYPASS Pin Yout Cout L Luminance Chrominance H Composite Composite Adaptive Vertical Enhancer Circuit The vertical enhancer circuit is an adaptive enhanced processing using two line memories. The adaptive LPF of the vertical enhancer circuit minimizes noise and dot–crawl. This block does not emphasize horizontal and vertical sync signals. Table 2 shows the relationship of the VH pin and the vertical enhancer function. The coring characteristics of the vertical enhancer circuit can be set up using the digital port in normal mode. Table 2. VH Function VH Pin Vertical Enhancer L On H Off D/A Converter The luminance and chrominance signals separated in the Advanced Comb Filter–II portion are converted to analog signals by two 8–bit D/A converters. The output voltage range is from 0.3 V to 1.5 V, 1.2 V p–p. The sampling clock of the D/A converter is 14.3 MHz/17.7 MHz. Clock Generation Circuit The block is a 4xFSC CLK generation circuit. It generates four times the subcarrier signal which locks the inputting subcarrier on the FSC pin at the normal (FSC) mode. At the other mode, the external 4xFSC clock should be input. MC141627 7 OUT OUT WHITE LEVEL (C4 – C7) (0 – 15 STEP) WHITE IN IN BLACK OUT OUT IN NOISE LEVEL (D4 – D7) (0 – 15 STEP) IN BLACK LEVEL (C0 – C3) (0 – 15 STEP) C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 Level L l L L L L L L L L L L H H L H L H 0 1 2 3 L L L L H H H H L L H H L H L H 4 5 6 7 H H H H L L L L L L H H L H L H 8 9 10 11 H H H H H H H H L L H H L H L H 12 13 14 15 Figure 2. Coring Characteristics OPERATING MODES The Advanced Comb Filter–II can be operated in any of three modes. These modes are fixed by a digital code input into MODE0 and MODE1. The descriptions of the four types of operating modes are: converter outputs. The clamp circuit operates as sync tip clamp by connecting CLout with Vin, and clamps the input video signal to the fixed value $04. The coring characteristics of the vertical enhancer circuit can be set up on the digital port. This mode operates the external 4xFSC CLK which is input on the FSC pin. Normal (FSC) Mode Digital Input Comb Filtering Mode This mode is for the normal Y/C separation. The video signal input to the A/D converter is separated into its Y and C components and output as analog information from the D/A converter outputs. The clamp circuit operates as sync tip clamp by connecting CLout with Vin, and clamps the input video signal to the fixed value $04. The coring characteristics of the vertical enhancer circuit can be set using the digital port. This mode operates the internal 4xFSC CLK which is generated by the built–in 4xFSC PLL. In this mode, the MC141627 uses only the filter and D/A portion. This mode can input 8–bit digital outputs from an external circuit. The 8–bit external digital data can be input into D0 – D7, and the input data is filtered by the Advanced Comb Filter–II algorithm, and one output as an analog signal from Yout and Cout. Table 3. Operating Mode Mode Normal (4xFSC) Mode This mode is for the normal Y/C separation. The video signal input to the A/D converter is separated into its Y and C components and output as analog information from the D/A MC141627 8 MODE1 MODE0 Normal (FSC) Mode L L Normal (4xFSC) Mode L H Digital Input Comb Filtering Mode H L MOTOROLA APPLICATION DESIGN CONSIDERATIONS VCC, GND To minimize noise effects for A/D, D/A, and all digital VCC and GND, wire up to the power supply separation. Leave the GND line as wide and short as possible. Furthermore, the wiring impedance should be as small as possible on the layout. To bypass noise, apply a high–capacity, high–performance frequency capacitor as close as possible to both analog and digital VCC and ground pins. A 0.1 µF multi–layer ceramic capacitor and a 47 µF tantalum capacitor are recommended. Vin In order to prevent flyback noise of the video input, it is necessary to keep the bandwidth to less than one half the clock frequency by using an area filter. Here the amplifier used as an input buffer needs a wide bandwidth and driving capability. Moreover, to minimize external noise effects, an input buffer should be driven by low impedance, and the Vin pin should be laid out as close as possible to the pattern layout. When using the built–in clamp circuit, connect CLout with Vin and input signals after ac coupling by using a high– performance capacitor. In this case, keep the Vin, CLout, coupling capacitor, and buffer–amplifier wiring as short as possible. Pay particular attention to external noise and parasitic impedance. A/D Reference Pin The RTP and RBT pins provide a self–bias function that internally generates VTP = 2.5 V and VBT = 0.5 V. Presetting the A/D converter analog input dynamic range. A stable performance is achieved by installing high–performance, high– frequency capacitance as close as possible to the RTP and RBT pins and bypassing to GND(AD). A 0.1 µF multi–layer ceramic capacitor and a 10 µF tantalum capacitor are recommended. CLC The CLC pin sets the clamp circuit speed with an external capacitor and resistor. Generally, the capacitor and resistor are arranged in a row and connected with GND(AD). Select a capacitor that minimizes the dielectric absorbing error. When the capacitor capacity is reduced, the shift speed of the VCR signal to VCC(AD) side is accelerated. When the resistor value is MOTOROLA reduced, the shift speed of the VCR signal to GND(AD) is accelerated. If the resistor value is too small at this point, sagging will appear in the VCR signal. Also, if the capacitor’s capacity is too large, the clamp speed will slow down; therefore, it is very important to adjust the values of the resistor and capacitance to match the application. D/A Reference REF(DA) is a D/A converter reference decoupling pin for both the Yout and Cout. Bypass to GND(DA) by applying a high–performance frequency capacitor as close to the pin as possible. A 0.1 µF multi–ceramic capacitor is recommended. Clock Input The clock frequency inputs 3.58 MHz/4.43 MHz during normal (FSC) mode, and 14.31818 MHz/17.734475 MHz during the other modes. The minimum input level is 1.0 V p–p. It should be phase–locked to the subcarrier of the video signal. The clock line should be wired with the shortest wire and be separated from other circuits to minimize cross coupling to other signals. The CLK(AD) pin is used only during digital input comb filtering mode; therefore, it should be in GND level except when the digital input comb filtering mode is selected. Ibias The Ibias pin is used to set up the bias current for the A/D and D/A converters. Connect an external resistor between the Ibias and GND(DA). Digital Input Comb Filtering Mode Connect CLK(AD) with the GND(D) when the A/D converter is not being used. Connect D0 – D7 with GND(D), when the D/A converter and filter are not being used. This is to eliminate any unnecessary operation of blocks which are not being used. At this point, make sure voltage is supplied to the VCC(AD), VCC(DA), and VCC(D). This eliminates latch–up during operating. Latch–Up The VCC(AD), VCC(DA), and VCC(D) pins are power supplies, independent from each other. Therefore, latch–up may occur when the power supply is turned on. To eliminate latch–up, turn on each power supply [VCC(AD), VCC(DA), and VCC(D) pins] simultaneously. MC141627 9 APPLICATION CIRCUIT 10 kΩ x 8 10 kΩ x 8 ADC GND DAC GND DIGITAL GND + VCC(D) 5V 47 kΩ x 8 TANTALUM CAPACITOR MULTI–LAYER CERAMIC CAPACITOR 47 kΩ x 8 C 47 k Ω x 4 33 µH 47 µF 75 Ω 20 CLK(AD) BYPASS 42 19 GND(D) GND(D) 43 18 VCC(D) VCC(D) 44 17 CLC FSC 45 16 CLout N/M 46 15 Vin PAL/NTSC 47 14 RBT Comb/BPF 48 13 RTP Cout + 1 – 8 7 4 + – 43 k Ω 47 µF 0.1 µF + 0.1 47 µF 2.2 kΩ µF 2.2 kΩ C2002 220 kΩ VCC(D) 8 C2002 + 1 – 4 4700 pF 3 2 2.2 kΩ MC14577 47 µF 2 kΩ 2 kΩ 1 kΩ 510 510 k A953 GAIN ADJUST + 0.1 10 µF µF + 0.1 µF 10 µF 33 µH 0.1 µF + 47 µF VCC(A) (5 V) 3 Vout 2 + 0.1 5 + 75 33 µH 12 VCC(AD) 10 11 GND(AD) 9 33 µH VIDEO IN 10 k Ω 8 I bias 7 REF(DA) 6 0.1 µ F 5 VCC(DA) Cout 4 + 10 µF 8 1/2MC14576 75 Ω 51 µF 3 Y out 2 GND(DA) MC141627 1.0 µF VCC(A) 10 V CLAMP LEVEL 41 0.1 µF 4 Yout C7 MODE0 VH PCO OVCC + C6 MODE1 21 100 33 µH C5 22 48 + 0.1 47 µF C4 39 D0 1 33 µH C3 D1 10 kΩ x 3 VDD(A) 10 V C2 TE0 SW VCC(D) 5V C0 TE1 23 33 µH CLK 29 28 27 26 25 24 D2 10 kΩ x 2 VCC(D) 5V 30 37 38 FILIN + 33 32 31 0.1 µF µF D3 0.1 µF BIAS 47 µF C1 36 35 34 D7 D6 D5 D4 + 47 ROTARY SW 10 µF µF VCC(A) (10 V) Vin MC7805CT 33 µH 4.7 µF + 0.1 µF 4.7 µF GND + 0.1 µF 6 2/2MC14576 MC141627 10 MOTOROLA EMI SUPPRESSION When using ICs in or near television receiver circuits, EMI (electromagnetic interference) and subsequent unwanted display artifacts and distortion are probable unless adequate EMI suppression is implemented. A common misconception is that some offending digital device is the culprit. This is erroneous in that an IC itself has insufficient surface area to produce sufficient radiation. The device, while it is the generator of interfering signals, must be coupled to an antenna before EMI is radiated. The source for the EMI is not the IC which generates the offending signals but rather the circuitry which is attached to the IC. Potential EMI signals are generated by all digital devices. Whether they become a nuisance is dependent upon their frequency and whether they have a sufficient antenna. The frequency and number of these signals is affected by both circuit design within the IC and the manufacturing process. Device speed is also a major contributor of potential EMI. Because the design is determined by the anticipated application, the manufacturing process is fixed and the drive for speed ever increasing, the only effective point to implement EMI suppression is in the PC board design. The PC board usually is the antenna which radiates the EMI. The most efficient method of minimizing EMI radiation is to minimize the efficiency of this antenna. The most common cause of inadequate EMI suppression lies with the ground system of the suspected digital devices. As pointed out previously, di/dt transitions can be significant in digital circuits. If the di/dt transitions appear in the ground system and the ground system is inductive, the harmonics present in these transitions are a source of potential EMI signals. The unfortunate result of putting digital devices on a reactive ground system is guaranteed EMI problems. The area which should be addressed first as a potential EMI source is the ground. Without an adequate ground system, EMI cannot be effectively reduced by decoupling. If at all possible, the ground should be a complete unbroken plane. Figure 5 shows two examples of relieving ground around device pins. When relieving vias and plated through holes, large areas of ground loss should be avoided. When the relief pattern is equal to half the distance between pins, over etching and process errors may remove ground between pins. If sufficient ground around enough pins are removed, the ground system can become isolated or nearly isolated “patches” which will appear inductive. If ground, such as the vicinity of an IC, must be removed, replace with a cross hatch of ground lines with the mesh as small as possible. If a single unbroken plane can be devoted to the ground system, EMI can usually be sufficiently suppressed by using ferrite beads on suspect EMI paths and decoupling with ade- MOTOROLA quate values of capacitors. The value of the decoupling capacitor depends on the frequency and amplitude of the offending signals. Ferrite beads are available in a wide variety of shape, size and material to fit virtually any application. Choose a ferrite bead for desired impedance at the desired frequency and construct a low pass filter using one or more appropriate capacitors in a “L”, “T” or “PI” arrangement. Use only capacitors of low inductive and resistive properties such as ceramic or mica. Install filters in series with each IC pin suspected of contributing offending EMI signals and as close to the pin as possible. Analysis using a spectrum analyzer can help determine which pins are suspect. Where PC board costs constrain the number of layers available, and if the EMI frequencies are far removed from the frequencies of operation, ferrite beads and decoupling capacitors may still be effective in reducing EMI emissions. Where only two (or in some cases, only one!) layer is used, the ground system is always reactive and poses an EMI problem. If the offending EMI and normal operating frequency differ sufficiently, filtering can still work. An “island” is constructed in the ground system for the digital device using ferrite beads and decoupling capacitors as shown by the example in Figure 6. The ground must be cut so that the digital ground for the device is isolated from the rest of the ground system. Next choose a ferrite bead of the appropriate value. Install this bead between the isolated ground and the ground system. Install low pass filters in all suspect lines with the capacitor closest to the device pin connected to the isolated ground in all signal lines where EMI is suspect. Also cut the power to the device and insert a ferrite bead as shown in Figure 6. Finally, decouple the device between the power pin(s) and isolated ground pin(s) using a low inductive/resistive capacitor of adequate value. The methods described above will work acceptably when the EMI frequency and the frequency of operation of the device generating the EMI differ greatly. Where the EMI is disturbing the high VHF or UHF channels and the device generating the EMI is operating within the NTSC/PAL bandwidth, the energy contained in the harmonics generating the EMI is situated well above the operating frequency and suppressing this type of EMI poses no great problem. However, if the EMI is present on low VHF channels and/or the operation of the device is outside the NTSC/PAL bandwidth, such as a 2X pixel clock or 4xFSC oscillator, compromise between video quality and suppression complexity is usually required to obtain an acceptable solution. For those cases where the operating frequency of the device is very near the frequency of the EMI disturbance, careful attention to PCB layout, multiple layer PCB and even shielding may be necessary to obtain an acceptable design. MC141627 11 WRONG BETTER Figure 3. FERRITE BEAD POWER INPUT OR OUTPUT SIGNAL FERRITE BEAD CUT LOW PASS FILTER 0.1 µF DECOUPLING GROUND CUT FERRITE BEAD Figure 4. MC141627 12 MOTOROLA PACKAGE DIMENSIONS FT SUFFIX QFP (QUAD FLAT PACKAGE) CASE 898–01 B P B Q J K R -A-, -B-, -D- ÉÉÉÉ ÉÉÉÉ D W 0.200 (0.008) X G DETAIL A DETAIL B M H A–B S D S SECTION B–B ROTATED 90° DETAIL A L 37 A–B A–B -B- -A- 12 25 13 24 -DA 0.200 (0.008) M C A–B 0.050 (0.002) A–B S D S S D S S 0.200 (0.008) M H A–B M C E -CH MOTOROLA -HY S H D V M B 0.200 (0.008) M C D 0.050 (0.002) D L 0.200 (0.008) 36 S 1 S S 48 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A- , -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H- . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C- . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H- . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.48 (0.019). DIM A B C D E G H J K L M P Q R S V W X Y MILLIMETERS MIN MAX 11.90 12.10 11.90 12.10 2.05 2.55 0.20 0.40 2.00 2.30 0.80 BASIC 0.00 0.30 0.10 0.20 0.65 1.05 8.80 BASIC 13° REF 0.40 BASIC 0° 7° 0.13 0.30 14.90 15.70 14.90 15.70 0.65 REF 1.60 REF 5° REF INCHES MIN MAX 0.469 0.476 0.469 0.476 0.026 0.041 0.081 0.100 0.079 0.091 0.031 BASIC 0.000 0.011 0.005 0.008 0.026 0.041 0.346 BASIC 13° REF 0.016 BASIC 0° 7° 0.006 0.011 0.587 0.618 0.587 0.618 0.026 REF 0.063 REF 5° REF DETAIL B MC141627 13 This page intentionally left blank. MC141627 14 MOTOROLA This page intentionally left blank. MOTOROLA MC141627 15 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC141627 16 ◊ *MC141627/D* MC141627/D MOTOROLA