SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 4.5-V to 5.5-V VCC Operation Max tpd of 5.5 ns at 5 V SN54ALS11A, . . . J OR W PACKAGE SN54AS11 . . . J PACKAGE SN74ALS11A, SN74AS11 . . . D, N, OR NS PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1B 1A NC VCC VCC 1C 1Y 3C 3B 3A 3Y 2A NC 2B NC 2C 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y NC 3C NC 3B 2Y GND NC 3Y 3A 1A 1B 2A 2B 2C 2Y GND SN54ALS11A, SN54AS11 . . . FK PACKAGE (TOP VIEW) 1C D D NC – No internal connection description/ordering information These devices contain three independent 3-input positive-AND gates. They perform the Boolean functions Y A • B • C or Y A B C in positive logic. + ) ) + ORDERING INFORMATION PDIP – N 0°C to 70°C SOIC – D SOP – NS –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA Tube SN74ALS11AN SN74AS11N SN74AS11N SN74ALS11AD Tape and reel SN74ALS11ADR Tube SN74AS11D Tape and reel SN74AS11DR CDIP – J Tube CFP – W Tube LCCC – FK SN74ALS11AN Tube Tape and reel Tube TOP-SIDE MARKING ALS11A AS11 SN74ALS11ANSR ALS11A SN74AS11NSR 74AS11 SNJ54ALS11AJ SNJ54ALS11AJ SNJ54AS11J SNJ54AS11J SNJ54ALS11AW SNJ54ALS11AW SNJ54ALS11AFK SNJ54ALS11AFK SNJ54AS11FK SNJ54AS11FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 FUNCTION TABLE (each gate) INPUTS A B C OUTPUT Y H H H H L X X L X L X L X X L L logic diagram, each gate (positive logic) 1A 1B 1C 2A 2B 2C 3A 3B 3C 1 2 13 12 3 4 5 6 9 10 11 8 1Y 2Y 3Y Pin numbers shown are for the D, J, N, NS, and W packages. absolute maximum ratings over operating SN74ALS11A) (unless otherwise noted)† free-air temperature range (SN54ALS11A, Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) SN54ALS11A VCC VIH Supply voltage High-level input voltage SN74ALS11A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 UNIT V V VIL Low level input voltage Low-level 0.8‡ 0.7§ IOH IOL High-level output current –0.4 –0.4 mA Low-level output current 4 8 mA 0.8 V TA Operating free-air temperature –55 125 0 70 °C ‡ Applies over temperature range –55°C to 70°C § Applies over temperature range 70°C to 125°C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54ALS11A TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –0.4 mA VOL 5V VCC = 4 4.5 IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, VI = 4.5 V VI = 0 MIN SN74ALS11A TYP† MAX MIN –1.5 VCC –2 0.25 –1.5 0.4 VCC –2 0.25 0.4 0.35 0.5 V V V 0.1 0.1 mA 20 20 µA –0.1 –20 UNIT –112 –30 –0.1 mA –112 mA mA 1 1.8 1 1.8 1.6 3 1.6 3 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V TO 5.5 V, CL = 50 PF, RL = 500 Ω, TA = MIN TO MAX§ SN54ALS11A MIN tPLH tPHL A B A, B, or C Y UNIT SN74ALS11A MAX MIN MAX 2 14 2 13 2 12.5 2 10 ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. absolute maximum ratings over operating free-air temperature range (SN54AS11, SN74AS11) (unless otherwise noted)¶ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ¶ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 recommended operating conditions (see Note 2) SN54AS11 SN74AS11 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –2 –2 mA IOL TA Low-level output current 20 20 mA 70 °C High-level input voltage 2 Operating free-air temperature 2 –55 125 V V 0 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –2 mA VOL II VCC = 4.5 V, VCC = 5.5 V, IOL = 20 mA VI = 7 V IIH IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 2.7 V VI = 0.4 V VCC = 5.5 V, VCC = 5.5 V, VO = 2.25 V VI = 4.5 V ICCH ICCL SN54AS11 TYP† MIN SN74AS11 TYP† MAX MIN –1.2 MAX –1.2 VCC–2 VCC–2 0.35 –30 0.5 V V 0.35 0.5 V 0.1 0.1 mA 20 20 µA –0.5 –0.5 mA –112 mA 7 mA –112 4.3 UNIT –30 7 4.3 VCC = 5.5 V, VI = 0 11.2 18 11.2 18 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) A B A, B, or C TO (OUTPUT) Y VCC = 4.5 V TO 5.5 V, CL = 50 PF, RL = 500 Ω, TA = MIN TO MAX§ SN54AS11 SN74AS11 MIN MAX MIN 1 6.5 1 6 1 6.5 1 5.5 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX ns SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ tPHZ 1.3 V 1.3 V 0.3 V tPHL ≈3.5 V tPLH VOL 0.3 V VOH 1.3 V 3.5 V Input 1.3 V tPZH Waveform 2 S1 Open (see Note B) 1.3 V 0.3 V ≈0 V VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-86841012A ACTIVE LCCC FK 20 1 TBD 5962-8684101CA ACTIVE CDIP J 14 1 TBD 5962-8684101DA ACTIVE CFP W 14 1 TBD 5962-9756101Q2A ACTIVE LCCC FK 20 1 TBD 5962-9756101QCA ACTIVE CDIP J 14 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type JM38510/37402B2A ACTIVE LCCC FK 20 1 TBD JM38510/37402BCA ACTIVE CDIP J 14 1 TBD POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type SN54ALS11AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type N / A for Pkg Type SN54AS11J ACTIVE CDIP J 14 1 TBD A42 SNPB SN74ALS11AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS11ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS11ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS11ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AS11NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AS11NSR ACTIVE SO NS 14 CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AS11NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS11NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54ALS11AFK ACTIVE LCCC FK 20 1 TBD Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) POST-PLATE N / A for Pkg Type SNJ54ALS11AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SNJ54ALS11AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type SNJ54AS11FK ACTIVE LCCC FK 20 1 TBD SNJ54AS11J ACTIVE CDIP J 14 1 TBD POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALS11ADR Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ALS11ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74AS11DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AS11NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS11ADR SOIC D 14 2500 346.0 346.0 33.0 SN74ALS11ANSR SO NS 14 2000 346.0 346.0 33.0 SN74AS11DR SOIC D 14 2500 346.0 346.0 33.0 SN74AS11NSR SO NS 14 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 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