ONSEMI MC100H642

MC10H642, MC100H642
68030/040 PECL to TTL
Clock Driver
Description
The MC10H/100H642 generates the necessary clocks for the
68030, 68040 and similar microprocessors. It is guaranteed to meet the
clock specifications required by the 68030 and 68040 in terms of
part−to−part skew, within−part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H642 also uses differential PECL internally to achieve its
superior skew characteristic.
The H642 includes divide−by−two and divide−by−four stages, both
to achieve the necessary duty cycle skew and to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Diagram).
The 10H version is compatible with MECL 10H™ ECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0 V).
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxH642G
Features
•
•
•
•
•
•
•
AWLYYWW
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0 V Supply
Pb−Free Packages are Available*
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Function
Reset(R): LOW on RESET forces all Q outputs LOW.
Select(SEL): LOW selects the ECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H642 also contains circuitry to force a stable input state of the
ECL differential input pair, should both sides be left open. In this Case,
the DE side of the input is pulled LOW, and DE goes HIGH.
Power Up: The device is designed to have positive edges of the ÷2
and ÷4 outputs synchronized at Power Up.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC10H642/D
MC10H642, MC100H642
VT
VT
Q1
GT
GT
Q0
VT
25
24
23
22
21
20
19
TTL Outputs
Q7
Q2
26
18
VBB
GT
27
17
DE
GT
28
16
DE
Q3
1
15
VE
VT
2
14
R
VT
3
13
GE
Q4
4
12
DT
Q6
TTL/ECL Clock Inputs
VBB
Q5
DE
DE
MUX
÷4
Q4
DT
Q3
SEL
5
6
7
8
9
10
11
Q5
GT
GT
Q6
Q7
VT
SEL
Q2
TTL Control Inputs
Figure 1. Pinout: PLCC−28
(Top View)
÷2
Q0
R
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Symbol
81
82
83
84
85
86
87
88
89
10
11
12
13
14
Q3
VT
VT
Q4
Q5
GT
GT
Q6
Q7
VT
SEL
DT
GE
R
Q1
Description
Signal Output (TTL)**
TTL VCC (+5.0 V)
TTL VCC (+5.0 V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL Ground (0 V)
TTL Ground (0 V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL VCC (+5.0 V)
Input Select (TTL)
TTL Signal Input
ECL Ground (0 V)
Reset (TTL)
Pin
Symbol
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VE
DE
DE
VBB
VT
Q0
GT
GT
Q1
VT
VT
Q2
GT
GT
* Divide by 2
**Divide by 4
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2
Description
ECL VCC (+5.0 V)
ECL Signal Input (Non−Inverting)
ECL Signal Input (Inverting)
VBB Reference Output
TTL VCC (+5.0 V)
Signal Output (TTL)*
TTL Ground (0 V)
TTL Ground (0 V)
Signal Output (TTL)*
TTL VCC (+5.0 V)
TTL VCC (+5.0 V)
Signal Output (TTL)**
TTL Ground (0 V)
TTL Ground (0 V)
MC10H642, MC100H642
Table 2. 10H PECL CHARACTERISTICS (VT = VE = 5.0 V ± 5%)
TA = 0°C
Symbol
Characteristic
Min
Condition
IINH
IINL
Input HIGH Current
Input LOW Current
VIH
VIL
Input HIGH Voltage (Note 1)
Input LOW Voltage (Note 1)
VBB
Output Reference Voltage (Note 1)
0.5
VEE = 5.0 V
Max
255
TA = 25°C
Min
0.5
Max
175
TA = 85°C
Min
0.5
Max
Unit
175
mA
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
3.555
V
3.62
3.73
3.65
3.75
3.69
3.81
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0 V.
Table 3. 100H PECL CHARACTERISTICS (VT = VE = 5.0 V ± 5%)
TA = 0°C
Symbol
Characteristic
Min
Condition
IINH
IINL
Input HIGH Current
Input LOW Current
VIH
VIL
Input HIGH Voltage (Note 2)
Input LOW Voltage (Note 2)
VBB
Output Reference Voltage (Note 2)
0.5
VEE = 5.0 V
Max
255
TA = 25°C
Min
0.5
Max
175
TA = 85°C
Min
0.5
Max
Unit
175
mA
3.835
3.190
4.120
3.525
3.835
3.190
4.120
3.525
3.835
3.190
4.120
3.525
V
3.620
3.740
3.620
3.740
3.620
3.740
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0 V.
Table 4. 10H/100H DC CHARACTERISTICS (VT = VE = 5.0 V ± 5%)
TA = 0°C
Symbol
IEE
ICCH
Characteristic
Power Supply Current
Condition
Min
Max
TA = 25°C
Min
Max
TA = 85°C
Min
Max
Unit
PECL
VE Pin
57
57
57
mA
TTL
Total All VT Pins
30
30
30
mA
30
30
30
mA
ICCL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10H642, MC100H642
Table 5. 10H/100H TTL DC CHARACTERISTICS (VT = VE = 5.0 V ± 5%)
TA = 0°C
Symbol
Characteristic
Min
Condition
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
2.0
IIH
Input HIGH Current
VIN = 2.7 V
VIN = 7.0 V
IIL
Input LOW Current
VIN = 0.5 V
VOH
Output HIGH Voltage
IOH = −3.0 mA
IOH = −15 mA
VOL
Output LOW Voltage
IOL = 24 mA
VIK
Input Clamp Voltage
IIN = −18 mA
IOS
Output Short Circuit Current
VOUT = 0 V
Max
0.8
TA = 25°C
Min
2.0
20
100
0.8
−225
−100
Unit
V
20
100
mA
−0.6
mA
V
0.5
−1.2
−100
Max
2.5
2.0
0.5
−1.2
−225
2.0
−0.6
2.5
2.0
0.5
−100
0.8
TA = 85°C
Min
20
100
−0.6
2.5
2.0
Max
V
−1.2
V
−225
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS (VT = VE = 5.0 V ± 5%)
TA = 0°C
Symbol
Characteristic
Condition
Q2−Q7
C ECL
C TTL
CL = 25 pF
TA = 25°C
TA = 85°C
Min
Max
Min
Max
Min
Max
4.70
4.70
5.70
5.70
4.75
4.75
5.75
5.75
4.60
4.50
5.60
5.50
Unit
tPLH
Propagation Delay
D to Output
tskpp
Part−to−Part Skew
tskwd*
Within−Device Skew
tPLH
Propagation Delay
D to Output
Q0, Q1
C ECL
C TTL
CL = 25 pF
tskpp
Part−to−Part Skew
All
Outputs
CL = 25 pF
2.0
2.0
2.0
ns
tskwd
Within−Device Skew
CL = 25 pF
1.0
1.0
1.0
ns
tPD
Propagation Delay
R to Output
All
Outputs
CL = 25 pF
6.5
ns
tR
tF
Output Rise/Fall Time
0.8 V to 2.0 V
All
Outputs
CL = 25 pF
2.5
2.5
ns
fMAX**
Maximum Input Frequency
RPW
RRT
4.30
4.30
4.3
1.0
1.0
1.0
ns
0.5
0.5
0.5
ns
5.30
5.30
6.3
4.50
4.50
4.0
2.5
2.5
CL = 25 pF
ns
5.50
5.50
6.0
4.25
4.25
4.5
2.5
2.5
5.25
5.25
ns
100
100
100
MHz
Reset Pulse Width
1.5
1.5
1.5
ns
Reset Recovery Time
1.25
1.25
1.25
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
* Within−Device Skew defined as identical transactions on similar paths through a device.
**MAX Frequency is 135 MHz.
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4
MC10H642, MC100H642
10/100H642 − DUTY CYCLE CONTROL
To maintain a duty cycle of ±5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures
1 and 2. For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature.
Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.
Best duty cycle control is obtained with a single mP load and minimum line length.
11
NEGATIVE PULSE WIDTH (ns)
POSITIVE PULSE WIDTH (ns)
11
4.75
10
5.00
5.25
9
9
0
10
20
30
40
50
4.75
5.00
5.25
10
60
0
10
20
30
40
50
CAPACITIVE LOAD (pF)
60
CAPACITIVE LOAD (pF)
Figure 4. MC10H642 Negative PW versus Load
@ ±5% VCC, TA = 25°C
10.6
10.8
10.4
10.6
NEGATIVE PULSE WIDTH (ns)
POSITIVE PULSE WIDTH (ns)
Figure 3. MC10H642 Positive PW versus Load
@ ±5% VCC, TA = 25°C
10.2
4.875
10.0
5.00
9.8
5.125
9.6
0
10
20
30
40
CAPACITIVE LOAD (pF)
50
5.00
10.0
5.125
9.8
9.4
60
0
50
60
10.5
NEGATIVE PULSE WIDTH (ns)
10.4
10.2
10.0
0 pF
25 pF
50 pF
9.8
9.6
9.4
10 CAPACITIVE
20
30 (pF) 40
LOAD
Figure 6. MC10H642 Negative PW versus Load
@ ±2.5% VCC, TA = 25°C
Figure 5. MC10H642 Positive PW versus Load
@ ±2.5% VCC, TA = 25°C
POSITIVE PULSE WIDTH (ns)
4.875
10.2
9.6
9.4
9.2
10.4
0
20
40
60
TEMPERATURE (°C)
80
10.3
10.1
0 pF
25 pF
50 pF
9.9
9.7
9.5
0
100
Figure 7. MC10H642 Positive PW versus Temperature,
VCC = 5.0 V
20
40
60
TEMPERATURE (°C)
80
100
Figure 8. MC10H642 Negative PW versus
Temperature, VCC = 5.0 V
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5
MC10H642, MC100H642
6.2
Tpd (ns)
6.0
5.8
4.75
5.00
5.6
5.25
5.4
5.2
0
10
20
30
40
50
60
CAPACITIVE (pF)
Figure 9. MC10H642 + Tpd versus Load, VCC ±5%, TA = 25°C
(Overshoot at 50 MHz with no load makes graph non linear)
DT
RESET, R
R
trec
R
Q0
Q1
Q2
Q7
tpw
MC10/100H642
Figure 10. Clock Phase and Reset Recovery Time After Reset Pulse
MC10/100H642
Din
Q0.Q1
Q4 & Q5
Q2
Q7
After Power Up
Figure 11.
Outputs
Q2
Q7 will Synchronize with Pos Edges of Din & Q0
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6
Q1
MC10H642, MC100H642
Switching Circuit PECL:
VEE
PECL
VCC & VCCO
TTL
USE 0.1 mF CAPACITORS
FOR DECOUPLING.
+7 V
50 W COAX
IN
PULSE
GENERATOR
DEVICE
UNDER
TEST
OPEN
OUT
ALL
OTHERS
450 W
tPZL, tPLZ
50 Ω COAX
50 Ω COAX
R1
500 W
DEVICE
UNDER
TEST
R2
500 W
50 pF
USE OSCILLOSCOPE
INTERNAL 50 W LOAD
FOR TERMINATION.
CH A
CH B
OSCILLOSCOPE
Figure 12. Switching Circuit and Waveforms
PECL/TTL
PECL/TTL
50%/1.5 V
Vin
80%/2.0 V
20%/0.8 V
Vout
Tpd++
Tpd−−
50%/1.5 V
Trise
Tfall
Vout
Figure 14. Waveforms: Rise and Fall Times
Figure 13. Propagation Delay — Single−Ended
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7
MC10H642, MC100H642
ORDERING INFORMATION
Package
Shipping †
MC10H642FN
PLCC−28
37 Units / Rail
MC10H642FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10H642FNR2
PLCC−28
500 / Tape & Reel
MC10H642FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100H642FN
PLCC−28
37 Units / Rail
MC100H642FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100H642FNR2
PLCC−28
500 / Tape & Reel
MC100H642FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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8
MC10H642, MC100H642
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
B
Y BRK
−N−
0.007 (0.180)
U
T L−M
M
0.007 (0.180)
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
G1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
H
0.007 (0.180)
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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9
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10H642, MC100H642
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
MC10H642/D