HCF40103B 8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS ■ ■ ■ ■ ■ ■ ■ ■ SYNCHRONOUS OR ASYNCHRONOUS PRESET MEDIUM -SPEED OPERATION : fCL =3.6MHz (Typ.) at VDD = 10V CASCADABLE QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF40103B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40103B consists of an 8-stage synchronous down counter with a single output that is active when the internal count is zero. This device contains a single 8-bit binary counter. It has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO DETECT output are active-low logics. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/ DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF40103BEY HCF40103BM1 HCF40103M013TR CE) input is high. The CARRY-OUT/ZERO DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESET ENABLE (APE) input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 represent a single 8 bit binary word. When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (25510) regardless of the state of any other input. The precedent relationship between control input is indicated in the truth table. If all control PIN CONNECTION September 2002 1/14 HCF40103B inputs are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. HCF40103B may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode. IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 CLOCK 2 CLEAR 3 4, 5, 6, 7, 10, 11, 12, 13 CI/CE J0 to J7 NAME AND FUNCTION Clock Input (LOW to HIGH edge triggered) Asynchronous Master Reset Input (Active Low) Terminal Enable Input Jam Inputs Asynchronous Preset Enable Inputs(Active Low) Terminal Count Output (Active Low) Synchronous Preset Enable Input (Active Low) 9 APE 14 CO/ZD 15 SPE 8 VSS Negative Supply Voltage 16 VDD Positive Supply Voltage FUNCTIONAL DIAGRAM TRUTH TABLES CONTROL INPUTS PRESET MODE CLR APE SPE CI/CE H H H H L H H H L X H H L X X H L X X X Synchronous Asynchronous X : Don’t Care Clock connected to Clock input Synchronous Operation : changes occur on negative to positive clock transitions. 2/14 ACTION Inhibit Counter Count Down Preset on Next Positive Clock Transition Preset Asynchronously Clear to Maximum Count HCF40103B LOGIC DIAGRAM LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7 3/14 HCF40103B TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage Value Unit -0.5 to +22 V VI DC Input Voltage -0.5 to VDD + 0.5 V II DC Input Current ± 10 mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C PD Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/14 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF40103B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 µA V 3.5 7 11 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 5/14 HCF40103B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPHL tPLH Propagation Delay Time Clock To Out tPHL tPLH Propagation Delay Time Carry In/counter Enable To Output tPHL tPLH Propagation Delay Time Asynchronous Preset Enable To Output tPHL tPLH Propagation Delay Time Clear To Output tTHL tTLH Transition Time tW tW tW tsetup tsetup fCL Clock Pulse Width Clear Pulse Width APE Pulse Width SPE Setup Time JAM Setup Time Maximum Clock Input Frequency VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. 6/14 Value (*) Unit Min. Typ. Max. 600 260 190 400 180 130 1300 600 400 750 360 200 200 100 80 300 180 80 320 160 100 360 160 120 280 140 100 200 80 60 0.7 1.8 2.4 300 130 95 200 90 65 650 300 200 375 180 100 100 50 40 150 90 40 160 80 50 180 80 60 140 70 50 100 40 30 1.4 3.6 4.8 ns ns ns ns ns ns ns ns ns ns MHz HCF40103B TYPICAL APPLICATIONS DIVIDE BY "N" COUNTER SYNCHRONOUS CASCADING MICROPROCESSOR INTERRUPT TIMER SYNCHRONOUS CASCADING MICROPROCESSOR INTERRUPT TIMER * An Output spike (160ns at VDD = 5V) occurs whenever two or more devices are cascaded in the parallel clocked mode because the clock-to-carry out delay is greater than the carry-in-to-carry-out delay. This spike is eliminated by gating the output of the last device with the clock as shown. 7/14 HCF40103B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 8/14 HCF40103B WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) 9/14 HCF40103B WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 10/14 HCF40103B WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 11/14 HCF40103B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 12/14 HCF40103B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 13/14 HCF40103B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 14/14