M54HC373 RAD-HARD OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 12ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 373 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9203-059 DESCRIPTION The M54HC373 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with sub-micron silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). DILC-20 FPC-20 ORDER CODES PACKAGE FM EM DILC FPC M54HC373D M54HC373K M54HC373D1 M54HC373K1 While the LE input is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and when OE is in high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION May 2004 Rev. 1 1/11 M54HC373 Figure 1: IEC Logic Symbols Figure 2: Input And Output Equivalent Circuit Table 1: Pin Description PIN N° SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 Q0 to Q7 3 State Output Enable Input (Active LOW) 3 State Outputs D0 to D7 Data Inputs LE GND VCC NAME AND FUNCTION Latch Enable Input Ground (0V) Positive Supply Voltage Table 2: Truth Table INPUTS OE LE D Q H L L L X L H H X X L H Z NO CHANGE (*) L H X: Don’t Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. 2/11 OUTPUTS M54HC373 Figure 3: Logic Diagram Table 3: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ± 70 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V 420 mW -65 to +150 °C 265 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 4: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time tr, tf Value Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns 3/11 M54HC373 Table 5: DC Specifications Test Condition Symbol VIH VIL VOH VOL II IOZ ICC 4/11 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 Unit V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-6.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-7.8 mA 5.68 5.8 5.63 5.60 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 V V 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=6.0 mA 0.17 0.26 0.33 0.40 6.0 IO=7.8 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA 6.0 VI = VCC or GND 4 40 80 µA V M54HC373 Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (LE, D - Q) tPZL tPZH High Impedance Output Enable Time tPLZ tPHZ High Impedance Output Disable Time tW(H) ts th Minimum Pulse Width (LE) Minimum Set-up Time Minimum Hold Time VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value TA = 25°C CL (pF) Min. 50 50 150 50 RL = 1 KΩ 150 RL = 1 KΩ 50 RL = 1 KΩ 50 50 Typ. Max. 25 7 6 42 14 12 57 19 16 39 13 11 54 18 15 30 14 13 15 6 6 16 4 3 60 12 10 125 25 21 175 35 30 125 25 21 175 35 30 125 25 21 75 15 13 50 10 9 5 5 5 50 -40 to 85°C -55 to 125°C Min. Min. Max. 75 15 13 155 31 26 220 44 37 155 31 26 220 44 37 155 31 26 95 19 16 65 13 11 5 5 5 Unit Max. 90 18 15 190 38 32 265 53 45 190 38 32 265 53 45 190 38 32 110 22 19 75 15 13 5 5 5 ns ns ns ns ns ns ns ns ns Table 7: Capacitive Characteristics Test Condition Symbol Parameter CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD VCC (V) Value TA = 25°C Min. Typ. Max. 5 10 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF 10 pF 38 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 22 + 16 x n (pF) 5/11 M54HC373 Figure 4: Test Circuit TEST tPLH, tPHL SWITCH Open tPZL, tPLZ VCC tPZH, tPHZ GND CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 5: Waveform - LE To Qn Propagation Delays, Le Minimum Pulse Width, Dn To Le Setup And Hold Times (f=1MHz; 50% duty cycle) 6/11 M54HC373 Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Propagation Delay Times (f=1MHz; 50% duty cycle) 7/11 M54HC373 DILC-20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 2.1 2.71 0.083 0.107 a1 3.00 3.70 0.118 0.146 a2 0.63 0.88 1.14 0.025 0.035 0.045 B 1.93 2.03 2.23 0.076 0.080 0.088 b 0.40 0.45 0.50 0.016 0.018 0.020 b1 0.20 0.254 0.30 0.008 0.010 0.012 D 25.14 25.40 25.65 0.990 1.000 1.010 e 7.36 7.62 7.87 0.290 0.300 0.310 e1 2.54 0.100 e2 22.73 22.86 22.99 0.895 0.900 0.905 e3 7.62 7.87 8.12 0.300 0.310 0.320 F 7.29 7.49 7.70 0.287 0.295 0.303 I 3.86 K 11.30 L 1.14 1.27 0.152 11.56 0.445 1.40 0.045 0.455 0.050 0.055 0016178J 8/11 M54HC373 FPC-20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 9.98 10.16 10.34 0.393 0.400 0.407 B 9.98 10.16 10.34 0.393 0.400 0.407 C 1.45 1.61 1.78 0.57 0.63 0.070 D 0.10 0.127 0.18 0.004 0.005 0.007 E 11.30 11.43 11.56 0.445 0.450 0.455 F 1.27 G 0.38 H 0.48 0.015 7.24 8.16 0.285 0.320 L 24.46 26.67 0.960 1.050 M 0.45 0.55 0.018 N 0.43 0.050 0.50 7.87 0.017 0.020 0.019 0.022 0.310 O 1.14 1.27 1.40 0.045 0.050 0.055 P 0.10 0.18 0.25 0.004 0.007 0.010 016032F 9/11 M54HC373 Table 8: Revision History Date Revision 10-May-2004 1 10/11 Description of Changes First Release M54HC373 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 11/11