STMICROELECTRONICS STI5300

STi5300
High-performance set-top box decoder
DATA BRIEF
DESCRIPTION
The new STi5300 MPEG-2 decoder from ST
provides a step-change in performance for pay TV
set-top boxes and digital video recorders.
Delivering 1.33 GOPS of processing power
through an ST230 VLIW CPU running at 333 MHz,
ST has ensured that manufacturers’ investment in
new products is protected as the STi5300 can
easily accommodate today’s interactive software,
and provides a platform that can support the even
more demanding applications of the future. Both
Linux and OS21 operating systems are supported,
and an MMU provides support for virtual memory
management.
The STi5300’s power comes from the VLIW
architecture of the ST230 CPU. This allows four
instructions to be executed at each CPU cycle,
dramatically
increasing
performance.
By
maintaining pin compatibility with the STi5100,
manufacturers can make use of the STi5300 with
minimal hardware redesign.
Package (27 x 27 PBGA 336 package)
xxxx
Figure 1. STi5300 low-cost interactive set-top box
IR Tx/Rx
HDD
128 Mbit
DDR
QPSK ZIF Rx
Transport
stream in
STV0299
and
STB6000
RGB
STi5300
QPSK ZIF Rx
STV0299
and
STB6000
USB
port
Transport
stream in
CVBS/YC
VCR
(Optional)
PSTN
SiLabs
DAA
Smart
Smart
Cards
cards
Flash
Rev. 1
September 2005
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STI5300
FEATURES
■ ST231 VLIW host CPU
■
PAL/NTSC/SECAM encoder
– RGB, CVBS, Y/C and YUV outputs with
10-bit DACs
– 333 MHz, 32 Kbyte ICache,
32 Kbyte DCache
– encoding of CGMS, Teletext, WSS, VPS,
close caption
– up to 1.333 GOPs at 333 MHz
– dynamic memory management through MMU
■
Audio subsystem
■
Unified memory interface
– MPEG-1 layers I/II, MP3
■
Package 27 mm x 27 mm PBGA336
– Dolby® Digital decoding
– footprint optimized for 2 layer PCBs
– Dolby Pro Logic® compatible output
Dual transport stream merger
– PCM input, mixing and sample rate
conversion
■
– supports DVB and DIRECTV®
– SRS/TruSurroundXT® virtual surround sound
– integrated DES-ECB, DVB and ICAM
descramblers
– simultaneous MPEG audio decode and
output of Dolby streams
– NDS RASP compliant
– low-cost DVB-CI and Cable Card support
■
■
■
On-chip peripherals
MPEG-2 [email protected] video decoder
– 4 ASCs (UARTs) with Tx and Rx FIFOs
– trick modes including smooth fast forward
and rewind
– 6 parallel 8-bit I/O banks
Graphics/display
– 3 SSCs for I2C/SPI master/slave interfaces
– 4 display planes
– SiLabs line side (DAA) interface
– 2, 4 and 8 bpp CLUT graphics, 256 x 30 bits
(AYCBCr) CLUT entries
– USB 1.1/2.0 host, OHCI/EHCI compliant
– 16 bpp true color graphics,
– 2 smartcard interfaces and clock generators
– DiSEqC 2.0™ interface
■
Enhanced security
– alpha blending, antialiasing, antiflutter,
antiflicker filters
PART NUMBERING
Table 1. Order codes
Part Number
Description
STi5300ZUA
Development version
STi5300AUA
Basic DVB
STi5300-Mboard
Development platform
STi5300-DVB
Software reference tree
REVISION HISTORY
Table 2. Revision history
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Date
Revision
September-2005
1
Description of changes
First issue
STI5300
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2005 STMicroelectronics - All rights reserved
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