STLC4560
Single chip 802.11b/g WLAN radio
Data Brief
Features
■
Extremely small footprint
■
Ultra low power consumption
■
Fully compliant with the IEEE 802.11b and
802.11g WLAN standards
■
Support for 54, 48, 36, 24, 18, 12, 9, and
6 Mbit/s OFDM, 11 and 5.5 Mbit/s CCK and
legacy 2 and 1 Mbit/s data rates
■
LFBGA240 (8.5x8x1.4mm)
Description
The STLC4560 is a single chip 802.11b/g WLAN
radio for embedded, low-power and very small
form factor mobile applications. The product
conforms to the IEEE 802.11b and 802.11g
protocols operating in the 2.45 GHz ISM
frequency band supporting OFDM data rates of
54, 48, 36, 24, 18, 12, 9, and 6 Mbit/s as well as
CCK data rates of 11 and 5.5 Mbit/s and legacy
data rates of 2 and 1 Mbit/s.
Single chip 802.11b/g WLAN solution with fully
integrated:
– zero IF (ZIF) transceiver
– voltage controlled oscillator (VCO)
– high-speed A/D and D/A converters
– OFDM and CCK baseband processor
– ARM9 media access controller (MAC)
– Mode selectable SPI or SDIO host interface
(up to 48 Mbps)
– passive components integration
– PA bias control
– flexible integrated power management unit
– glueless FEM interface
■
Intelligent power control, including 802.11
power save mode
■
Fully integrated Bluetooth coexistence
The STLC4560 is a fully integrated wireless radio
including a ZIF transceiver, RF Synthesizer/VCO,
high-speed data converters, an OFDM/CCK
digital baseband processor, an ARM9-based
MAC and a complete power management unit
with integrated PA bias control. In addition some
passive components are integrated further
reducing the overall reference design cost and
size. An external FEM completes a highly
integrated chip set solution.
Applications
■
Cellular phones
■
Personal digital assistants (PDA)
■
Portable computers
■
Hand-held data transfer devices
■
Cameras
■
Computer peripherals
■
Cable replacement
January 2008
Host control is provided by a flexible SPI or SDIO
serial interface. The SPI interface supports a
maximum clock rate of 48 MHz whereas the 4-bit
SDIO supports a maximum clock rate of 25 MHz.
For maximum flexibility, the STLC4560 accepts
system reference clock frequencies of 19.2, 26,
38.4 and 40 MHz. A reference design evaluation
platform of hardware and software is provided to
system integrators to rapidly enable wireless
connectivity to mobile platforms.
Rev 1
For further information contact your local STMicroelectronics sales office.
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www.st.com
8
Block diagram
STLC4560
1
Block diagram
Figure 1.
Block diagram
STLC4560
Power management unit (PMU)
RF ZIF section:
FEM:
PA, switches,
Balun,
passives
FEM I/F
RF VCO
Rx down converters
Tx up converters
baseband filters
High speed
data converters
Switch control
2/8
Baseband
processor
OFDM/CCK
modulation
SPI I/F
Host
CPU
CXS I/F
Bluetooth
device
MAC
ARM9
WEP
STLC4560
Electrical characteristics
2
Electrical characteristics
Table 1.
Absolute maximum ratings
Symbol
VCC
Parameter
Test condition
PMU VBATT
Voltage on any other pin
VCC to VCC
Within shared voltage
rails
Any GND to GND
Table 2.
Symbol
TOP
VBATT
supply
VDIG
Min.
Typ.
Max.
Unit
-0.3
-
7.0
V
-0.3
-
Vcc + 0.3
V
-0.3
-
+0.3
V
-0.3
-
+0.3
V
Min.
Typ.
Max.
Unit
85
oC
5.5
V
Operating conditions and input power specifications
Parameter
Test condition
Operating temperature
range
-30
Input supply voltage
Power management unit
VBATT supply input
Average standby mode
current
VBATT = 3.6 V
Input supply voltage
SWx (x={1, 2, 3, 4})
supply input
3.0
3.6
μA
10
1.7
VBATT
V
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Electrical characteristics
Table 2.
Symbol
STLC4560
Operating conditions and input power specifications (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
Input supply voltage
Power management unit
VBATT supply input
3.0
3.6
5.5
V
Standby current
25 oC, POWER_UP = 0V.
The resulting current is
mainly leakage
10
μA
Sleep mode current
25 oC, POWERUP = 1.86
V. The radio is operating
on the sleep clock at
32.768 kHz. Sleep mode
is a subset of PSM.
120
μA
25 oC, 100 ms Beacon
period,
75 byte Beacons
Power save mode current
@ 1 Mbit/s, short
preamble, DTIM = 6
610
μA
Receive or Idle current
25 oC, the radio is always
on, receiving beacons,
no TX
195
mA
PSM Receive current
25 oC, PSM, receiving
packets at 1.9Mbit/s at
the application layer
76
mA
Transmit current
25 oC, the radio is always
on, transmitting 1.9Mbit/s
at the application layer
199
mA
PSM Transmit current
25 oC, PSM, transmitting
1.9Mbit/s at the
application layer
49
mA
Input supply voltage
VIO input supply
determines host CMOS
logic levels for:
SPI_CSX, SPI_CLK,
SPI_DIN, SPI_DOUT,
HOST_IRQ,
LF_XTAL_IN, FREQ,
RF_ACTIVE, STATUS,
TX_CONF
Input supply current
VIO = 1.86 V
Power consumption
VBATT
Supply
VIO
4/8
1.62
1.86
1.98
V
0.5
6
mA
STLC4560
3
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5/8
Package mechanical data
Figure 2.
STLC4560
LFBGA240 mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
A
A1
MAX.
MIN.
TYP.
1.4
0.15
MAX.
0.055
0.006
A2
1.065
0.042
A3
0.28
0.011
A4
0.8
0.031
b
0.25
0.3
0.35
0.010
0.012
0.014
D
8.35
8.5
8.65
0.329
0.335
0.341
D1
E
7.5
7.85
OUTLINE AND
MECHANICAL DATA
8
0.295
8.15
0.309
0.315
E1
7
0.276
e
0.5
0.020
F
0.5
0.020
0.321
Body: 8.5 x 8 x 1.4mm
ddd
0.08
0.003
eee
0.15
0.006
fff
0.05
0.002
LFBGA240
Low Profile Ball Grid Array
7870466 A
6/8
STLC4560
4
Ordering information
Ordering information
Table 3. Ordering information
Operating
temperature range
Package
STLC4560TRAY
-30°C to 85°C
LFBGA240- (8.5x8x1.4mm)
Tray
STLC4560
-30°C to 85°C
LFBGA240- (8.5x8x1.4mm)
Tape and reel
Order codes
5
Packing
Revision history
Table 4.
Document revision history
Date
Revision
09-Jan-2008
1
Changes
Initial release.
7/8
STLC4560
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