STMICROELECTRONICS STPM01FTR

STPM01
Programmable single phase energy metering IC
with tamper detection
Feature summary
■
Active, reactive, apparent energies and RMS
values
■
Ripple free active energy pulsed output
■
Live and neutral monitoring for tamper
detection
■
Easy and fast digital calibration in only one
point over the whole current range
■
OTP for calibration and configuration
■
Integrated linear VREGS for digital and analog
supply
TSSOP20
system control, oscillator, hard wired DSP and
SPI interface.
■
Selectable RC or crystal oscillator
■
Support 50÷60 HZ – IEC62052-11, IEC620532x specification
■
Less than 0.1% error
■
Precision voltage reference:
1.23V and 30 ppm/°C Max
Description
The STPM01 is designed for effective
measurement of active, reactive and apparent
energy in a power line system using Rogowski
Coil, Current Transformer and Shunt sensors.
This device can be implemented as a single chip
1-phase energy meter or as a peripheral
measurement in a microcontroller based 1-phase
or 3-phase energy meter. The STPM01 consists,
essentially, of two parts: the analog part and the
digital part. The former, is composed by
preamplifier and 1st order ∆ ∑ A/D converter
blocks, Band gap voltage reference, Low drop
voltage regulator, the latter, is composed by
There is also an OTP block, which is controlled
through the SPI by means of a dedicated
command set. The configured bits are used for
testing, configuration and calibration purpose.
From a pair of ∆ ∑ output signals coming from
analog section, a DSP unit computes the amount
of consummated active, reactive and apparent
energy, RMS and instantaneous values of voltage
and current. The results of computation are
available as pulse frequency and states on the
digital outputs of the device or as data bits in a
data stream, which can be read from the device
by means of SPI interface. This system bus
interface is used also during production testing of
the device and/or for temporary or permanent
programming of bits of internal OTP. In the
STPM01 an output signal with pulse frequency
proportional to energy is generated, this signal is
used in the calibration phase of the energy meter
application allowing a very easy approach. When
the device is fully configured and calibrated, a
dedicated bit of OTP block can be written
permanently in order to prevent accidental
entering into some test mode or changing any
configuration bit.
Order code
Part number
Temperature range
Package
Packaging
STPM01FTR
-40 to 85 °C
TSSOP20 (Tape & reel)
2500 parts per reel
February 2007
Rev. 4
1/56
www.st.com
56
STPM01
Contents
1
Schematic diagram
......................................... 4
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1
Measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2
ADC Offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.3
Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.4
Power supply DC and AC Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.5
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/56
8.1
General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.2
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.3
∆ ∑A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.4
Zero crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.5
Period and line voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.6
Single wire meter mode (only Rogowsky coil sensor) . . . . . . . . . . . . . . . 19
8.7
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.8
Load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.9
Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.10
Tamper detection module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.10.1
Detailed operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.10.2
Tamper state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.11
Phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.12
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STPM01
8.13
Resetting the STPM01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.14
Energy to frequency conversion (standalone) . . . . . . . . . . . . . . . . . . . . . 25
8.15
Driving a stepper motor (standalone) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.16
Using STPM01 in microcontroller based meter (peripheral) . . . . . . . . . . 27
8.17
Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.18
Programming the STPM01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.19
Configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.20
Mode signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.21
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.21.1
Remote Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.22
Reading data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.23
Writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.24
Energy calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.24.1
Active power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.24.2
Reactive power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.24.3
Apparent power and RMS values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9
STPM01 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3/56
Schematic diagram
1
Schematic diagram
Figure 1.
Block diagram
4/56
STPM01
STPM01
Pin configuration
2
Pin configuration
Figure 2.
Pin connections (top view)
Table 1.
Pin description
Pln N°
Symbol
Type (1)
1
MON
PO
Programmable output pin, see table 1
2
MOP
PO
Programmable output pin, see table 1
Digital input/output pin, see table 1
Name and function
3
SCS
D IN
4
VDDD
A OUT
5
VSS
GND
Ground
6
VCC
P IN
Supply voltage
Supply voltage for OTP cells
1.5V Output of internal low drop regulator which supplies the digital core
7
VOTP
P INr
8
VDDA
A OUT
9
IIP1
A IN
Positive input of primary current channel
10
IIN1
A IN
Negative input of primary current channel
11
IIP2
A IN
Positive input of secondary current channel
12
IIN2
A IN
Negative input of secondary current channel
13
VIP
A IN
Positive input of voltage channel
14
VIN
A IN
Negative input of voltage channel
15
SYN
D I/O
Programmable input/output pin, see table 1
16
CLKIN
A IN
Crystal oscillator input or resistor connection if RC oscillator is selected
17
CLKOUT
A OUT
18
SCL/NLC
D I/O
19
SDA/TD
D I/O
Programmable input/output pin, see table 1
20
LED
DO
Programmable output pin, see table 1
3V Output of internal low drop regulator which supplies the analog part
Oscillator Output (RC or crystal)
Programmable input/output pin, see table 1
1. A: Analog, D: Digital, P: Power
5/56
Maximum ratings
STPM01
3
Maximum ratings
Table 2.
Absolute maximum ratings (See note)
Symbol
Parameter
Value
Unit
-0.3 to 6
V
± 150
mA
-0.3 to VCC+0.3
V
VCC
DC Input voltage
IPIN
Current on any pin (sink/source)
VID
Input voltage at digital pins (SCS, MOP, MON, SYN, SDATD,
SCLNLC, LED)
VIA
Input voltage at analog pins (IIP1, IIN1, IIP2, IIN2, VIP, VIN)
-0.7 to 0.7
V
VOTP
Input voltage at OTP pin
-0.3 to 25
V
ESD
Human body model (all pins)
± 3.5
kV
TOP
Operating ambient temperature
-40 to 85
°C
Junction temperature
-40 to 150
°C
Storage temperature range
-55 to 150
°C
TJ
TSTG
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these condition is not implied
Table 3.
Thermal Data
Symbol
RthJA
Parameter
Thermal resistance junction-ambient
1. This value is referred to single-layer PCB, JEDEC standard test board.
6/56
Value
Unit
114.5 (1)
°C/W
STPM01
Functions
4
Functions
Table 4.
Programmable pin functions
Programmable
pin
Stand-alone mode
(APL register=2 or 3)
Peripheral mode
(APL register=0 or 1)
MON
Output for Stepper’s node (MB)
If APL=0 then Watchdog signal.
If APL=1 then ∆Σ signal of current channel
MOP
Output for Stepper’s node (MA)
If APL=0 then ZCR
If APL=1 then ∆Σ signal of voltage channel
LED
If APL=2 then LED provides high frequency
pulses proportional to Active Energy with 50%
duty cycle.
If APL=3 then LED provides pulses proportional
to Active Energy (internal signal AW). The
number of pulses per kWh can be selected
according to the value of KMOT configuration bit.
If APL=0 then LED can provide Active,
Reactive or Apparent Energy according to
value of KMOT configuration bit.
If APL=1 then LED is connected to the MUX
signal generated from the tamper detection
circuit.
When LED=low then the primary current
channel is selected, if LED=high the
secondary current channel is selected.
SCLNLC
SDATD
No-load indicator:
when low, a no-load condition is detected
Tamper indicator:
when low tamper condition is detected
SYN
Negative active power indicator:
when low a negative active power condition is
detected
SCS
Must be high to activate SCLNLC, SDATAD and
SYN indications
Used for SPI interface (see SPI interface
section for details)
7/56
Functions
Table 5.
Symbol
STPM01
Internal signal description
Name
Description
ZCR
Zero crossing signal
Provides positive pulse every time the line voltage crosses zero
AW
Active energy
Pulse frequency signal proportional to active energy
RW
Reactive energy
Pulse frequency signal proportional to reactive energy
SW
Apparent energy
Pulse frequency signal proportional to apparent energy
LIN
Line frequency signal
This signal is high when the voltage channel value is rising and it is low when
the voltage channel is falling. Basically this signal is the sign of dv/dt.
BFR
Base frequency range
This signal is high when the voltage line frequency is outside the nominal
band. It is low when the voltage line frequency is inside the nominal band.
Stepper motor signals
Signal available in MOP and MON to drive a stepper motor
BIT
Tamper flag
This signal provides the information on the tamper status. If low no tamper is
detected, when high a tamper condition has been detected. This signal is part
of the status register but is also available on the SDATD pin when in
standalone mode.
BIL
No load condition
Provides information on the load condition. This signal is part of the status
register but is also available on the SCLNLC pin when in standalone mode.
BIL=1 no load condition, BIL=0 normal operation.
MA
MB
8/56
STPM01
Electrical characteristics
5
Electrical characteristics
Table 6.
Electrical characteristics
(VCC =5V, TA= 25°C, 2.2µF between VDDA and VSS, 2.2µF between VDDD and VSS, 2.2µF
between VCC and VSS unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
400
Hz
Energy measurement accuracy
fBW
Effective bandwidth
Limited by digital filtering
5
Error
Measurement error
Over the dynamic range (5% to
1000% of the calibration power
value)
0.1
%
SNR
Signal to noise ratio
Over the entire bandwidth
52
db
PSRRDC Power supply DC rejection
Voltage signal: 200 mVrms/50Hz
Current signal: 10 mVrms/50Hz
fCLK= 4.194 MHz
VCC=3.3V±10%, 5V±10%
0.2
%
PSRRAC Power supply AC rejection
Voltage signal: 200 mVrms/50Hz
Current signal: 10 mVrms/50Hz
fCLK= 4.194 MHz
VCC=3.3V+0.2Vrms1@100Hz
VCC=5.0V+0.2Vrms1@100Hz
0.1
%
5.5
V
General section
VCC
Operating supply voltage
ICC
Supply current configuration
registers cleared or device
locked (TSTD=1)
∆ICC
Increase of supply current per
configuration bit, during
programming
3.0
4 MHz, VCC = 5V
3
4
8 MHz, VCC = 5V
5
6
4 MHz, VCC = 5V
120
mA
µA/bit
Increase of supply current per
configuration bit with device
locked
4 MHz, VCC = 5V
2
2.5
V
POR
Power on reset on VCC
VDDA
Analog supply voltage
2.85
3.0
3.15
V
VDDD
Digital supply voltage
1.425
1.50
1.575
V
fCLK
Oscillator clock frequency
fLINE
MDIV bit = 0
4.000
4.194
MHz
MDIV bit = 1
8.000
8.192
MHz
Nominal line frequency
45
65
Hz
VOTP
OTP programming voltage
14
20
V
IOTP
OTP programming current per
bit
tOTP
OTP programming time per bit
2.5
100
mA
300
µs
9/56
Electrical characteristics
Table 6.
Symbol
ILATCH
STPM01
Electrical characteristics
(VCC =5V, TA= 25°C, 2.2µF between VDDA and VSS, 2.2µF between VDDD and VSS, 2.2µF
between VCC and VSS unless otherwise specified)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
300
mA
-0.3
0.3
V
Gain 8X
-0.15
0.15
Gain 16X
-0.075
0.075
Gain 24X
-0.05
0.05
Gain 32X
-0.035
0.035
Current injection latch-up
immunity
Analog Inputs (IIP1, IIN1, IIP2, IIN2, VIP, VIN)
Voltage channel
VMAX
Maximum input signal levels
Current
channels
V
fADC
A/D Converter bandwidth
10
KHz
fSPL
A/D Sampling frequency
FCLK/4
Hz
VOFF
Amplifier offset
ZIP
VIP, VIN Impedance
Over the total operating voltage
range
ZIN
VIP1, VIN1, VIP2, VIN2
Impedance
Over the total operating voltage
range
GERR
IVL
ILEAK
100
Current channels gain error
±20
mV
400
KΩ
100
KΩ
±10
%
Voltage channel leakage current
-1
1
Channel disabled (PST=0 to 3;
CH2 disabled if CSEL=0; CH1
Current channel leakage current disabled if C
SEL=1) or device off
-1
1
Input enabled
µA
µA
-10
10
Digital I/O Characteristics (SDA, CLKIN, CLKOUT, SCS, SYN, LED)
SDA, SCS, SYN, LED
VIH
Input high voltage
VIL
Input low voltage
VOH
Output high voltage
IO = -2mA
VOL
Output low voltage
IO = +2mA
IUP
Pull up current
tTR
Transition time
CLKIN
0.75VCC
V
1.5
SDA, SCS, SYN, LED
0.25VCC
CLKIN
V
0.8
VCC-0.4
V
0.4
CLOAD = 50pF
V
15
µA
10
ns
Power I/O Characteristics (MOP, MON)
VOH
Output high voltage
IO = -14mA
VOL
Output low voltage
IO = +14mA
tTR
Transition time
CLOAD = 50pF
10/56
VCC-0.5
V
0.5
5
10
V
ns
STPM01
Electrical characteristics
Table 6.
Electrical characteristics
(VCC =5V, TA= 25°C, 2.2µF between VDDA and VSS, 2.2µF between VDDD and VSS, 2.2µF
between VCC and VSS unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
1
µA
4
MΩ
Crystal oscillator (see circuit figure 6)
II
Input current on CLKIN
RP
External resistor
CP
External capacitors
fCLK
Nominal output frequency
1
22
pF
4
4.194
8
8.192
MHz
RC Oscillator (see circuit figure 6)
ICLKIN
Settling current
RSET
Settling resistor
tJIT
Frequency jitter
40
fCLK= 4 MHz
60
µA
12
kΩ
1
ns
1.23
V
±1
%
On chip reference voltage
Reference voltage
VREF
TC
Reference accuracy
Temperature coefficient
After calibration
30
50
ppm/
°C
SPI interface timing
FSCLKr
Data read speed
32
MHz
FSCLKw
Data write speed
100
KHz
tDS
Data setup time
20
ns
tDH
Data hold time
0
ns
tON
Data driver on time
20
ns
tOFF
Data driver off time
20
ns
tSYN
SYN active width
Table 7.
Line current
interface
s
Typical external components
Function
Line voltage
interface
2/fCLK
Component
Parameter
Value
Tolerance
R to R ratio VRMS=230V
1650
±1%
R to R ratio VRMS=110V
830
±1%
Current shunt
0.2
±5%
Current transformer Current to voltage conversion ratio
30
±12%
Rogowsky coil
3
±12%
Resistor divider
Unit
V/V
mV/A
11/56
Terminology
6
Terminology
6.1
Measurement error
STPM01
The error associated with the energy measurement made by the STPM01 is defined as:
Percentage Error = [STPM01 (reading) - True Energy] / True Energy
6.2
ADC Offset error
This is the error due to the DC component associated with the analog inputs of the A/D
converters. Due to the internal automatic DC offset cancellation the STPM01 measurement
is not affected by DC components in voltage and current channel. The DC offset
cancellation is implemented in the DSP.
6.3
Gain error
The gain error is gain due to the signal channel gain amplifiers. This is the difference
between the measured ADC code and the ideal output code. The difference is expressed as
percentage of the ideal code.
6.4
Power supply DC and AC Rejection
This parameter quantifies the STPM01 measurement error as a percentage of reading when
the power supplies are varied. For the PSRRAC measurement, a reading at two nominal
supplies voltages (3.3 and 5 V) is taken. A second reading is obtained with the same input
signal levels when an ac (200 mVrms/100 Hz) signal is introduced onto the supplies. Any
error introduced by this ac signal is expressed as a percentage of reading.
For the PSRRDC measurement, a reading at two nominal supplies voltages (3.3 and 5V) is
taken. A second reading is obtained with the same input signal levels when the supplies are
varied ±10%. Any error introduced is again expressed as a percentage of the reading.
6.5
Conventions
The lowest analog and digital power supply voltage is named VSS which represent the
system Ground (GND). All voltage specifications for digital input/output pins are referred to
GND.
Positive currents flow into a pin. Sinking current means that the current is flowing into the pin
and then it is positive. Sourcing current means that the current is flowing out of the pin and
then it is negative.
Timing specifications of signal treated by a digital control part are relative to CLKOUT. This
signal is provided from the crystal oscillator of 4.194MHz nominal frequency or from the
internal RC oscillator, eventually an external source of 4.194MHz or 8.192MHz can be used.
Timing specifications of signals of the SPI interface are relative to the SCLNLC, there is no
direct relationship between the clock (SCLNLC) of the SPI interface and the clock of the
DSP block.
A positive logic convention is used in all equations.
12/56
STPM01
Typical performance characteristics
7
Typical performance characteristics
Figure 3.
Supply current vs supply voltage,
TA=25°C
Figure 4.
RC Oscillator frequency vs VCC,
R=12kΩ, TA=25°C
Figure 5.
RC Oscillator: Frequency jitter vs
temperature
Figure 6.
Analog voltage regulator: Line load regulation
Figure 7.
Digital voltage regulator: Line - load Figure 8.
regulation
Voltage channel linearity at
different VCC voltages
13/56
Typical performance characteristics
Figure 9.
Power supply AC rejection vs VCC
Figure 11. Error over dynamic range gain
dependence
Figure 13. Gain response of ∆Σ AD Converters
14/56
STPM01
Figure 10. Power supply DC rejection vs VCC
Figure 12. Primary current channel linearity at
different VCC
STPM01
Theory of operation
8
Theory of operation
8.1
General operation description
The STPM01 is able to perform active, reactive and apparent energy measurements, RMS
and instantaneous values for voltage and current, line frequency information.
Most of the functions are fully programmable using internal configuration bits accessible
through SPI interface. The most important configuration bits are the two Application bits
(APL - see table 1 for configuration register). Using these bits the STPM01 can be
programmed as peripheral (APL=0 or APL=1) in microcontroller based meter systems or as
standalone meter device (APL=2 or APL=3).
In standalone mode, the STPM01 is able to drive a stepper motor with the MOP and MON
pins, while some of the SPI pins (see table 1) are used to provide information on tamper, no
load and negative power.
In peripheral mode, due to the fact that the stepper motor is not used, the MOP and MON
pins are used to provide different information (see table 1), while the SPI pins are used to
communicate with the microcontroller.
The STPM01 includes internal registers that hold the useful information for the meter
system. Two kinds of active energy are available: the total active energy that includes all
harmonic content called type0 and the active energy limited to the 1st harmonic called
type1. This last energy value is obtained filtering the type0 active energy. The resolution of
both the two active energies is 20-bit. Reactive and Apparent energies are also available
with a 20-bit resolution.
STPM01 provides also the RMS values of voltage and current. Due to the modest dynamic
variation of the voltage, the RMS value is stored with a resolution of 11bit. While the RMS
current value has a resolution of 16bit. The momentary sampled value of voltage and
current are available also with a resolution of 11 and 16 bit respectively. The line frequency
value is stored with a resolution of 14 bits.
Due to the proprietary energy computation algorithm, STPM01 calibration is very easy and
fast allowing calibration in only one point over the whole current range. The calibration
parameters are stored permanently in the OTP (one time programmable) cells, preventing
calibration tampering.
8.2
Analog inputs
Input amplifiers
The STPM01 has one fully differential voltage input channel and two fully differential current
input channels.
The voltage channel consists of a differential amplifier with a gain of 4. The maximum
differential input voltage for the voltage channel is ±0.3V.
The two current channels are multiplexed (see tamper section for details) to provide a single
input to a preamplifier with a gain of 4. The output of this preamplifier is connected to the
input of a programmable gain amplifier (PGA) with possible gain selections of 2,4,6,8. The
total gain of the current channels will be then 8, 16, 24, 32. The gain selections are made by
writing to the gain register and it can be different for the two current channels. In case the
tamper function is not used, the secondary current can be disabled.
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Theory of operation
STPM01
The maximum differential input voltage is dependent on the selected gain according to the
following table.
Table 8.
Gain of voltage and current channels
Voltage channels
Gain
Current channels
Max Input voltage (V)
±0.30
4
Gain
Max input voltage (V)
8X
±0.15
16X
±0.075
24X
±0.05
32X
±0.035
The gain register is included in the Device Configuration Register with the address names
PST and ADDG. The table below shows the gain configuration according to the register
values:
Table 9.
Configuration of current sensors
Primary
Gain
Secondary
Sensor
Gain
Configuration Bits
Sensor
8
16
PST (3 bits)
ADDG (1 bit)
0
0
0
1
1
0
1
1
Rogowsky Coil
24
Disabled (No Tamper)
32
8
CT
2
X
32
Shunt
3
X
4
0
4
1
8
8
16
16
Rogowsky Coil
Rogowsky Coil
24
24
5
0
32
32
5
1
8
8
CT
6
X
32
Shunt
7
X
CT
8
Both the voltage and current channels implement an active offset correction architecture
which gives the benefit to avoid any offset compensation.
The analog voltage and current signals are processed by the ∑∆ Analog to digital converters
that feed the hardwired DSP. The DSP implements an automatic digital offset cancellation
that make possible avoiding any manual offset calibration on the analog inputs.
16/56
STPM01
8.3
Theory of operation
∑∆ A/D Converters
The analog to digital conversion in the STPM01 is carried out using two first order ∑∆
converters. The device performs A/D conversions of analog signals on two independent
channels in parallel. The current channel is multiplexed as primary or secondary current
channel in order to be able to perform a tamper function, if it is enabled. The converted ∑∆
signals are supplied to the internal hardwired DSP unit, which filters and integrates those
signals in order to boost the resolution and to yield all the necessary signals for
computations.
A ∑∆ modulator converts the input signal into a continuous serial stream of 1s and 0s at a
rate determined by the sampling clock. In the STPM01, the sampling clock is equal to fCLK/4.
The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is
subtracted from the input signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) can approach that of the input signal level. When
a large number of samples are averaged a very precise value of the analog signal is
obtained. This averaging is carried out in the DSP section which implements decimation,
integration and DC offset cancellation of the supplied ∑∆ signals. The gain of the decimation
filters is 1.004 for the voltage channel and 0.502 for the current channel. The resulting signal
has a resolution of 11bits for voltage channel and 16 bits for current channel.
Figure 14. First order ∑∆ A/D Converter
f CLK/4
Integrator
+
Input analog signal
Output digital signal
Σ
∫
-
DAC
8.4
Zero crossing detection
The STPM01 has a zero crossing detector circuit on the voltage channel which can be used
by application for synchronization of some utility equipment to event of zero crossing of line
voltage. This circuit produces the internal signal ZCR which has a rising edge every time the
line voltage crosses zero and a negative edge every time the voltage reaches its positive or
negative peak. The ZCR signal is then at twice the line voltage frequency. The ZCR signal is
available on the MOP pin only when STPM01 works as peripheral with the configuration bit
APL=0.
17/56
Theory of operation
STPM01
Figure 15. ZCR Signal
8.5
Period and line voltage measurement
The period module measures the period of base frequency of voltage channel and checks if
the voltage signal frequency is in the band from fCLK/217 to fCLK/215. In order to do this, the
signal LIN is produced which is low when the line voltage is rising and it is high when the line
voltage is falling. This means that the LIN signal is the sign of dv/dt. With further elaboration,
the ZCR signal is also produced. On the trailing edge of LIN (Line Frequency) the period
counter starts counting up pulses of fCLK/4 reference signal. The LIN signal is available on
the status bit register (see table 12).
If the counted number of pulses between two trailing edges of LIN is higher than the fCLK/217
Hz equivalent pulses or if the counting is never stopped (no more LIN trailing edge) it means
that the base frequency is lower than fCLK/217 Hz and an error flag BFR (Base Frequency
Range) is set.
If the counted number of pulses between two trailing edges of LIN is higher than the fCLK/215
equivalent pulses, the base frequency exceeds the limit. In this case, such error must be
repeated three times in a row, in order to set the error flag BFR.
The BFR flag is also set if the register value of the RMS voltage drops below 64. BFR is
cleared when the register value goes above 128. The BFR, then, gives also information
about the presence of the line voltage inside the meter.
18/56
STPM01
Theory of operation
Figure 16. LIN and BFR signal
When the BFR error is set, the computation of power is zero unless the FRS bit is set or the
Single Wire Mode operation is selected (see paragraph 5). In fact, the effect of the BFR bit
can be overridden by setting FRS configuration bit. It means that if FRS is set and BFR is
also set, all the energy computation is carried on as BFR was cleared.
In standalone mode, the MOP, MON and LED provide the energy information, their
operation is not affected by FRS bit, it means that when BFR is set they will be held low
regardless the FRS value.
When the line frequency re-enter the nominal band the BFR flag is automatically reset. This
BFR error flag is also assembled as part of 8-bit status register.
8.6
Single wire meter mode (only Rogowsky coil sensor)
STPM01 support Single Wire Meter (SWM) operation when working with Rogowsky Coil
current sensors. In SWM mode there is no available voltage information in the voltage
channel. It is possible that someone has disconnected one wire (live or neutral) of the meter
for tampering purposes or in case the line voltage is very stable, it is possible to use a
predefined value for computing the energy without sensing it.
In order to enable the SWM mode, the STPM01 must be configured with PST values of 4 or
5, (Tamper enabled-Rogowsky Coils). In this way, if the BFR error is detected, STPM01
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Theory of operation
STPM01
enters in SWM. If BFR is cleared the energy calculation is performed normally, when BFR is
set (no voltage information is available) the energy computation is carried out using a
nominal voltage value according to the NOM configuration bits.
Since there is no more information on the phase shift between voltage and current, the
apparent rather than active power is used for tamper and energy computation. The
calculated apparent energy will be the product between IRMS (effectively measured) and an
equivalent VRMS that can be calculated as follows:
VRMS=VPK*KNOM, where VPK represents the maximum line voltage reading of the
STPM01 and KNOM is a coefficient that changes according to the following table:
Table 10.
Nominal voltage values
NOM
KNOM
0
0.3594
1
0.3906
2
0.4219
3
0.4531
For example, if a R1 = 783kΩ and R2 = 475Ω are used as resistor divider when the line
voltage is present, the positive voltage present at the input of the voltage channel of
STPM01 will be:
VI =
R2
⋅V
2
R1 + R2 RMS
since the maximum voltage value applicable to the voltage channel input of STPM01 is
+0.3V, the equivalent maximum line voltage applicable will be:
VPK = R1+R2/R2 • 0.3 = 494.82
considering the case of NOM=2, the correspondent RMS values used for energy
computation will be:
VRMS = VPK • 0.4219 = 208.76 [V]
Usually the supply voltage for the electronic meter is taken from the line voltage, in SWM,
since the line voltage is not present any more, some other power source must be used in
order to provide the necessary supply to STPM01 and the other electronic components of
the meter.
8.7
Power supply
The main STPM01 supply pin is the VCC pin. From the VCC pin two linear regulators provide
the necessary voltage for the analog part VDDA (3V) and for the digital part VDDD (1.5V). The
VSS pin represents the reference point for all the internal signals. 100nF low ESR capacitor
should be connected between VCC and VSS, VDDA and VSS, VDDD and VSS. All these
capacitors must be located very close to the device.
The STPM01 contains a Power On Reset (POR) detection circuit. If the VCC supply is less
than 2.5V then the STPM01 goes into an inactive state, all the functions are blocked
asserting a reset condition. This is useful to ensure correct device operation at power-up
and during power-down. The power supply monitor has built-in hysteresis and filtering,
which give a high degree of immunity to false triggering due to noisy supplies.
20/56
STPM01
Theory of operation
A BandGap voltage reference (VBG) of 1.23V ±1% is used as reference voltage level source
for the two linear regulators and for the A/D converters. Also, this module produces several
bias currents and voltages for all other analog modules and for the OTP module. The
bandgap voltage can be compensated regardless to the temperature variations with the
BGTC bits..
Figure 17. Bandgap temperature variation
8.8
Load monitoring
The STPM01 includes a no load condition detection circuit with adjustable threshold. This
circuit monitors the voltage and the current channels and, when the measured voltage is
below the set threshold, the internal signal BIL becomes high. The information about this
signal is also available in the status bit BIL.
The no load condition occurs when the product between VRMS and IRMS register values is
below a given value. This value can be set with the LTCH configuration bits.
Four different no-load threshold values can be chosen according to the two configuration
bits LTCH (see table 11).
Table 11.
No load detection thresholds
LTCH
KLTCH
0
800
1
1600
2
3200
3
6400
When a no load condition occurs (BIL=1) the integration of power is suspended and the
tamper module is disabled.
In standalone mode, if a no load condition is detected, the BIL signal blocks generation of
pulses for stepper and forces SCLNLC pin to be low. If APL=2 (see 8.14) the LED pin
continues providing the high frequency pulses, while if APL=3, the pulses are stopped as
happens for MOP and MON.
In peripheral mode, the BIL signal can be accessed only through the SPI interface.
21/56
Theory of operation
8.9
STPM01
Error detection
In addition to the no load condition and the line frequency band, the integration of power can
be suspended also due to detected error on the source signals.
There are two kinds of error detection circuits involved. The first checks all the ∑∆ signals
from the analog part if any is stacked at 1 or 0 within the 1/128 of fCLK period of observation.
In case of detected error the corresponding ∑∆ signal is replaced with an idle ∑∆ signal,
which represents a constant value 0. All error and other resolved flags are treated as bits of
a device status and can be read out by means of SPI interface.
Another error condition occurs if the MOP, MON and LED pin outputs signals are different
from the internal signals that drive them. This can occur if some of this pin is forced to GND
or to some other imposed voltage value. In this case the internal status bit PIN is activated
providing the information that some hardware problem has been detected, for example the
stepper motor has been mechanically blocked.
8.10
Tamper detection module
The STPM01 is able to measure the current in both live and neutral wire. This mechanism is
adopted to implement anti-tamper function. If this function is selected (see Table 10), the
live and neutral wire currents are monitored; when a difference between the two
measurements is detected, the STPM01 enters the Tamper State, while when there is a
very small difference between the two channels the STPM01 is in Normal state.
In particular, both channels are not observed all the time, rather a time multiplex mechanism
is used. During the observation time of the selected channel, its active energy is calculated.
The detection of a tamper condition occurs when the absolute value of the difference
between the two active energy values is greater than a certain percentage of the averaged
energy during the activated tamper module. This percentage value can be selected between
two different values (12.5% and 6.25%) according to the value of the configuration bit CRIT.
The tamper condition will be detected when the following formula will be satisfied:
EnergyCH1 - EnergyCH2 > KCRIT (EnergyCH1 + EnergyCH2)/2; where KCRIT can be 12.5%
or 6.25%.
The detection threshold is much higher than the accuracy difference of the current
channels, which should be less than 0.2%, but, some headroom should be left for possible
transition effect, due to accidental synchronism of actual load current change with the
rhythm of taking the energy samples.
The tamper circuit works if the energies associated with the two current channels will be
both positive or negative, if the two energies will have different sign, the tamper will be on all
the time however, the channel with the associated higher power will be selected for the final
computation of energy.
In single wire mode, the Apparent energy rather then the active is used for Tamper
detection.
8.10.1
Detailed operational description
Normal state
The meter is initially set to normal state, i.e. tamper not detected. In such state, we expect
that the values of both load currents should not differ more than the accuracy difference of
the channels does. For this reason, we can use an average value of currents of both
22/56
STPM01
Theory of operation
channels for active energy calculation. The average is implemented with the multiplex ratio
of 32:32 periods of line per channel. This means that for 32 periods of line voltage, i.e.
640ms at 50Hz, the current of primary channel is used for the calculation followed by
another 32 periods of line voltage when the current of secondary channel is used instead.
Four periods before the primary to secondary switching point a tamper detection module is
activated and it is deactivated after eight periods of line are elapsed. This means that
energy of four periods of primary channel immediately followed by energy of four periods of
secondary channel is sampled within the tamper module. We shall call those samples A and
B respectively. From these two samples the criteria of tamper detected is calculated. If four
consecutive new results of criteria happen, i.e. after elapsed 5.12s at 50Hz, the meter will
enter into Tamper State
8.10.2
Tamper state
Within this state the multiplex ratio will change either to 60:4, when primary current is higher
than secondary, or to 4:60 otherwise. Thus, the channel with the higher current will
participate in the energy calculation. Even more, the energy is not averaged by the
mentioned ratio, rather the last measured higher current is used also during 4 line period
gap. The gap is still needed in order to monitor the samples of the non-selected channel,
which should check when the tamper detected state is changed to either normal or another
tamper detected state.
Several cases of transition of the state are shown on the Figure below.
Figure 18. Tamper conditions
23/56
Theory of operation
STPM01
The detected tamper condition is stored in the BIT status bit. If BIT=0 tamper is not
detected, if BIT=1 a tamper condition has been detected. In standalone mode the BIT flag is
also available in the SDATD pin.
When internal signals are not good enough to perform the computation, i.e. line period is out
or range or ∑∆ signals from analog part are stacked at high or low logic level, or no load
condition is activated, the tamper module is disabled and its state is preset to normal.
8.11
Phase compensation
The STPM01 is does not introduce any phase shift between voltage and current channel.
However, the voltage and current signals come from transducers, which could have inherent
phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current
transformer (CT). These phase errors can vary from part to part, and they must be corrected
in order to perform accurate power calculations. The errors associated with phase mismatch
are particularly noticeable at low power factors. The STPM01 provides a means of digitally
calibrating these small phase errors through a introducing delays on the voltage or current
signal. The amount of phase compensation can be set using the 4 bits of the phase
calibration register (CPH).
The default value of this register is at value of 0 which gives 0° phase compensation. When
the 4 bits give a CPH of 15 (1111) the introduced compensation is +0.576°. This
compensates the phase shift usually introduced by the current sensor, while the voltage
sensor, normally a resistor divider, does not introduce any delay. The resolution step of the
phase compensation is 0.038°.
8.12
Clock generator
All the internal timing of the STPM01 is based on the CLKOUT signal. This signal can be
generated in three different ways:
1. RC: this oscillator mode can be selected using the RC configuration bit. If RC=1 the
STPM01 will run using the RC oscillator. A resistor connected between CLKIN and
Ground will set the RC current. For 4Mhz operation the suggested settling resistor is
12kΩ; The oscillator frequency can be compensated using the CRC configuration bit
(see table 13)
2. Quartz: If RC=0 the oscillator will work with an external crystal. The suggested circuit
is depicted in fig. 18;
3. External Clock: keeping RC=0, it is also possible to feed the CLKOUT pin with an
external oscillator signal
The clock generator is powered from analog supply and is responsible for two tasks. The
first one is to retard the turn on of some function blocks after POR in order to help smooth
start of external power supply circuitry by keeping off all major loads.
The second task of the clock generator is to provide all necessary clocks for analog and
digital parts. Within this task, the MDIV configuration bit is used to inform the device about
the nominal frequency value of CLKOUT. Two nominal frequency ranges are expected, from
4.000MHz to 4.194MHz (MDIV=0) or from 8.000MHz to 8.192MHz (MDIV=1).
24/56
STPM01
Theory of operation
Figure 19. Different oscillator circuits (a): STPM12/14 with quartz; (b) STPM11/13; (c) STPM12/14
with external source
8.13
Resetting the STPM01
The STPM01 has no reset pin. The device is automatically reset by the POR circuit when
the VCC crosses the 2.5V value but it can be reset also through the SPI interface giving a
dedicated command (see SPI section for remote reset command details).
In case of reset caused by POR circuit all clocks and both DC buffers in the analog part are
kept off for about 30ms and all blocks of digital part, except for SPI interface, which is hold in
a reset state for about 125ms after a reset condition.
When the reset is performed through SPI no delayed turn on is generated.
Resetting the STPM01 causes all the functional modules of STPM01 to be cleared including
the OTP shadow latches (see paragraph 16 for OTP shadow latches description)
The reset through SPI (Remote reset request) will normally take place during production
testing or in an application of meter with some on-board microprocessor when some
malfunction of metering device will be detected.
8.14
Energy to frequency conversion (standalone)
When used in standalone mode the STPM01 provides energy to frequency conversion both
for calibration and energy readout purposes. In fact one convenient way to verify the meter
calibration is to provide a pulse train signal with 50% duty cycle whose frequency signal is
proportional to the active energy under steady load conditions. In this case the user will
choose a certain number of pulses on the LED pin that will corresponds to 1kWh. We will
name this value as P.
The Active Energy frequency-based signal is available in the LED pin when APL=2 or
APL=3.
If APL=2 the LED is driven from internal signal AW (Active Energy) whose frequency is
proportional to the active energy. The signal AW is taken from the 11th bit of the active
energy register, consequently a relationship between the LSB value of the Active energy
register and the number of pulses provided per each kWh (P) can be defined as.
25/56
Theory of operation
STPM01
kAW = 1000/(211•P) [Wh] Eq. 1
If APL=3 the LED pin provides Active Energy frequency-based signal dependent on the
value of the KMOT configuration bit according to the following table. In this case the pulses
will have a fixed width of 31.25 ms.
Table 12.
Different settings for led signal
APL=2
APL=3
Pulses
Pulses
KMOT (2 Bits)
0
P/64
1
P/128
P
2
P/32
3
P/256
Due to the innovative and proprietary power calculation algorithm the frequency signal is not
affected by any ripple at twice the line frequency, this feature strongly reduces the
calibration time of the meter.
In a practical example where APL=2, and the desired P is 64000 pulses/KWh (=17.7
Hz*kW), we have:
KAW = 7.63*10-6 Wh
This means that the reading of 0x00001 in the active energy register represents 7.63 µWh,
while 0xFFFFF represents 8Wh.
8.15
Driving a stepper motor (standalone)
When used in standalone mode (APL=2 or APL=3), the STPM01 is able to directly drive a
stepper motor. From signal AW, a stepper driving signals MA and MB are generated by
means of internal divider, mono-flop and decoder. The MA and MB signals are brought to
the MOP and MON pins that are able to drive the stepper motor. Several kinds of selections
are possible for the driving signals according to the configuration bits LVS and KMOT.
The numbers of pulses per kWh (PM) in the MOP and MON outputs are linked with the
number of pulses of the LED P (see previous paragraph) pin with the following relationship:.
Table 13.
26/56
Configuration of Mop and Mon Pins
LVS (1 Bit)
KMOT (2 Bits)
Pulses length
PM
0
0
31.25 ms
P/64
0
1
31.25 ms
P/128
0
2
31.25 ms
P/32
0
3
31.25 ms
P/256
1
0
156.25 ms
P/640
1
1
156.25 ms
P/1280
1
2
156.25 ms
P/320
1
3
156.25 ms
P/2560
STPM01
Theory of operation
The mono-flop limits the length of the pulses according to the LVS bit value.
The decoder distributes the pulses to MA and MB alternatively, which means that each of
them has only a half of selected frequency.
In case of detected negative power the behavior of MOP and MON depend on the ABS
configuration bit status. If this bit is set, the negative power is computed as it was positive
(absolute value regardless of the sign), and the MOP and MON signals maintain the pulse
sequence in order to keep the forward rotation direction of the motor. If ABS is zero negative
power is computed with its own sign, and the MOP and MON signals invert their logic state
in order to make the backward rotation direction of the motor. See the diagram below..
Figure 20. Positive energy or absolute computation energy (ABS=1) stepper driving signals
Hi
MON
Lo
Hi
MOP
Lo
Figure 21. Negative energy stepper driving signals
Hi
MON
Lo
Hi
MOP
Lo
When a no-load condition is detected MOP and MON are held low.
8.16
Using STPM01 in microcontroller based meter (peripheral)
The higher flexibility of STPM01 allows its use in very high end microcontroller based energy
meters. In this case the STPM01 must be programmed to work in peripheral mode, all the
SPI pins (SCS, SCLNCL, SDATD, SYN) are used only for communication purposes allowing
the microcontroller to write and read the internal STPM01 registers. The peripheral mode
has two further different configuration modes according to the status of the APL
27/56
Theory of operation
STPM01
configuration bit. The APL bit status changes the function of MOP, MON and LED pins
according to the description below.
APL=0:
In the MOP pin, the ZCR signal is available (see paragraph 3 for details about ZCR signal);
The pin MON provides the DOG signal. The DOG signal generates a 16ms long positive
pulse every 1.6 seconds. Generation of these pulses can be suspended if data are read in
intervals shorter than 1.6s. The DOG signal is actually a watchdog reset signal which can be
used to control an operation of an on-board microcontroller. It is set to high whenever the
VDDA voltage is below 2.5 V, but after VDDA goes above 2.5V this signal starts to run.
It is expected that an application microcontroller should access the data in the metering
device on regular basis at least 1/s (recommended is 32/s). Every latching of results in the
metering device requested from the microcontroller also resets the watchdog. If latching
requests does not follow each other within 1.6 second, an active high pulse on MON is
produced, because device assumes that microcontroller does not operate properly. An
application can use this signal either to control the RESET pin of its microcontroller or it can
be tied to some interrupt pin. The last possibility is recommended for a battery backup
application which can enter some sleep mode due to power down condition and should not
be reset by metering device because it would exit from the sleep mode.
The LED pin can be driven from AW wide Band (Active Energy as in standalone mode), AW
limited at fundamental, RW (Reactive Energy) or SW (Apparent Energy) according to the
value of KMOT bit.
Table 14.
Led pin configuration in peripheral mode
KMOT (2 Bits)
Signal available in LED pin
# of Pulses
0
AW Type 0
(1)
P [kWh]
1
AW Type 1 (1)
P [kWh]
2
RW
P [kVARh]
3
SW
P [kVAh]
1. * Type0 is the Wide band Active Energy and Type1 is the fundamental Active Energy if FUND=0, if FUND=1 they are
swapped.
In this case, since the LED pin is driven by signals different from AW, some other
relationship between the LSB of the register and must be defined:
KAWFund = 4*KAW [Wh]
KRW = 2*KAW [VARh]
KSW = KAW [VAh]
APL=1:
MOP provides the ∑∆ signal generated from the analog voltage input;
MON provides the ∑∆ signal generated from the analog current input, according to the
selection of the tamper module
LED provides the information about the selection of the current channel made by the tamper
module. If LED is low it means the primary channel is selected, if LED is high the secondary
channel is actually selected.
28/56
STPM01
8.17
Theory of operation
Status bits
The STPM01 includes 8 status bits that provide several information on the current meter
status. The status bits are the following:
Table 15.
Status bit description
Bit #
Name
0
BIL
Description
Condition
BIL=0: No load condition not detected
No load condition
BIL=1: No load detected
1
BCF
∑∆ signals status
2
BFR
Line frequency range
BCF=0: ∑∆ signals alive
BCF=1: one or both ∑∆ signals are stacked
BFR=0: Line frequency inside the 45Hz-65Hz range
BFR=1: Line frequency out of range
BIT=0: Tamper not detected;
3
BIT
Tamper condition
BIT=1: Tamper detected;
MUX=0: Primary current channels selected by the tamper module;
4
MUX
Current channel selection MUX=1: Secondary current channels selected by the tamper
module;
LIN=0: line voltage is going from the minimum to the maximum value.
(∆v/∆t >0);
5
LIN
Trend of the line voltage
LIN=1: line voltage is going from the maximum to the minimum value.
(∆v/∆t < 0);
PIN=0: the output pins are consistent with the data
6
PIN
Output pins check
PIN=1: the output pins are different with the data, this means some
output pin is forced to 1 or 0.
HLT=0: the data records reading are valid.
7
HLT
Data Validity
HLT=1: the data records are not valid. A reset occurred and a restart
is in progress.
When STPM01 is used in peripheral mode all these signal can be read through the SPI
interface. See paragraph 16 for details on the Status bit location in the STPM01 data
records.
In standalone mode the BIL signal is available in SCLNLC pin and the BIT signal in the
SDATD pin. All the other signals can be read only through SPI interface.
8.18
Programming the STPM01
Data records
The STPM01 has 8 internal data records registers. Every data record consists of 4-bit parity
code and 28-bit data value where the parity code is computed from the data value, which
makes total of 32 bits or 4 bytes.
The figure below shows the data records structure with the name of the contained
information.
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Theory of operation
STPM01
Each bit of parity nibble is defined as odd parity of all seven corresponding bits of data
nibbles.
The first 6 registers are read-only except for the 8 bit mode signals in the DFP register (the
mode signals will be described later in this paragraph). The last two registers CFL and CFH
can be also written because they contain the configuration bits. Among these last 64bits (32
of CFL and 32 of CFH), 8 bits are used for parity nibbles, then only 56 bits are used for
configuring and programming the STPM01.
Figure 22. STPM01 Data records map
20 bit
4 bit
8 bit
1bit 1bit
1bit
6 bit
DAP
parity
type0 active energy
DRP
parity
reactive energy
DSP
parity
apparent energy
lower f(u)
DFP
parity
type 1 energy
mode signals
DEV
parity
p
uRMS
iRMS
DMV
parity
p
uMOM
iMOM
CFL
parity
lower part of configurators
CFH
parity
upper part of configurators
Status
0 1
msb
lsb
11 bit
8.19
upper f(u)
16 bit
Configuration bits
All the configuration bits that control the operation of the device (CFL and CFH data records)
can be written in a temporary or permanent way. In case of temporary writing the
configuration bits value are written in the so-called Shadow Registers which are simple
latches that hold the configuration data. In case of permanent writing the configuration bits
are stored in the OTP (one time programmable) cells that keep the information for an
undefined period of time even if the STPM01 is without supply, but, once written, they
cannot be changed anymore.
The shadow registers are cleared whenever a reset condition occurs (both POR and remote
reset).
As indicated in the data records table, the configuration bits are 56. Each of them consists of
paired elements, one is latch, the OTP shadow, and another is the OTP antifuse element.
When the STPM01 is released in the market, all antifuses represents logic low state but they
can be written by the user in order to configure the STPM01.This means that STPM01 can
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STPM01
Theory of operation
retain 56 bits of information even if it has been unsupplied for an undefined time. That’s why
the CFG signals are used to keep certain configuration and calibration values of device.
The very first CFG bit, called TSTD, is used to disable any change of system signals after it
was permanently set. During the configuration phase, each bit set to logic level 1 will
increase the supply current of STPM01 of about 120 µA, until the TSTD bit is set to 1. The
residual increase of supply current is 2µA per each bit set to 1. It is then recommended to
set the TSTD bit to 1 after the configuration procedure in order to keep the supply current as
low as possible.
The STPM01 can work either using the data stored in the OTP cells either the data available
in the shadow latches. This can be chosen according to the value RD Mode signal (see
Mode Signal paragraph for description). If the RD is set, the CFG bits originates from
corresponding OTP shadow latches otherwise, if the RD is cleared, the CFG bits originates
from corresponding OTP antifuses. This way one can temporary sets up certain
configuration or calibration of device then verify it and then change it, if it is necessary. For
example, this is extensively exercised during production tests.
Each configuration bit can be written sending a byte command to STPM01 through its SPI
interface. The procedure to write the configuration bits is described in the SPI section.
After the TSTD bit has been set, the only write commands accepted will be the Precharge
and the Remote Reset, this implies that the shadow latches cannot be used as source of
configuration data anymore.
Table 16.
Configuration bits map
Address
Name
N. of
bits
0
TSTD
1
Test mode and OTP write disable:
- TSTD=0: testing and continuous pre-charge of OTP when in read mode,
- TSTD=1:normal operation and no more writes to OTP
000001
1
MDIV
1
Measurement frequency range selection:
- MDIV=0: 4.000MHz to 4.194MHz,
- MDIV=1: 8.000MHz to 8.192MHz
000010
2
RC
1
Type of internal oscillator selection:
- RC=0:crystal oscillator,
- RC=1:RC oscillator
000011
3
4 (1)
2
000100
Peripheral or Standalone mode:
- APL=0: peripheral, MON=WatchDOG; MOP=ZCR, LED=pulses,
- APL=1: peripheral, MOP=∆Σ Voltage; MON=∆Σ current; LED=Mux (current) APL=2: standalone, MOP,MON=stepper, LED=pulses, SCLNLC=no load
condition, SDATD=tamper detected, SYN=negative active power direction
- APL=3: standalone, MOP:MON=stepper, LED=pulses according to KMOT,
SCLNLC=no load condition, SDATD=tamper detected, SYN=negative active
power direction
6-BIT
Binary
DEC
000000
APL
Description (1)
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Theory of operation
Table 16.
STPM01
Configuration bits map
Address
Name
6-BIT
Binary
DEC
000101
5
000110
6
000111
(1)
PST
7
N. of
bits
Description (1)
3
Current channel sensor type, gain and tamper selection:
- PST=0: primary is coil x8 (x16 if ADDG=1), secondary is not used, no tamper
- PST=1: primary is coil x24 (x32 if ADDG=1), secondary is not used, no tamper
- PST=2: primary is CT x8, secondary is not used, no tamper
- PST=3: primary is shunt x32, secondary is not used, no tamper
- PST=4: primary is coil x8 (x16 if ADDG=1), secondary is coil x8 (x16 if
ADDG=1), tamper
- PST=5: primary is coil x24 (x32 if ADDG=1), secondary is coil x24 (x32 if
ADDG=1), tamper
- PST=6: primary is CT x8, secondary is CT x8, tamper
- PST=7: primary is CT x8, secondary is shunt x32, tamper
001000
8
FRS
1
In case the voltage channel frequency is out of the useful band (BFR signal),
this bit set the way to compute the power.
- FRS=0: power is set to zero;
- FRS=1: the nominal voltage is used to compute the power;
001001
9
MSBF
1
Bit sequence output during record data reading selection:
- MSBF=0: msb first
- MSBF=1: lsb first
001010
10
FUND
1
This bit swap the information stored in the type0 (first 20 bits of DAP register)
and type1 (first 20 bits of DFP register) active energy.
- FUND = 0: type 0 contains wide band active energy, type1 contains
fundamental active energy
- FUND = 1: type 0 contains fundamental active energy, type1 contains wide
band active energy
001011
11
ABS
1
Power accumulation type selection on Active, Reactive and Apparent energies:
- ABS=0: signed accumulation,
- ABS=1: absolute accumulation
001100
12
2
No load condition threshold as product between VRMS and IRMS:
LTCH=0
800
LTCH=1
1600
LTCH=2
3200
LTCH=3
6400
001101 13 (1)
001110
LTCH
Constant of stepper pulses/kWh (see par. 16) selection when APL=2 or 3:
If LVS=0,
KMOT=0
P/64
KMOT=1
P/128
KMOT=2
P/32
KMOT=3
P/256
14
If LVS=1,
KMOT
001111 15 (1)
32/56
2
KMOT=0
KMOT=1
KMOT=2
KMOT=3
P/640
P/1280
P/320
P/2560
Selection of pulses for LED when APL=0:
KMOT=0
Type0 Active Energy
KMOT=1
Type1 Active Energy
KMOT=2
Reactive Energy
KMOT=3
Apparent Energy
STPM01
Theory of operation
Table 16.
Configuration bits map
Address
Name
6-BIT
Binary
DEC
010000
16
RESERVED
BGTC
2
Bandgap Temperature compensation bits. See figure 4 for details.
CPH
4
4-bit unsigned data for compensation of phase error, 0°+0.576°.
16 values are possible with a compensation step of 0.0384°. When CPH=0 the
compensation is 0°, when CPH=15 the compensation is 0.576°.
8
8-bit unsigned data for voltage channel calibration.
256 values are possible. When CHV is 0 the calibrator is at -12.5% of the
nominal value. When CHV is 255 the calibrator is at +12.5%. The calibration
step is then 0.098%.
8
8-bit unsigned data for primary current channel calibration.
256 values are possible. When CHP is 0 the calibrator is at -12.5% of the
nominal value. When CHP is 255 the calibrator is at +12.5%. The calibration
step is then 0.098%.
8
8-bit unsigned data for secondary current channel calibration.
256 values are possible. When CHS is 0 the calibrator is at -12.5% of the
nominal value. When CHS is 255 the calibrator is at +12.5%. The calibration
step is then 0.098%.
18
010011 19 (1)
010100
20
010101
21
010110
Description (1)
2
010001 17 (1)
010010
N. of
bits
22
010111 23 (1)
011000
24
011001
25
011010
26
011011
27
011100
28
011101
29
011110
30
CHV
011111 31 (1)
100000
32
100001
33
100010
34
100011
35
100100
36
100101
37
100110
38
CHP
100111 39 (1)
101000
40
101001
41
101010
42
101011
43
101100
44
101101
45
101110
46
CHS
101111 47 (1)
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Theory of operation
Table 16.
STPM01
Configuration bits map
Address
Name
6-BIT
Binary
DEC
110000
48
110001 49 (1)
110010
N. of
bits
CRC
2
2-bit unsigned data for calibration of RC oscillator. (see Typical Characteristics
in page 8)
CRC=0, or CRC=3 cal=0%
CRC=1, cal=+10%;
CRC=2, cal=-10%.
NOM
2
2-bit modifier of nominal voltage for Single Wire Meter.
NOM=0: KNOM=0.3594 / NOM=1: KNOM=0.3906 / NOM=2: KNOM=0.4219 /
NOM=3: KNOM=0.4531;
50
110011 51 (1)
Description (1)
110100
52
ADDG
1
Selection of additional gain on current channels:
ADDG=0: Gain+=0 / ADDG=1: Gain+=8
110101
53
CRIT
1
Selection of tamper threshold:
CRIT =0: 12,5% / CRIT =1: 6,25%
110110
54
LVS
1
Type of stepper selection:
LVS=0: pulse width 31.25 ms, 5V, / LVS=1: pulse width, 156.25 ms, 3V
110111
55
1
Reserved
1. IMPORTANT: This Bit represents the MSB of the decimal value indicated in the description column.
As it is indicated above, the STPM01 includes 56 CFG bits. Normally, some of these bits
should be permanently set during production of application of STPM01 in order to protect
the application from power fails. Of course, if an application would include an on-board
microcontroller, it could reload the configuration and calibration values after power on restart
and so, the permanent set of STPM01 would not be necessary. But this is not very safe way
to do it, because due to some EMI even imposed to tamper the meter, the microcontroller
may become lost and during such state, it can change some system signals in the STPM01
or somebody can change the calibration and configuration by changing the software of onboard microcontroller.
8.20
Mode signals
The STPM01 includes 8 Mode signals located in the DFP data record, 3 of these are used
only for internal testing purposes while 5 are useful to change some of the operation of the
STPM01. The mode signals are not retained when the STPM01 supply is not available and
then they are cleared when a POR occurs but they are not cleared when a remote reset
command (RRR) is sent through SPI.
The mode signals bit can be written using the normal writing procedure of the SPI interface
(see SPI section).
Of course, we can clear the RD by clearing all system signals. The first way is to generate
POR signal but this way we clear and reset the whole device. An alternative way is to set the
TSTD bit in the shadow latches. This setting becomes effective after SCS goes to idle state
when the TSTD clears all system signals including itself but, it does not reset the whole
device.
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STPM01
Theory of operation
Table 17.
Mode signals description
Bit #
Signal
Name
0
Reserved
1
Reserved
3
Reserved
4
CSEL
6
7
Status
Binary
Command
Hex
Command
0
MOP and MON operates normally
0111001x
72 or 73
1
MOP and MON provides the driving signals to implement a
charge-pump DC-DC converter
1111001x
F2 or F3
0
Current Channel 1 selected when tamper is disabled.
0111100x
78 or 79
1
Channel 2 selected when tamper is disabled.
1111100x
F8 or F9
0
The 56 Configuration bits originated by OTP antifuses
0111101x
7A or 7B
1
The 56 Configuration bits originated by shadow latches.
1111101x
FA or FB
0
Any writing in the configuration bits is recorded in the
shadow latches.
0111110x
7C or 7D
1
Any writing in the configuration bits is recorded both in the
shadow latches and in the OTP antifuse elements.
1111110x
FC or FD
1
Swap the 32 bits data records reading. From
1,2,3,4,5,6,7,8, to 5,6,7,8,1,2,3,4 and viceversa.
1111111x
FF
PUMP
2
5
Bit
Value
RD
WE
Precharge
– RD mode signal has been already described in the SPI section but there is another
implied function of the signal RD. When it is set, each sense amplifier is disconnected
from corresponding antifuse element and this way, its 3V NMOS gate is protected
from the high voltage of VOTP during permanent write operation. This means that as
long as the VOTP voltage reads more than 3V, the signal RD should be set.
– PUMP: when set, the PUMP mode signal transform the MOP and MON pins to act as
driving signals to implement a charge-pump DC-DC converter (see schematic page
36). This feature is useful in order to boost the VCC supply voltage of the STPM01 to
generate the VOTP voltage (14V to 20V) needed to program the OTP antifuse
elements.
– CSEL In normal operation, if the anti-tamper module is not activated (see PST
configuration bits) the STPM01 will select the channel 1 as source of current
information. For debug or calibration purposes it is possible to select channel 2 as
source of current channel signal when the tamper module is disabled. This is done
setting CSEL mode bit.
– WE (write Enable): This mode signal is used to permanently write to the OTP antifuse
element. When this bit is not set, any write to the configuration bit is recorded in the
shadow latches. When this bit is set the writing is recorded both in the shadow latch
and in the OTP antifuse element.
– Precharge: this command swaps the sequence of data record read, allowing the
reading of the last four data records as first and the first four as second. The reading
sequence will be 5,6,7,8,1,2,3,4. Differently from the other mode signals, the
precharge command is not retained inside the STPM01, in fact it should be sent each
time before the reading of the data records. This is the only command that can be
sent to STPM01 when the TSTD bit has been set.
35/56
Theory of operation
8.21
STPM01
SPI Interface
The SPI interface supports a simple serial protocol, which is implemented in order to enable
a communication between some master system (microcontroller or PC) and the device.
Three tasks can be performed with this interface:
- remote resetting the device,
- reading data records,
- writing the Mode bits and the configuration bits (temporarily or permanently);
Four pins of the device are dedicated to this purpose: SCS, SYN, SCLNCN, SDATD. SCS,
SYN and SCLNLC are all input pins while SDATD can be input or output according if the SPI
is in write or read mode. A high level signal for these pins means a voltage level higher than
0.75xVCC, while a low level signal means a voltage value lower than 0.25xVCC.
The internal register are not directly accessible, rather a 32bit of transmission latches are
used to pre-load the data before being read or written to the internal registers.
The condition in which SCS, SYN and SCLNLC inputs are set to high level determines the
idle state of the SPI interface and no data transfer occurs.
– SCS: as already described in the document, when STPM01 is in standalone mode,
the SYN, SCLNLC and SDATD are used also for providing information on the meter
status (see table 1) and are not used for SPI communication. The SCS pin allows
using the above pins for SPI communication even when the STPM01 is working in
standalone mode, in fact SCS pin enables SPI operation when low. In this section, the
SYN, SCLNLC and SDATD operation as part of the SPI interface is described.
– SYN: this pin operates different functions according to the status of SCS pin. When
SCS is low the SYN pin status select if the SPI is in read (SYN=1) or write mode
(SYN=0). When SCS is high and SYN is also high the results of the input or output
data are transferred to the transmission latches.
– SCLNLC: it is basically the clock pin of the SPI interface. This pin function is also
controlled by the SCS status. If SCS is low, SCLNCL is the input of serial bit
synchronization clock signal. When SCS is high, SCLNLC is also high determining
the idle state of the SPI.
– SDATD is the Data pin. If SCS is low, the operation of SDATD is dependent on the
status of SYN pin. if SYN is high SDATD is the output of serial bit data (read mode) if
SYN is low SDATD is the input of serial bit data signal (write mode). If SCS is high
SDATD is input of idle signal.
Any pin above has internal weak pull up device of nominal 15µA. This means that when
some pin is not forced by external signals, the state of pin is logic high. A high state of any
input pin above is considered as an idle (not active) state. For the SPI to operate correctly
the STPM01 must be correctly supplied as described in the Power Supply section. Idle state
of SPI module is recognized when the signals of pins SYN, SCS, SCLNLC and SDATD are
in a logic high state. Any SPI operations should start from such idle state. The exception to
this rule is when STPM01 has been put into mode of standalone application. In such mode it
can happen that states of pins SCLNLC, SDATD and SYN are not high due to states of
corresponding internal status bits.
When SCS is active (low), signal SDATD should change its state at trailing edge of signal
SCLNLC and the signal SDATD should be stable at next leading edge of signal SCLNLC.
The first valid bit of SDATD is always started with activation of signal SCLNLC.
36/56
STPM01
8.21.1
Theory of operation
Remote Reset
The timing diagram of the operation is shown on the Figure 1. The time step can be as short
as 30ns.
The internal reset signal is named RRR. Unlike the POR, the RRR signal does not cause
the 30ms retard restart of analog module and the 120ms retard restart of digital module.
This signal doesn’t clear the mode signals.
Figure 23. Timing for providing remote reset request
SCS
SYN
SCLNLC
SDATD
t1 t2 t3 t4
t5 t6
t7
t8
t9
t10
All the time intervals must be longer than 30ns. t7 Æ t8 is the reset time, this interval must be longer than 30ns
as well.
8.22
Reading data records
Data records reading will take place most often when there will be an on-board
microcontroller in an application. Such microcontroller will be able to read all measurement
results and all system signals (configuration, calibration, status, mode). Again, the time step
can be as short as 30ns. There are two phases of reading, called latching and shifting.
Latching is used to sample results into transmission latches. The transmission latches are
the Flip-Flops that hold the data in the SPI interface. This is done with the active pulse on
SYN when SCS is idle. The length of pulse on SYN must be longer than 2 periods of
measurement clock, i.e. more than 500ns at 4MHz.
The shifting starts when SCS become active. In the beginning of this phase another, but
much shorter pulse (30ns) on SYN should be applied in order to ensure that an internal
transmission serial clock counter is reset to zero. An alternative way is to extend the pulse
on SYN into the second phase of reading. After that reset is done, a 32 serial clocks per
data record should be applied. Up to 8 data records can be read this way. This procedure
can be aborted at any time by deactivation of SCS (see figure 23).
The first read out byte of data record is Least Significant Byte (LSB) of data value and of
course, the fourth byte is Most Significant Byte (MSB) of data value. Each byte can be
37/56
Theory of operation
STPM01
further divided into a pair of 4-bit nibbles, most and least significant nibble (msn, lsn). This
division makes sense with the MSB of data value because the msn of it holds the parity
code rather than useful data.
Figure 24. Data records reconstruction
The sequence of data record during the reading operation is fixed. Normally, an application
will read 1st,.., 6th data record, the 7th and 8th data record would read only when it need to
fetch the configuration data. However, an application may apply a Precharge command (see
Table 18) prior reading phase. This command forces the device to respond with the
sequence 5th,.., 8th, 1st,.., 4th. Such change of sequence can be used to skip the first four
data records.
The timing diagram of the reading operation is shown on the Figure 22. One can see the
latching and beginning of shifting phase of the first byte (0x5F) of the first data record and
end of reading. Also, both alternatives to reset the internal transmission serial clock counter
is shown in signal SYN.
38/56
STPM01
Theory of operation
Figure 25. Timing for data records reading
S
C
S
f(read)
S
Y
N
S
C
LN
LC
S
D
A
T
D
1stbyte
last bit of 32ndbyte
t1
t2
t3t4 t5 t6
t7 t8
t1 →t2: Latching Phase. Interval value>2/fCLK
t2 →t3: Data latched, SPI idle. Interval value > 30ns
t3 →t4: Enable SPI for read operation. Interval value > 30ns
t4 →t5: Serial clock counter is reset. Interval value > 30ns
t5 →t6: SPI reset and enabled for read operation. Interval value > 30ns
t7: Internal data transferred to SDATD
t8: SDATD data is stable and can be read
The system that reads the data record from the STPM01 should check the integrity of each
data record. If the check fails, the reading should be repeated, but this time only the shifting
should be applied otherwise a new data would be latched into transmission latches and
incorrectly read one would be lost.
Normally, each byte is read out as most significant bit (msb) first. But this can be changed by
setting the MSBF configuration bit in the STPM01 CFL data record. If this is done, each byte
is read out as least significant bit (lsb) first.
8.23
Writing procedure
Each writable bit (Configuration and Mode bits) has its own 6-bit absolute address. For the
configuration bits, the 6-bit address value corresponds to its decimal value, while for the
mode bits the addresses are the ones indicated in the Mode Signal paragraph.
In order to change the state of some latch one must send to STPM01 a byte of data which is
normal way to send data via SPI. This byte consists of 1-bit data to be latched (msb),
followed by 6-bit address of destination latch, followed by 1-bit don’t care data (lsb) which
makes total 8 bits of command byte.
For example, if we would like to set the configuration bit 47 (part of the secondary current
channel calibrator) to 0, we must convert the decimal 47 to its 6-bit binary value: 101111.
The byte command will be then composed like this:
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Theory of operation
STPM01
1 bit DATA value+6-bits address+1 bit (0 or 1) as depicted in figure 11. In this case the
binary command will be 0101111 (0x5F) which is the one depicted in the figure or 0101110
(0x5E).
Figure 26. Timing for writing configuration and mode bits
t1 →t2 (>30ns): SPI out of idle state
t2 →t3 (>30ns): SPI enabled for write operation
t3: data value is placed in SDA
t4: SDA value is stable and shifted into the device
t3 →t5 (>10µs): writing Clock period
t3 →t5: 1 bit Data value
t5 →t6: 6 bits address of the destination latch
t6 →t7: 1 bit EXE command
t8: end of SPI writing
t9: SPI enters idle state
The same procedure should be applied for the mode signals, but in this case the 6-bits
address must be taken from the table 18.
The lsb of command is also called EXE bit because instead of data bit value, the
corresponding serial clock pulse is used to generate the necessary latching signal. This way
the writing mechanism does not need the measurement clock in order to operate, which
makes the operation of SPI module of STPM01 completely independent from the rest of
device logic except from the signal POR.
Commands for changing system signals should be sent during active signals SCS and SYN
as it is shown in the Figure 11. The SYN must be put low in order to disable SDATD output
driver of STPM01 and make the SDATD as an input pin. A string of commands can be send
within one period of active signals SCS and SYN or command can be followed by reading
the data record but, in this case, the SYN should be deactivated in order to enable SDATD
output driver and a SYN pulse should be applied before activation of SCS in order to latch
the data.
Interfacing the standard 3-wire SPI with STPM01 SPI.
Due to the fact a 2-wire SPI is implemented in STPM01 it is clear that sending any
command from a standard 3-wire SPI would require 3-wire to 2-wire interface, which should
produce a proper signal on SDATD from host signals SDI, SDO and SYN. A single gate 340/56
STPM01
Theory of operation
state buffer could be omitted by an emulation of SPI just to send some command. On a
microcontroller this would be done by the following steps:
1. disable the SPI module;
2. set SDI pin which is connected to SDATD to be output;
3. activate SYN first and then SCS;
4. apply new bit value to SDI and activate SCL;
5. deactivate SCL;
6. repeat the last two steps seven times to complete one byte transfer;
7. repeat the last three steps for any remaining byte transfer;
8. set SDI pin to be input;
9. deactivate SCS and the SYN;
10. enable the SPI module;
In case of Precharge command (0xFF), emulation above is not necessary. Due to the pull up
device on the SDATD pin of the STPM01 the processor needs to perform the following
steps:
1. activate SYN first in order to latch the results;
2. after at least 1µs activate SCS;
3. write one byte to the transmitter of SPI (this will produce 8 pulses on SCL with
SDI=1);
4. deactivate SYN;
5. optionally read the data records (the sequence of reading will be altered;
6. deactivate SCS;
Permanent writing of the CFG bits
In order to make a permanent set of some CFG bits, the following procedure should be
conducted:
1. collect all addresses of CFG bits to be permanently set into some list;
2. clear all OTP shadow latches;
3. set the system signal RD;
4. connect a current source of at least +14V, 1mA to 3mA to VOTP;
5. wait for VOTP voltage is stable;
6. set one OTP shadow latch from the list;
7. set the system signal WE;
8. wait for 300µs;
9. clear the system signal WE;
10. clear the OTP shadow latch which was set in step 6;
11. until all wanted CFG bits are permanently set, repeat steps 5 to 11;
12. disconnect the current source;
13. wait for VOTP voltage is less than 3V;
14. clear the system signal RD;
15. read all data records, in the last two of them there is read back of CFG bits;
16. if verification of CFG bits fails and there is still chance to pass, repeat steps 1
to 16.
For steps of set or clear apply the timing shown in Figure 24 with proper signal on the
SDATD. For step 15 apply the timing shown in Figure 23.
41/56
Theory of operation
STPM01
For permanent set of the TSTD bit, which will cause no more writing to the Configuration
bits, the procedure above must be conducted in such way that steps 6 to 13 are performed
in series during single period of active SCS because the idle state of SCS would make the
signal TSTD immediately effective which in turn, would abort the procedure and possibly
destroy the device due to clearing of system signal RD and so, connecting all gates of 3V
NMOS sense amplifiers of already permanently set CFG bits to the VOTP source.
8.24
Energy calculation algorithm
Inside the STPM01 the computing section of the measured active power uses a completely
new signal patented process approach. This approach allows the device to reach high
performances in terms of accuracy.
The signals, coming from the sensors, for the instantaneous voltage:
v(t) = V•sin ωt; where V is the peak voltage and ω is related to the line frequency (see[1])
and the instantaneous current:
i(t) = I • sin (ωt + ϕ); where I is the peak current, ωis related to the line frequency and ϕ is the
phase difference between voltage and current (see[2]).
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STPM01
8.24.1
Theory of operation
Active power
Figure 27. Active energy computation diagram
In the STPM01, after the pre-conditioning and the A/D conversion, the digital voltage signal
(which is dynamically more stable with respect to the current signal) is processed by a
differentiated stage which transforms:
v(t) →v’(t) = dv/dt = V ⋅
ω ⋅ cos ωt − [Eq. 2 - see (5)]
The resulted signal, together with the pre-processed and digitalized current signal:
i(t) = I ⋅ sin(ωt + ϕ); [Eq. 3 - see (6)]
are then available for the calculation process. These digital signals are also provided into
two additional stages which perform the integration of themselves, obtaining:
dv/dt → v(t) = V ⋅ sin ωt; [Eq. 4 - see (7)]
i(t) →
I (t ) = ∫ i (t ) ⋅ dt = −
I
ω
⋅ cos(ωt + ϕ )
[Eq. 5 - see (8)]
Now four signals are available. Combining (pairing) them by means of two multiplying stages
two results are obtained:
43/56
Theory of operation
p/ 1 (t ) =
STPM01
dv
V ⋅ I ⋅ cos ϕ V ⋅ I ⋅ cos(2ωt + ϕ )
⋅ ∫ i(t ) ⋅ dt = −
−
dt
2
2
[Eq. 6 - see (9)]
p/ 2 (t ) = v(t ) ⋅ i(t ) =
V ⋅ I ⋅ cos ϕ V ⋅ I ⋅ cos(2ωt + ϕ )
−
2
2
[Eq. 7 - see (10)]
After these two operations, another stage performs the subtraction between the results p2
and p1 and a division by 2, obtaining the active power:
( p (t ) − p/ 1 (t )) V ⋅ I ⋅ cos ϕ
p(t ) = / 2
=
2
2
[Eq. 8 - see (11)]
In this way, the AC part V•I•cos(2ωt + ϕ)/2 has been then removed from the instantaneous
power.
In the case of current sensors like “Rogowski coils”, which provide the rate of the
instantaneous current signal (di/dt), the initial voltage signal differentiated stage will be
switched off. In this case the signals coming from the A/D conversion and their consequent
integrations will be:
v(t) = V•sin ωt [Eq. 9]
i′(t ) =
di(t )
= − I ⋅ ω ⋅ cos(ωt + ϕ )
dt
[Eq. 10]
V (t ) = ∫ v(t ) ⋅ dt = −
V
ω
⋅ cos ωt
[Eq. 11][
i′′(t ) = ∫ i′(t ) ⋅ dt = i(t ) = − I ⋅ sin(ωt + ϕ )
[Eq. 12]
The signals process flow will be the same as shown in the previous case, and even with the
formulas above, the result will be the same.
The absence of any AC component allows a very fast calibration procedure: it requires just
to set (using the internal device programming registers) the voltage and current sensor
conversion constants, using the effective voltage and current (Vrms, Irms) readings
provided by the device built-in communication port, avoiding the time-averaged readings of
the active power or need for line synchronization.
8.24.2
Reactive power
The reactive power is produced using the already computed signals. In case of shunt sensor
the voltage signal is derived while the current signal is not. A first computation is to multiply
44/56
STPM01
Theory of operation
DS value of integrated voltage channel with the value of integrated current channel, which
yields:
⎛ I
⎞ VI
Q1 (t ) = ∫ v ′(t ) dt ⋅ I (t ) =v (t ) ⋅ I (t ) = (V sin ω t ) ⋅ ⎜ − cos( ω t + ϕ ⎟ =
⋅ (sin ϕ − sin( 2ω t + ϕ ) )
⎝ ω
⎠ 2ω
[Eq. 13]
The second is to multiply filtered DS value of voltage channel with the value of filtered
current channel,
Q2 (t ) = v′(t ) ⋅ i(t ) = Vω cos ωt ⋅ I sin(ωt + ϕ ) =
VI
⋅ ω ⋅ (sin ϕ + sin(2ωt + ϕ ) )
2
[Eq. 14]
From the above results, Q1(t) is proportional to 1/ω while Q2(t) is proportional to ω. The
correct reactive power would result from the following formula:
Q=
1
1 VI
⋅ Q1 (t ) ⋅ ω + Q2 (t ) ⋅ = sin ϕ
ω 2
2
[Eq. 15]
Since the above computation would need significant additional circuitry, the Reactive Power
in the STPM01 is calculated using only the Q1(t) multiplied by ω, it means:
Q3 (t ) =
1
VI
⋅ Q1 (t ) ⋅ ω = ⋅ (sin ϕ − sin( 2ωt + ϕ ) )
2
2
[Eq. 16]
The Reactive Power will present then a ripple at twice the line frequency. Since the average
value of a sinusoid is 0, this ripple does not contribute to the reactive energy calculation over
time, moreover, in the STPM01 the reactive power is not used for meter calibration or to
generate the stepper pulses, then this ripple will not affect the overall system performances.
In case of Rogowsky coil, the same procedure is applied, but the current channel will be
proportional to the derived of the current and the differentiated is bypassed in the voltage
channel, so we have:
VI
⎛ V
⎞
Q1 (t ) = ∫ v (t )dt ⋅ ∫ i′(t )dt =V (t ) ⋅ i (t ) = ⎜ − cos(ωt ) ⎟ ⋅ (− I sin(ωt + ϕ ) ) =
(sin ϕ + sin( 2ωt + ϕ ) )
2ω
⎝ ω
⎠
[Eq. 17]
Q1 (t ) = v(t ) ⋅ i′(t ) = V sin ωt (t ) ⋅ (− Iω cos(ωt + ϕ ) ) = −
VI
⋅ ω ⋅ (sin ϕ − sin( 2ωt + ϕ ) )
2
[Eq. 18]
The reactive power is then calculated:
Q3 (t ) =
1
VI
⋅ Q1 (t ) ⋅ ω = ⋅ (sin ϕ + sin( 2ωt + ϕ ) )
2
2
[Eq. 19]
45/56
Theory of operation
8.24.3
STPM01
Apparent power and RMS values
The RMS values are calculated starting from the following formulas.
Shunt or Current Transformer
T
1 2
I
I (t )dt =
∫
T 0
ω⋅ 2
[Eq. 20]
multiplying Eq 20 by ω, the IRMS value is obtained:
I RMS =
I
2
[Eq. 21]
The RMS voltage value is obtained as:
T
VRMS =
1 2
V
v (t ) dt =
∫
T 0
2
[Eq. 22]
For the Apparent Power another value is produced:
1
V ⋅ω
v′2 (t ) dt =
∫
T 0
2
T
[Eq. 23]
Multiplying Eq.20 and Eq. 23, the Apparent power is produced:
S=
I
V ⋅ ω VI
⋅
=
2
ω⋅ 2
2
[Eq. 24]
Rogowsky Coil
In this case we have:
T
I RMS =
I
1
i′′2 (t )dt =
∫
T 0
2
[Eq. 25]
while VRMS is calculated as in Eq. 22.
The Apparent Power is simple calculated multiplying Eq.25 and Eq. 22.
The DSP then performs the integration of the computed powers into energies. These
integrators are implemented as Up/Down counters and they can rollover. 20-bit output buses
of the counters are assigned as most significant part of energy data records. It is a
responsibility of an application to read the counters at least every second not to miss any
rollover.
46/56
STPM01
9
STPM01 Calibration
STPM01 Calibration
Energy meters based on STPM01 device are calibrated in a fast and easy way. The
calibration is essentially based on the single calibration of the voltage and current channel
considering their RMS values rather than on the frequency of output pulse signal. When the
two channel are calibrated all the other measurement are calibrated too. This allows the
calibration to be performed in only one point shortening the production time of the meter.
This procedure is possible due to the below key points:
– Device is compound of two independent meter channels for line voltage and current
respectively. Each channel includes its own digital calibrator, to adjust the RMS in the
range of ±12.5% in 256 steps, and digital filter, to remove any signal DC component.
All final results are not subject to calibration procedure because they are achieved
from such corrected signals by mathematical modules implemented by hardwired
DSP.
– Device computes different kind of energies: active, reactive and apparent. The active
energy is produced without 2nd harmonic of line frequency. It also computes rms
values of measured voltage and current.
– Device produces an energy output pulse signal but information can also be read
through Serial Port Interface, SPI, and communication channel.
– Device has an embedded memory, 56 bits, used for configuration and calibration
purposes. The value of these bits can be read or they can be changed temporarily or
permanently through SPI communication channel.
Let’s consider the basic information needed to start the calibration procedure:
Table 18.
Line RMS voltage
Vn
(230V)
Line RMS current
In
(5A)
Power sensitivity
P
(LED: P=128000 pulses/kWh, Stepper Motor: PM=P/64= 2000 pulses/kWh)
Shunt Sensor
KS
0,42 mv/A
The following typical STPM01 parameters and constants are also known:
Table 19.
Parameter
Internal reference voltage
VBG
Value
Tolerance
1.23 V
± 2%
223
Internal Calculation Frequency
fM
Amplification of voltage ADC
AV
4
± 1%
Amplification of current ADC
AI
8, 16, 24, 32
± 2%
Gain of differentiator
GDIF
0,6135
Gain of integrator
GINT
0,815
Gain of decimation filter
GDF
1.004
RMS Voltage register length
BV
211
RMS Current register length
BI
216
DUD
217
Constant
Hz
± 50 ppm
47/56
STPM01 Calibration
STPM01
As shown in Tab. 19, only analog parameter are object of calibration because introduce a
certain error. Voltage ADC amplification Av is constant, while Ai is chosen according to used
sensors.
The calibration algorithm will firstly calculate the voltage divider ratio and, as final result, the
correction parameters, called Kv and Ki, which applied to STPM01 voltage and current
measures compensate small tolerances of analog components that affect energy
calculation.
Since Kv and Ki calibration parameters are the decimal representation of the corresponding
configuration bytes CHV and CHP or CHS (respectively voltage channel, primary current
channel and secondary current channel calibration bytes), at the end of calibration CHV and
CHP or CHS (according to the current channel under calibration, primary or secondary
respectively) bits' values are obtained.
In the following procedure CHV, CHP and CHS will be indicated as Cv and Ci.
Through hardwired formulas Kv and Ki tune measured values varying from 0,75 to 1 in 256
steps, according to the value of Cv and Ci (from 0 to 255).
To obtain the greatest correction dynamic initially calibrators are set in the middle of the
range, thus obtaining a calibration range of 12.5% per voltage or current channel:
Calibrator’s value
Kv = Ki = 0.875
Ci = Cv = 128
In this way it is possible to tune Kv and Ki having a precise measured: for example Cv=0
generates a correction factor of -12.5% (Kv=0.75) and Cv=255 determines a correction
factor of +12.5% (Kv=1), and so on.
According to what pointed out above, the following formulas, which relate Kv,i and Cv,i are
obtained:
Kv,i = (Cv,i/128) * 0.125 + 0.75
Cv,i = 1024 * Kv,i - 768.
The calibration procedure will output Cv and Ci values that will allow the above power
sensitivity of the meter.
This sensitivity is used to calculate target frequency at LED pin for nominal voltage and
current values:
XF = f * 64;
with:
f = PM * In * Vn / 3600000;
From values above and for both chosen amplification factor AI=32 and initial calibration data,
the following target values can be calculated:
Target RMS reading for given In:
XI = In * KS * AI * Ki * GINT * GDF * GDIF * BI / (VBG * 1000)=1573
Target RMS reading for given Vn:
XV = f * BV * BI * DUD / (fM * XI)=852
The output of the voltage divider is then:
48/56
STPM01
STPM01 Calibration
VDIV = (XV * VBG)/ (2 * GDIF * AV * Kv * GDF * GINT * BV)= 145,6 mV
Choosing R2=500Ω (connected between VI and VSS), the R1 resistor (connected between
VLINE and VIP) value is obtained:
R1 = R2 * (Vn - VDIV) / VDIV = 789,3 Ω
Indicating with IA and VA the real readings on the STPM01 rms registers of voltage and
current, and with XI and XV ideal values of RMS current and voltage readings already
calculated, the final values for calibrators can be calculated as:
XV = (Kv * VA) / 0.875
XI = (Ki * IA) / 0.875
If the computed final calibration data would fall out of calibration data range, the Energy
Meter should be recognized as bad or the given presumptions and calculations above
should be checked. Otherwise, if the final data of calibrators would be written into Energy
Meter, the rms readings should be very close to target values I and V and the frequency of
LED output should be very close to target value f.
49/56
Schematic
10
STPM01
Schematic
Figure 28. STPM01 Application with one current transformer and one shunt (see user manual
“STPM01: single phase with CT and Shunt” for details)
50/56
STPM01
Schematic
Figure 29. STPM01 with 3X charge pump DC/DC converter
51/56
Package mechanical data
11
STPM01
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
52/56
STPM01
Package mechanical data
TSSOP20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0˚
L
0.45
A
0.0256 BSC
0.60
8˚
0˚
0.75
0.018
8˚
0.024
0.030
A2
A1
b
K
e
L
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
53/56
Package mechanical data
STPM01
Tape & Reel TSSOP20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
MAX.
MIN.
330
13.2
TYP.
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
54/56
TYP
0.504
22.4
0.519
0.882
Ao
6.8
7
0.268
0.276
Bo
6.9
7.1
0.272
0.280
Ko
1.7
1.9
0.067
0.075
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
STPM01
Revision history
12
Revision history
Table 20.
Revision history
Date
Revision
Changes
28-Sep-2004
1
Preliminary Data.
22-Dec-2005
2
Document Updating.
24-Oct-2006
3
The chapter 9 has been updated and the document has been reformatted.
06-Feb-2006
4
The Figure 11. has been changed.
55/56
STPM01
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