STMICROELECTRONICS TS321IDT

TS321
Low power single operational amplifier
Features
■
Large output voltage swing:
0 to 3.5V min. (VCC = 5V)
■
Low supply current: 500µA
■
Low input bias current: 20nA
■
Low input offset voltage: 2mV max.
■
Wide power supply range:
– Single supply: +3V to +30V
– Dual supplies: ±1.5V to ±15V
■
SO-8
(Plastic micropackage)
SOT23-5
(Plastic package)
Stable with high capacitive loads
Description
Pin connections (top view)
The TS321 is intended for cost-sensitive
applications where space saving is of great
importance. This bipolar op-amp offers the
benefits of a reduced component size (SOT23-5
package), with specifications that match (or are
better than) industry standard devices (like the
popular LM358A, LM324, etc.). The TS321 has
an input common mode range (Vicm) that includes
ground, and therefore can be employed in single
supply applications.
November 2007
N.C.
1
Inverting input
2
3
Non-inverting input
V
CC
Rev 5
8
N.C.
-
7
VCC+
+
6
Output
5
N.C.
4
Output
1
V
CC
2
Non-inverting input
3
5
VCC+
4
Inverting input
1/12
www.st.com
12
Circuit schematics
1
TS321
Circuit schematics
Figure 1.
Schematic diagram
V CC
6mA
4mA
100mA
Q5
Q6
CC
Inverting
input
Q2
Q3
Q1
Q7
Q4
R SC
Q11
Non-inverting
input
Output
Q13
Q10
Q8
Q9
Q12
50mA
GND
2/12
TS321
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 1.
Absolute maximum ratings
Symbol
VCC+
Parameter
Supply voltage
Vi
Input voltage
Vid
Differential input voltage
Output short-circuit duration (1)
Iin
Input current
(2)
Value
Unit
±16 to 32
V
-0.3 to +32
V
+32
V
Infinite
50
mA
-65 to +150
°C
Maximum junction temperature
+150
°C
Rthja
Thermal resistance junction to ambient (3)
SOT23-5
SO-8
250
125
°C/W
Rthjc
Thermal resistance junction to case(3)
SOT23-5
SO-8
81
40
°C/W
HBM: human body model(4)
300
Tstg
Tj
ESD
Storage temperature range
MM: machine model
(5)
200
CDM: charged device model(6)
V
1500
1. Short-circuits from the output to VCC can cause excessive heating if VCC > 15V. The maximum output current is
approximately 40mA independent of the magnitude of VCC.
2. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base
junction of the input PNP transistor becoming forward biased and thereby acting as input diodes clamps. In addition to this
diode action, there is also NPN parasitic action on the IC chip. This transistor action can cause the output voltages of the
Op-amps to go to the VCC voltage level (or to ground for a large overdrive) for the time during which an input is driven
negative. This is not destructive and normal output is restored when the input voltage goes back above -0.3V.
3. Short-circuits can cause excessive heating. Destructive dissipation can result from simultaneous short-circuits on all
amplifiers. All values are typical.
4. Human body model: A 100pF capacitor is charged to the specified voltage, then discharged through a 1.5kΩ resistor
between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.
5. Machine model: A 200pF capacitor is charged to the specified voltage, then discharged directly between two pins of the
device with no external series resistor (internal resistor < 5Ω). This is done for all couples of connected pin combinations
while the other pins are floating.
6. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly
to the ground through only one pin. This is done for all pins. The CDM value applies to SO-8 only.
Table 2.
Operating conditions
Symbol
VCC
+
Parameter
Supply voltage
Vicm
Common mode input voltage range (VCC+= 30V)
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
Toper
Operating free-air temperature range
Value
Unit
3 to 30
V
0 to VCC+ -1.5
0 to VCC+ -2
V
-40 to +125
°C
3/12
Electrical characteristics
TS321
3
Electrical characteristics
Table 3.
VCC+ = +5V, VCC- = Ground, Vo = 1.4V, Tamb = +25°C (unless otherwise specified)
Symbol
Vio
Parameter
Input offset voltage (1)
Conditions
TS321
TS321A
Tmin ≤ Tamb ≤ Tmax
TS321
TS321A
Iio
Input offset current
Iib
Input bias current (2)
Avd
Large signal voltage
gain
SVR
Supply voltage rejection
Rs ≤ 10kΩ, VCC+ = 5 to 30V
ratio
ICC
Supply current, no load
Max.
0.5
4
2
VCC+ = +15V, RL = 2kΩ, Vo = 1.4V to 11.4V
Tmin ≤ Tamb ≤ Tmax
mV
2
30
50
nA
20
150
200
nA
50
25
100
65
110
VCC+ = +5V
VCC+ = +30V
Tmin ≤ Tamb ≤ Tmax
VCC+ = +5V
VCC+ = +30V
Isource
Output current source
Vid = +1V
VCC+ = +15V, Vo = +2V
Output sink current
Vid = -1V
VCC+ = +15V, Vo = +2V
VCC+ = +15V, Vo = +0.2V
Short-circuit to ground
VCC+ = +15V
+
Unit
5
3
Tmin ≤ Tamb ≤ Tmax
Common mode rejection
Rs ≤ 10kΩ
ratio
Io
Typ.
Tmin ≤ Tamb ≤ Tmax
CMR
Isink
Min.
V/mV
dB
500
600
800
900
600
900
1000
µA
65
85
dB
20
40
mA
10
12
20
50
mA
µA
40
mA
VOH
VCC = +30V, RL = 2kΩ
Tmin ≤ Tamb ≤ Tmax
VCC+ = +30V, RL = 10kΩ
High level output voltage
Tmin ≤ Tamb ≤ Tmax
VCC+ = +5V, RL = 2kΩ
Tmin ≤ Tamb ≤ Tmax
VOL
Low level output voltage
RL = 10kΩ
Tmin ≤ Tamb ≤ Tmax
SR
Slew rate
VCC+ = +15V, Vi = 0.5 to 3V, RL = 2kΩ,
CL = 100pF, unity gain
0.4
V/μs
Gain bandwith product
VCC+ = 30V, f = 100kHz, Vin = 10mV,
RL = 2kΩ, CL = 100pF
0.8
MHz
GBP
4/12
26
25.5
27
26.5
3.5
3
60
27
28
5
V
15
20
mV
TS321
Table 3.
Symbol
φm
THD
en
Electrical characteristics
VCC+ = +5V, VCC- = Ground, Vo = 1.4V, Tamb = +25°C (unless otherwise specified)
Parameter
Conditions
Phase margin
Total harmonic distortion
f = 1kHz, AV = 20dB, RL = 2kΩ, Vo = 2Vpp,
CL = 100pF, VCC+ = +30V
Equivalent input noise
voltage
f = 1kHz, Rs = 100Ω, VCC+ = +30V
Min.
Typ.
Max.
Unit
60
Degrees
0.015
%
40
nV
-----------Hz
1. Vo = 1.4V, Rs = 0Ω, 5V < VCC+ < 30V, 0 < Vicm < VCC+ - 1.5V.
2. The direction of the input current is out of the IC. This current is essentially constant and independent of the state of the
output, therefore there is no change in the load on the input lines.
5/12
Electrical characteristics
Figure 2.
TS321
Current consumption versus
temperature
Figure 3.
AC coupled inverting amplifier
Rf
100kW
CI
A V= -
Rf
R1
(as shown AV = -10)
R1
10kW
Co
0
eo
RB
6.2kW
R3
100kW
eI ~
R2
VCC 100kW
2VPP
RL
10kW
C1
10mF
Figure 4.
Non-inverting DC gain
Figure 5.
R1
100kW
A V = 1 + R2
R1
10kW
(As shown A V = 101)
eO
1/4
TS324
+5V
AC coupled non-inverting amplifier
R2
1MW
A V= 1 + R2
R1
(as shown AV = 11)
C1
0.1mF
Co
0
eo
CI
R1
10kW
e O (V)
RB
6.2kW
R2
1MW
eI ~
R3
1MW
RL
10kW
R4
100kW
VCC
0
Figure 6.
e1
100kW
eO
e2
100kW
e3
100kW
100kW
6/12
e I (mV)
DC summing amplifier
100kW
e4
C2
10mF
100kW
R5
100kW
2VPP
TS321
Macromodel
4
Macromodel
4.1
Important note concerning this macromodel
Please consider the following remarks before using this macromodel.
●
All models are a trade-off between accuracy and complexity (i.e. simulation time).
●
Macromodels are not a substitute to breadboarding; rather, they confirm the validity of
a design approach and help to select surrounding component values.
●
A macromodel emulates the nominal performance of a typical device within specified
operating conditions (temperature, supply voltage, for example). Thus the
macromodel is often not as exhaustive as the datasheet, its purpose is to illustrate the
main parameters of the product.
Data derived from macromodels used outside of the specified conditions (VCC, temperature,
for example) or even worse, outside of the device operating conditions (VCC, Vicm, for
example), is not reliable in any way.
4.2
Macromodel code
** Standard Linear Ics Macromodels, 1993.
** CONNECTIONS :
* 1 INVERTING INPUT
* 2 NON-INVERTING INPUT
* 3 OUTPUT
* 4 POSITIVE POWER SUPPLY
* 5 NEGATIVE POWER SUPPLY
.SUBCKT TS321 1 2 3 4 5
***************************
.MODEL MDTH D IS=1E-8 KF=3.104131E-15 CJO=10F
* INPUT STAGE
CIP 2 5 1.000000E-12
CIN 1 5 1.000000E-12
EIP 10 5 2 5 1
EIN 16 5 1 5 1
RIP 10 11 2.600000E+01
RIN 15 16 2.600000E+01
RIS 11 15 2.003862E+02
DIP 11 12 MDTH 400E-12
DIN 15 14 MDTH 400E-12
VOFP 12 13 DC 0
VOFN 13 14 DC 0
IPOL 13 5 1.000000E-05
CPS 11 15 3.783376E-09
DINN 17 13 MDTH 400E-12
VIN 17 5 0.000000e+00
DINR 15 18 MDTH 400E-12
VIP 4 18 2.000000E+00
FCP 4 5 VOFP 3.400000E+01
FCN 5 4 VOFN 3.400000E+01
FIBP 2 5 VOFN 2.000000E-03
7/12
Macromodel
TS321
FIBN 5 1 VOFP 2.000000E-03
* AMPLIFYING STAGE
FIP 5 19 VOFP 3.600000E+02
FIN 5 19 VOFN 3.600000E+02
RG1 19 5 3.652997E+06
RG2 19 4 3.652997E+06
CC 19 5 6.000000E-09
DOPM 19 22 MDTH 400E-12
DONM 21 19 MDTH 400E-12
HOPM 22 28 VOUT 7.500000E+03
VIPM 28 4 1.500000E+02
HONM 21 27 VOUT 7.500000E+03
VINM 5 27 1.500000E+02
EOUT 26 23 19 5 1
VOUT 23 5 0
ROUT 26 3 20
COUT 3 5 1.000000E-12
DOP 19 25 MDTH 400E-12
VOP 4 25 2.242230E+00
DON 24 19 MDTH 400E-12
VON 24 5 7.922301E-01
.ENDS
4.3
Macromodel electrical characteristics
Table 4.
VCC+ = +3V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless
otherwise specified)
Symbol
Conditions
Vio
Unit
0
mV
Avd
RL = 2kΩ
100
V/mV
ICC
No load, per operator
300
µA
0 to +3.5
V
Vicm
VOH
RL = 2kΩ
3.5
V
VOL
RL = 2kΩ
5
mV
Vo = 0V
40
mA
GBP
RL = 2kΩ, CL = 100pF
0.8
MHz
SR
RL = 2kΩ, CL = 100pF
0.4
V/μs
∅m
RL = 2kΩ, CL = 100pF
60
Degrees
Ios
8/12
Value
TS321
5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
5.1
SOT23-5 package information
Figure 7.
SOT23-5 package mechanical drawing
Table 5.
SOT23-5 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
Mils
Max.
Min.
Typ.
Max.
A
0.90
1.45
35.4
57.1
A1
0.00
0.15
0.00
5.9
A2
0.90
1.30
35.4
51.2
b
0.35
0.50
13.7
19.7
C
0.09
0.20
3.5
7.8
D
2.80
3.00
110.2
118.1
E
2.60
3.00
102.3
118.1
E1
1.50
1.75
59.0
68.8
e
0.95
37.4
e1
1.9
74.8
L
0.35
0.55
13.7
21.6
9/12
Package information
5.2
TS321
S0-8 package information
Figure 8.
SO-8 package mechanical drawing
Table 6.
SO-8 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.010
D
4.80
4.90
5.00
0.189
0.193
0.197
H
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
e
0.004
0.010
0.049
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
1°
8°
1°
8°
ccc
10/12
Inches
0.10
0.004
TS321
6
Ordering information
Ordering information
Table 7.
Order codes
Part number
Temperature
range
Package
Packaging
SOT23-5L
Tape & reel
TS321ILT
Marking
K401
TS321AILT
K402
TS321ID/IDT
-40°C, +125°C
Tube or
Tape & reel
SO-8
TS321AID/AIDT
TS321IYLT(1)
SOT23-5L
(Automotive grade level)
TS321AIYLT(1)
321I
321AI
K406
Tape & reel
K407
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 & Q 002 or equivalent are on-going.
7
Revision history
Table 8.
Document revision history
Date
Revision
30-Jun-2001
1
Initial release.
4-Jul-2005
2
PPAP references inserted in the datasheet, see order codes table.
ESD protection inserted in Table 1: Absolute maximum ratings.
6-Sep-2005
3
Correction of errors in package names and markings in order codes
table.
Minor grammatical and formatting corrections.
4
Missing PPAP references inserted, see order codes table.
Thermal resistance junction to ambient and thermal resistance
junction to case information added in Table 1: Absolute maximum
ratings.
Macromodel updated see Section 4: Macromodel.
5
Added CDM value for SO-8 in Table 1: Absolute maximum ratings.
Added Tj value in Table 1: Absolute maximum ratings.
Macromodel updated see Section 4: Macromodel.
Reformatted package information.
Added footnote in Table 7: Order codes.
Removed TS321IYD/IYDT and TS321AIYD/AIYDT order codes.
12-Dec-2005
8-Nov-2007
Changes
11/12
TS321
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12/12