FREESCALE K40P121M100SF2

Freescale Semiconductor
Data Sheet: Product Preview
K40 Sub-Family Data Sheet
Document Number: K40P121M100SF2
Rev. 4, 3/2011
K40P121M100SF2
Supports the following:
MK40N512VMC100
Features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Memories and memory interfaces
– Up to 512 KB program flash memory on nonFlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
• Human-machine interface
– Segment LCD controller supporting up to 40
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
• Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (up to x64) integrated
into each ADC
– Two 12-bit DACs
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
• Communication interfaces
– USB full-/low-speed On-the-Go controller with onchip transceiver
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Five UART modules
– Secure Digital host controller (SDHC)
– I2S module
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2011 Freescale Semiconductor, Inc.
Preliminary
Table of Contents
1 Ordering parts...........................................................................3
6.1 Core modules....................................................................19
1.1 Determining valid orderable parts......................................3
6.1.1
Debug trace timing specifications.......................19
2 Part identification......................................................................3
6.1.2
JTAG electricals..................................................20
2.1 Description.........................................................................3
6.2 System modules................................................................23
2.2 Format...............................................................................3
6.3 Clock modules...................................................................23
2.3 Fields.................................................................................3
6.3.1
MCG specifications.............................................23
2.4 Example............................................................................4
6.3.2
Oscillator electrical specifications.......................26
3 Terminology and guidelines......................................................4
6.3.3
32kHz Oscillator Electrical Characteristics.........28
3.1 Definition: Operating requirement......................................4
6.4 Memories and memory interfaces.....................................28
3.2 Definition: Operating behavior...........................................5
6.4.1
Flash (FTFL) electrical specifications.................29
3.3 Definition: Attribute............................................................5
6.4.2
EzPort Switching Specifications.........................30
3.4 Definition: Rating...............................................................6
6.5 Security and integrity modules..........................................31
3.5 Result of exceeding a rating..............................................6
6.6 Analog...............................................................................31
3.6 Relationship between ratings and operating
6.6.1
ADC electrical specifications..............................31
requirements......................................................................6
6.6.2
CMP and 6-bit DAC electrical specifications......38
3.7 Guidelines for ratings and operating requirements............7
6.6.3
12-bit DAC electrical characteristics...................41
3.8 Definition: Typical value.....................................................7
6.6.4
Voltage reference electrical specifications..........44
3.9 Typical value conditions....................................................8
6.7 Timers................................................................................45
4 Ratings......................................................................................8
6.8 Communication interfaces.................................................45
4.1 Thermal handling ratings...................................................9
6.8.1
USB electrical specifications...............................46
4.2 Moisture handling ratings..................................................9
6.8.2
USB DCD electrical specifications......................46
4.3 ESD handling ratings.........................................................9
6.8.3
USB VREG electrical specifications...................46
4.4 Voltage and current operating ratings...............................9
6.8.4
CAN switching specifications..............................47
5 General.....................................................................................10
6.8.5
DSPI switching specifications (low-speed
5.1 Nonswitching electrical specifications...............................10
mode)..................................................................47
5.1.1
Voltage and current operating requirements......10
6.8.6
DSPI switching specifications (high-speed
5.1.2
LVD and POR operating requirements...............11
5.1.3
Voltage and current operating behaviors............12
6.8.7
I2C switching specifications................................50
5.1.4
Power mode transition operating behaviors.......12
6.8.8
UART switching specifications............................50
5.1.5
Power consumption operating behaviors............13
6.8.9
SDHC specifications...........................................50
5.1.6
EMC radiated emissions operating behaviors....16
6.8.10
I2S switching specifications................................51
5.1.7
Designing with radiated emissions in mind.........17
5.1.8
Capacitance attributes........................................17
6.9.1
TSI electrical specifications................................53
5.2 Switching specifications.....................................................17
6.9.2
LCD electrical characteristics.............................54
mode)..................................................................48
6.9 Human-machine interfaces (HMI)......................................53
5.2.1
Device clock specifications.................................17
7 Dimensions...............................................................................55
5.2.2
General switching specifications.........................18
7.1 Obtaining package dimensions.........................................55
5.3 Thermal specifications.......................................................18
8 Pinout........................................................................................56
5.3.1
Thermal operating requirements.........................18
8.1 K40 Signal Multiplexing and Pin Assignments..................56
5.3.2
Thermal attributes...............................................19
8.2 K40 Pinouts.......................................................................60
6 Peripheral operating requirements and behaviors....................19
9 Revision History........................................................................61
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
2
Preliminary
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK40 and MK40.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K40
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
3
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
EX = 64 QFN (9 mm x 9 mm)
LH = 64 LQFP (10 mm x 10 mm)
LK = 80 LQFP (12 mm x 12 mm)
MB = 81 MAPBGA (8 mm x 8 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
MF = 196 MAPBGA (15 mm x 15 mm)
MJ = 256 MAPBGA (17 mm x 17 mm)
CCC
Maximum CPU frequency (MHz)
•
•
•
•
•
50 = 50 MHz
72 = 72 MHz
100 = 100 MHz
120 = 120 MHz
150 = 150 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK40N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
4
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
5
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
6
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
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- No permanent failure
∞
–∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
7
Ratings
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
4 Ratings
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
8
Preliminary
Freescale Semiconductor, Inc.
Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 85°C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
mA
–0.3
5.5
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
9
General
Symbol
VAIO
ID
Description
Min.
Max.
Unit
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
VREGIN
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
5 General
5.1 Nonswitching electrical specifications
5.1.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
VBAT
VIH
VIL
VHYS
RTC battery supply voltage
Notes
Input high voltage
Input low voltage
Input hysteresis
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
10
Preliminary
Freescale Semiconductor, Inc.
General
Table 1. Voltage and current operating requirements (continued)
Symbol
IIC
Description
Min.
Notes
1
0
DC injection current — total MCU limit, includes sum
of all stressed pins
• VIN < VSS
VRFVBAT
Unit
DC injection current — single pin
• VIN < VSS
VRAM
Max.
–0.2
mA
1
VDD voltage required to retain RAM
VBAT voltage required to retain the VBAT register file
0
–5
mA
1.2
—
V
TBD
—
V
1. All functional non-supply pins are internally clamped to VSS, and induce an injection current when VIN is less than VSS. The
IIC maximum operating requirement should not be exceeded. If this requirement cannot be met, the input must be current
limited to the value specified.
5.1.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
TBD
1.1
TBD
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
TBD
2.56
TBD
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
TBD
2.70
TBD
V
VLVW2H
• Level 2 falling (LVWV=01)
TBD
2.80
TBD
V
VLVW3H
• Level 3 falling (LVWV=10)
TBD
2.90
TBD
V
VLVW4H
• Level 4 falling (LVWV=11)
TBD
3.00
TBD
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
60
TBD
1.60
mV
TBD
V
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
TBD
1.80
TBD
V
VLVW2L
• Level 2 falling (LVWV=01)
TBD
1.90
TBD
V
VLVW3L
• Level 3 falling (LVWV=10)
TBD
2.00
TBD
V
VLVW4L
• Level 4 falling (LVWV=11)
TBD
2.10
TBD
V
VHYSL
Notes
Low-voltage inhibit reset/recover hysteresis —
low range
40
mV
VBG
Bandgap voltage reference
TBD
1.00
TBD
V
tLPO
Internal low power oscillator period
TBD
1000
TBD
μs
factory trimmed
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
11
General
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
TBD
1.1
TBD
V
Notes
5.1.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin)
—
1
μA
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
30
50
kΩ
2
RPD
Internal pulldown resistors
30
50
kΩ
3
VOH
Description
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
1
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.1.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
12
Preliminary
Freescale Semiconductor, Inc.
General
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
Unit
Notes
—
300
μs
1
• RUN → VLLS1
—
4.1
μs
• VLLS1 → RUN
—
123.8
μs
• RUN → VLLS2
—
4.1
μs
• VLLS2 → RUN
—
49.3
μs
• RUN → VLLS3
—
4.1
μs
• VLLS3 → RUN
—
49.2
μs
• RUN → LLS
—
4.1
μs
• LLS → RUN
—
5.9
μs
• RUN → STOP
—
4.1
μs
• STOP → RUN
—
4.2
μs
• RUN → VLPS
—
4.1
μs
• VLPS → RUN
—
5.8
μs
After a POR event, amount of time from the point VDD
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
RUN → VLLS1 → RUN
RUN → VLLS2 → RUN
RUN → VLLS3 → RUN
RUN → LLS → RUN
RUN → STOP → RUN
RUN → VLPS → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.1.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
TBD
mA
1
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
13
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash
Max.
Unit
Notes
2
• @ 1.8V
• @ 3.0V
IDD_RUN
Typ.
—
40
TBD
mA
—
42
TBD
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
3
• @ 1.8V
• @ 3.0V
IDD_RUN_M Run mode current — all peripheral clocks
enabled and peripherals active, code executing
AX
from flash
• @ 1.8V
• @ 3.0V
—
55
TBD
mA
—
56
TBD
mA
4
—
85
TBD
mA
—
85
TBD
mA
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
35
TBD
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
15
TBD
mA
5
IDD_STOP
Stop mode current at 3.0 V
—
0.4
TBD
mA
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.25
TBD
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
TBD
TBD
mA
7
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
1.05
TBD
mA
8
IDD_VLPS
Very-low-power stop mode current at 3.0 V
—
50
TBD
μA
IDD_LLS
Low leakage stop mode current at 3.0 V
—
12
TBD
μA
—
8
TBD
μA
IDD_VLLS3
Very low-leakage stop mode 3 current at 3.0 V
• 128KB RAM devices
IDD_VLLS2
Very low-leakage stop mode 2 current at 3.0 V
—
4
TBD
μA
IDD_VLLS1
Very low-leakage stop mode 1 current at 3.0 V
—
2
TBD
μA
IDD_VBAT
Average current when CPU is not accessing
RTC registers at 3.0 V
—
550
TBD
nA
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral
clocks disabled.
3. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, but peripherals are not in active operation.
4. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode.
6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
disabled. Code executing from flash.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
14
Preliminary
Freescale Semiconductor, Inc.
General
7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
disabled.
9. Includes 32kHz oscillator current and RTC operation.
5.1.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks disabled except FTFL
LVD disabled, USB regulator disabled
No GPIOs toggled
Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
15
General
•
•
•
•
All peripheral clocks enabled but peripherals are not in active operation
LVD disabled, USB regulator disabled
No GPIOs toggled
Code execution from flash
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
5.1.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
dBμV
1, 2
—
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
TBD
VRE2
Radiated emissions voltage, band 2
50–150
TBD
VRE3
Radiated emissions voltage, band 3
150–500
TBD
VRE4
Radiated emissions voltage, band 4
500–1000
TBD
0.15–1000
TBD
VRE_IEC_SAE IEC and SAE level
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
16
Preliminary
Freescale Semiconductor, Inc.
General
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/
Wideband TEM (GTEM) Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5.1.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.1.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.2 Switching specifications
5.2.1 Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
100
MHz
System and core clock when USB in operation
20
—
MHz
Bus clock
—
50
MHz
Flash clock
—
25
MHz
Notes
Normal run mode
fSYS
fSYS_USB
fBUS
fFLASH
VLPR mode
fSYS
System and core clock
—
2
MHz
fBUS
Bus clock
—
2
MHz
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
17
General
Symbol
fFLASH
Description
Flash clock
Min.
Max.
Unit
—
1
MHz
Notes
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
2
External reset pulse width (digital glitch filter disabled)
TBD
—
2
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
3
• Slew disabled
—
12
ns
• Slew enabled
—
36
ns
Port rise and fall time (low drive strength)
1.
2.
3.
4.
4
• Slew disabled
—
32
ns
• Slew enabled
—
36
ns
The greater synchronous and asynchronous timing must be met.
This is the shortest pulse that is guaranteed to be recognized.
75pF load
15pF load
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
°C
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
18
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5.3.2 Thermal attributes
Board
type
Symbol
Description
121
MAPBGA
Unit
Notes
Single-layer RθJA
(1s)
Thermal resistance, junction to ambient (natural
convection)
TBD
°C/W
1
Four-layer
(2s2p)
Thermal resistance, junction to ambient (natural
convection)
TBD
°C/W
1
Single-layer RθJMA
(1s)
Thermal resistance, junction to ambient (200 ft./min.
air speed)
TBD
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal resistance, junction to ambient (200 ft./min.
air speed)
TBD
°C/W
1
—
RθJB
Thermal resistance, junction to board
TBD
°C/W
2
—
RθJC
Thermal resistance, junction to case
TBD
°C/W
3
—
ΨJT
Thermal characterization parameter, junction to
package top outside center (natural convection)
TBD
°C/W
4
1.
RθJA
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
6 Peripheral operating requirements and behaviors
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Symbol
Description
Tcyc
Clock period
Min.
Max.
Unit
Frequency dependent
MHz
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
19
Peripheral operating requirements and behaviors
Table 10. Debug trace operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
2
—
ns
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 11. JTAG limited voltage range electricals
Symbol
J1
J2
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
TCLK cycle period
ns
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
20
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 11. JTAG limited voltage range electricals (continued)
Symbol
J3
Description
Min.
Max.
TCLK clock pulse width
Unit
ns
• Boundary Scan
50
—
• JTAG and CJTAG
20
—
• Serial Wire Debug
10
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 12. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
J2
TCLK cycle period
J3
TCLK clock pulse width
ns
ns
• Boundary Scan
50
—
• JTAG and CJTAG
25
—
• Serial Wire Debug
12.5
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
21
Peripheral operating requirements and behaviors
Table 12. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 5. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 6. Boundary scan (JTAG) timing
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
22
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 7. Test Access Port timing
TCLK
J14
J13
TRST
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
23
Peripheral operating requirements and behaviors
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
TBD
—
µA
Internal reference (slow clock) startup time
—
TBD
4
µs
Δfdco_res_t
Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
—
± 0.1
± 0.3
%fdco
1
Δfdco_res_t
Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+ 0.5
± 3.5
%fdco
1
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.5
± TBD
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
3.4
—
4
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
3
—
5
MHz
Internal reference (fast clock) current
—
TBD
—
µA
Internal reference startup time (fast clock)
—
TBD
TBD
µs
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25°C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Iints
tirefsts
Δfdco_t
Iintf
tirefstf
Notes
- 1.0
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
2, 3
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
24
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol
Description
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
Min.
Typ.
Max.
Unit
Notes
—
23.99
—
MHz
4, 5
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
—
TBD
TBD
ps
6
Jacc_fll
FLL accumulated jitter of DCO output over a 1µs
time window
—
TBD
TBD
ps
6
FLL target frequency acquisition time
—
—
1
ms
7
48.0
—
100
MHz
—
950
—
µA
tfll_acquire
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1=8MHz,
fpll_ref=2MHz, VDIV multiplier=48)
8
fpll_ref
PLL reference frequency range
2.0
—
4.0
MHz
Jcyc_pll
PLL period jitter
—
400
—
ps
9, 10
Jacc_pll
PLL accumulated jitter over 1µs window
—
TBD
—
ps
9, 10
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
0.15 +
1075(1/
fpll_ref)
ms
11
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification was obtained at internal frequency of TBD.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
25
Peripheral operating requirements and behaviors
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1
Symbol
VDD
IDDOSC
IDDOSC
Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz
—
300
—
μA
• 16 MHz
—
700
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz
—
800
—
μA
• 16 MHz
—
1.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
2, 4
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
26
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. Oscillator DC electrical specifications (continued)
Symbol
RS
Description
Min.
Typ.
Max.
Unit
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
1.
2.
3.
4.
5.
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using either the integrated capacitors or by using external components.
When low power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2
Symbol
Oscillator frequency specifications
Table 15. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Notes
1
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
27
Peripheral operating requirements and behaviors
Table 15. Oscillator frequency specifications (continued)
Symbol
tcst
Description
Min.
Typ.
Max.
Unit
Notes
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
TBD
—
ms
2, 3
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
800
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
4
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
3
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
2. Proper PC board layout procedures must be followed to achieve specifications.
3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1
Symbol
32kHz oscillator DC electrical specifications
Table 16. 32kHz oscillator DC electrical specifications
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
2.5
—
pF
Cload
Internal load capacitance (programmable)
—
15
—
pF
Peak-to-peak amplitude of oscillation
—
0.6
—
V
Notes
VBAT
RF
Vpp
6.3.3.2
Symbol
fosc_lo
tstart
32kHz oscillator frequency specifications
Table 17. 32kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32
—
kHz
Crystal start-up time
—
1000
—
ms
1
1. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
28
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module.
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 18. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm4
thversscr
Longword Program high-voltage time
—
20
TBD
μs
Sector Erase high-voltage time
—
20
100
ms
1
—
160
800
ms
1
Notes
thversblk256k Erase Block high-voltage time for 256 KB
Notes
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Symbol
Flash timing specifications — commands
Table 19. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
—
—
1.4
ms
Read 1s Block execution time
trd1blk256k
• 256 KB data flash
trd1sec2k
Read 1s Section execution time (flash sector)
—
—
40
μs
1
tpgmchk
Program Check execution time
—
—
35
μs
1
trdrsrc
Read Resource execution time
—
—
35
μs
1
tpgm4
Program Longword execution time
—
50
TBD
μs
Erase Flash Block execution time
tersblk256k
tersscr
• 256 KB data flash
Erase Flash Sector execution time
2
—
160
800
ms
—
20
100
ms
2
Program Section execution time
tpgmsec512
• 512 B flash
—
TBD
TBD
ms
tpgmsec1k
• 1 KB flash
—
TBD
TBD
ms
tpgmsec2k
• 2 KB flash
—
TBD
TBD
ms
trd1all
Read 1s All Blocks execution time
—
—
2.8
ms
trdonce
Read Once execution time
—
—
35
μs
Program Once execution time
—
50
TBD
μs
tpgmonce
1
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
29
Peripheral operating requirements and behaviors
Table 19. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
tersall
Erase All Blocks execution time
—
320
1600
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
35
μs
1
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3
Flash (FTFL) current and power specfications
Table 20. Flash (FTFL) current and power specfications
Symbol
Description
IDD_PGM
Worst case programming current in program flash
6.4.1.4
Symbol
Typ.
Unit
10
mA
Reliability specifications
Table 21. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k
Data retention after up to 10 K cycles
5
TBD
—
years
2
tnvmretp1k
Data retention after up to 1 K cycles
10
TBD
—
years
2
tnvmretp100
Data retention after up to 100 cycles
15
TBD
—
years
2
10 K
TBD
—
cycles
3
nnvmcycp
Cycling endurance
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
30
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 22. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid (setup)
—
12
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DP3.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
31
Peripheral operating requirements and behaviors
The ADCx_DP2 and ADCx_DM2 ADC inputs are used as the PGA inputs and are not
direct device pins. Accuracy specifications for these pins are defined in Table 25 and
Table 26.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1
16-bit ADC operating conditions
Table 23. 16-bit ADC operating conditions
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDDVDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSSVSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
Reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input
capacitance
• 16 bit modes
—
8
10
pF
• 8/10/12 bit
modes
—
4
5
—
2
5
Symbol
RADIN
RAS
fADCK
fADCK
Crate
Input resistance
Analog source
resistance
13/12 bit modes
ADC conversion
clock frequency
≤13 bit modes
ADC conversion
clock frequency
16 bit modes
ADC conversion
rate
≤13
fADCK < 4MHz
Notes
kΩ
3
—
—
5
kΩ
4
1.0
—
18.0
MHz
5
2.0
—
12.0
MHz
6
bit modes
18.484
—
818.330
Ksps
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock =
50MHz
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
32
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. 16-bit ADC operating conditions (continued)
Symbol
Crate
Description
Conditions
ADC conversion
rate
16 bit modes
Min.
Typ.1
Max.
Unit
Notes
7
No ADC hardware
averaging
37.037
—
361.402
Ksps
Continuous
conversions enabled
Peripheral clock =
50MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS/
CAS time constant should be kept to <1ns.
4. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
5. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
6. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
7. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
R ADIN
ADC SAR
ENGINE
V ADIN
C AS
V AS
R ADIN
INPUT PIN
INPUT PIN
R ADIN
R ADIN
INPUT PIN
C ADIN
Figure 10. ADC input impedance equivalency diagram
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
33
Peripheral operating requirements and behaviors
6.6.1.2
Symbol
IDDA
fADACK
16-bit ADC electrical characteristics
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC=1, ADHSC=0
—
2.4
—
MHz
• ADLPC=1, ADHSC=1
—
4.0
—
MHz
tADACK = 1/
fADACK
• ADLPC=0, ADHSC=0
—
5.2
—
MHz
• ADLPC=0, ADHSC=1
—
6.2
—
MHz
Supply current
ADC
asynchronous
clock source
Sample Time
See Reference Manual chapter for sample times
Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC
configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/
converters/ADC_CALCULATOR_CNV.zip?fpsp=1
TUE
DNL
INL
EFS
EQ
Total unadjusted
error
• ≤13 bit modes
±0.8
±TBD
• <12 bit modes
±0.5
±1
Differential nonlinearity
• ≤13 bit modes
±0.7
±TBD
• <12 bit modes
±0.2
±0.5
Integral nonlinearity
• ≤13 bit modes
—
±1.0
±TBD
• <12 bit modes
—
±0.5
±TBD
Full-scale error
• ≤13 bit modes
—
±0.4
±TBD
• <12 bit modes
—
±1.0
±TBD
• 16 bit modes
—
-1 to 0
—
• ≤13 bit modes
—
—
±0.5
Quantization
error
LSB4
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
Max
averaging
LSB4
VADIN =
VDDA
LSB4
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
34
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Symbol
Description
ENOB
Effective number 16 bit differential mode
of bits
• Avg=32
Min.
Typ.2
Max.
Unit
Notes
5
• Avg=1
TBD
13.6
TBD
bits
TBD
13.2
TBD
bits
TBD
TBD
TBD
bits
TBD
TBD
TBD
bits
16 bit single-ended mode
• Avg=32
• Avg=1
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
16 bit differential mode
6.02 × ENOB + 1.76
dB
5
• Avg=32
—
-94
TBD
dB
—
TBD
TBD
dB
16 bit single-ended mode
• Avg=32
SFDR
Spurious free
dynamic range
16 bit differential mode
5
• Avg=32
TBD
95
—
dB
TBD
TBD
—
dB
16 bit single-ended mode
• Avg=32
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
VTEMP25
Temp sensor
voltage
• –40°C to 25°C
—
TBD
—
mV/°C
• 25°C to 105°C
—
TBD
—
mV/°C
—
TBD
—
mV
25°C
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. Input data is 1 kHz sine wave.
FIGURE TBD
Figure 11. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
35
Peripheral operating requirements and behaviors
FIGURE TBD
Figure 12. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended
modes
6.6.1.3
16-bit ADC with PGA operating conditions
Table 25. 16-bit ADC with PGA operating conditions
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
VREFPGA
PGA ref voltage
Symbol
VADIN
VREFOUT VREFOUT VREFOUT
V
Notes
2, 3
Input voltage
VSSA
—
VDDA
V
VCM
Input Common
Mode range
VSSA
—
VDDA
V
RPGAD
Differntial input
impedance
Gain = 1, 2, 4, 8
—
128
—
kΩ
IN+ to IN-4
Gain = 16, 32
—
64
—
Gain = 64
—
32
—
RAS
Analog source
resistance
—
100
—
Ω
5
TS
ADC sampling
time
1.25
—
—
µs
6
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
6.6.1.4
16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Symbol
Description
IDDA_PGA
Supply current
IDC_PGA
Input DC current
IILKG
Input Leakage
current
Conditions
Min.
Typ.1
Max.
Unit
—
590
TBD
μA
PGA disabled
—
TBD
TBD
Notes
A
2
μA
3
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
36
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
G
BW
Description
Gain4
Input signal
bandwidth
PSRR
Power supply
rejection ration
CMRR
Common mode
rejection ratio
Min.
Typ.1
Max.
• PGAG=0
TBD
0.98
TBD
• PGAG=1
TBD
1.99
TBD
• PGAG=2
TBD
3.97
TBD
• PGAG=3
TBD
7.95
TBD
• PGAG=4
TBD
15.8
TBD
• PGAG=5
TBD
31.4
TBD
• PGAG=6
TBD
61.2
TBD
—
—
4
kHz
—
—
40
kHz
TBD
TBD
—
dB
VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
• Gain=1
TBD
TBD
—
dB
• Gain=64
TBD
TBD
—
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
Conditions
• 16-bit modes
• < 16-bit modes
Gain=1
Unit
Notes
RAS < 100Ω
VOFS
Input offset
voltage
—
0.2
TBD
mV
Gain=1, ADC
Averaging=32
TGSW
Gain switching
settling time
—
—
10
µs
5
dG/dT
Gain drift over
temperature
—
TBD
TBD
ppm/°C
0 to 50°C
—
TBD
TBD
ppm/°C
—
TBD
TBD
ppm/°C
0 to 50°C, ADC
Averaging=32
—
TBD
TBD
%/V
—
TBD
TBD
%/V
VDDA from 1.71
to 3.6V
dVOFS/dT
Offset drift over
temperature
dG/dVDDA
Gain drift over
supply voltage
EIL
Input leakage
error
• Gain=1
• Gain=64
Gain=1
• Gain=1
• Gain=64
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
SNR
Maximum
differential input
signal swing
Signal-to-noise
ratio
V
6
16-bit
differential
mode,
Average=32
where VX = VREFPGA × 0.583
• Gain=1
• Gain=64
TBD
83.0
—
dB
TBD
57.5
—
dB
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
37
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
THD
SFDR
ENOB
SINAD
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
16-bit
differential
mode,
Average=32,
fin=500Hz
Total harmonic
distortion
• Gain=1
• Gain=64
TBD
89.4
—
dB
TBD
90.0
—
dB
Spurious free
dynamic range
• Gain=1
• Gain=64
TBD
90.9
—
dB
TBD
77.0
—
dB
Effective number
of bits
• Gain=1, Average=4
TBD
12.3
—
bits
• Gain=1, Average=8
TBD
12.7
—
bits
• Gain=64, Average=4
TBD
8.4
—
bits
• Gain=64, Average=8
TBD
8.7
—
bits
• Gain=1, Average=32
TBD
13.3
—
bits
• Gain=2, Average=32
TBD
13.1
—
bits
• Gain=4, Average=32
TBD
12.5
—
bits
• Gain=8, Average=32
TBD
11.8
—
bits
• Gain=16, Average=32
TBD
11.1
—
bits
• Gain=32, Average=32
TBD
10.2
—
bits
• Gain=64, Average=32
TBD
9.3
—
bits
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
16-bit
differential
mode,
Average=32,
fin=500Hz
16-bit
differential
mode,
fin=500Hz
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function if input common mode voltage (VCM) and the PGA gain.
3. This is the input leakage current of the module in addition to the PAD leakage current.
4. Gain = 2PGAG
5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
IDDHS
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
—
—
200
μA
Supply current, High-speed mode (EN=1, PMODE=1)
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
38
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 27. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
—
20
μA
VSS – 0.3
—
VDD
V
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
VAIN
Analog input voltage
VAIO
Analog input offset voltage
VH
Analog comparator hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
120
250
600
ns
Analog comparator initialization delay2
—
—
TBD
ns
6-bit DAC current adder (enabled)
—
7
—
μA
IDAC6b
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
39
Peripheral operating requirements and behaviors
0.08
0.07
0.06
HYSTCTR
Setting
CM P Hystereris (V)
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
40
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP
P Hystereris (V)
0.12
HYSTCTR
Setting
0.1
00
01
0
08
0.08
10
11
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
Vin level (V)
1.9
2.2
2.5
2.8
3.1
Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
TA
Temperature
−40
105
°C
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1
2
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
41
Peripheral operating requirements and behaviors
6.6.3.2
Symbol
12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Description
Min.
Typ.
Max.
Unit
IDDA_DACLP Supply current — low-power mode
—
—
150
μA
IDDA_DACH Supply current — high-speed mode
—
—
700
μA
Notes
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) — lowpower mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) — highpower mode
—
15
30
μs
1
tCCDACLP
Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
—
—
5
μs
1
tCCDACHP
Code-to-code settling time (0xBF8 to 0xC08) —
high-speed mode
1
TBD
—
μs
1
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
100
TBD
mV
Vdacouth
DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2 V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREFO (1.15 V)
—
—
±1
LSB
4
VOFFSET
Offset error
±0.4
—
±0.8
%FSR
5
EG
Gain error
±0.1
—
±0.6
%FSR
5
90
dB
PSRR
1.
2.
3.
4.
Power supply rejection ratio, VDDA > = 2.4 V
60
TCO
Temperature coefficient offset voltage
—
TBD
—
μV/C
TGE
Temperature coefficient gain error
—
TBD
—
ppm of
FSR/C
AC
Offset aging coefficient
—
—
TBD
μV/yr
Rop
Output resistance load = 3 kΩ
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0+100mV to VDACR−100 mV
The DNL is measured for 0+100 mV to VDACR−100 mV
The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
42
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5. Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
Figure 15. Typical INL error vs. digital code
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
43
Peripheral operating requirements and behaviors
Figure 16. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 30. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Supply voltage
1.71
3.6
V
TA
Temperature
−40
105
°C
CL
Output load capacitance
—
100
nF
VDDA
Notes
Table 31. VREF full-range operating behaviors
Symbol
Vout
Description
Min.
Typ.
Max.
Unit
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
TBD
1.2
TBD
V
Notes
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
44
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 31. VREF full-range operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Vout
Voltage reference output with factory trim
TBD
—
TBD
V
Vout
Voltage reference output user trim
1.198
—
1.202
V
Vstep
Voltage reference trim step
—
0.5
—
mV
Vdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
20
mV
Ac
Aging coefficient
—
—
TBD
ppm/year
Ibg
Bandgap only (MODE_LV = 00) current
—
—
TBD
µA
Itr
Tight-regulation buffer (MODE_LV =10) current
—
—
1.1
mA
Load regulation (MODE_LV = 10) current =
±1.0mA
—
—
TBD
V
Tstup
Buffer startup time
—
—
100
µs
DC
Line regulation (power supply rejection)
—
—
TBD
mV
–60
—
TBD
dB
Notes
See
Figure 17
Table 32. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 33. VREF limited-range operating behaviors
Symbol
Vout
Description
Min.
Max.
Unit
Voltage reference output with factory trim
TBD
TBD
V
Notes
TBD
Figure 17. Typical output vs.temperature
TBD
Figure 18. Typical output vs. VDD
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
45
Peripheral operating requirements and behaviors
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 34. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
TBD
TBD
TBD
V
0.8
—
2.0
V
VLGC
Threshold voltage for logic high
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK
USB_DM sink current
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
TBD
0.4
V
6.8.3 USB VREG electrical specifications
Table 35. USB VREG electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
120
TBD
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1
TBD
μA
IDDoff
Quiescent current — Shutdown mode
—
500
—
nA
—
—
TBD
μA
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
VReg33out
Regulator output voltage — Input supply
(VREGIN) > 3.6 V
3
3.3
3.6
V
2.5
2.8
3.6
V
• Run mode
• Standby mode
Notes
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
46
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 35. USB VREG electrical specifications
(continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VReg33out
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.3
—
3.6
V
1
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Current limitation threshold
185
290
395
mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.4 CAN switching specifications
See General switching specifications.
6.8.5 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (low-speed mode)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
12.5
MHz
4 x tBCLK
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) - 4
—
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) - 4
—
ns
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
47
Peripheral operating requirements and behaviors
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
DSPI_SIN
Data
First data
Last data
DS5
DSPI_SOUT
DS6
First data
Data
Last data
Figure 19. DSPI classic SPI timing — master mode
Table 37. Slave mode DSPI timing (low-speed mode)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
6.25
MHz
8 x tBCLK
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
5
—
ns
DS14
DSPI_SCK to DSIP_SIN input hold
15
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
15
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
15
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DSPI_SOUT
First data
DS13
DSPI_SIN
DS12
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 20. DSPI classic SPI timing — slave mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
48
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.6 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (high-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBCLK
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) − 2
—
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) − 2
—
ns
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
TBD
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
4 x tBCLK
—
ns
(tSCK/2) − 2
(tSCK/2 + 2
ns
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
DSPI_SIN
Data
First data
Last data
DS5
DSPI_SOUT
First data
DS6
Data
Last data
Figure 21. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (high-speed mode)
Num
Description
Operating voltage
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
49
Peripheral operating requirements and behaviors
Table 39. Slave mode DSPI timing (high-speed mode) (continued)
Num
Description
Min.
Max.
Unit
DS11
DSPI_SCK to DSPI_SOUT valid
—
TBD
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DSPI_SOUT
First data
DS13
DSPI_SIN
DS12
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 22. DSPI classic SPI timing — slave mode
6.8.7 I2C switching specifications
See General switching specifications.
6.8.8 UART switching specifications
See General switching specifications.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
50
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 40. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed)
0
25
MHz
fpp
Clock frequency (MMC full speed)
0
20
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tTHL
SDHC input setup time
5
—
ns
SD8
tTHL
SDHC input hold time
0
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 23. SDHC timing
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
51
Peripheral operating requirements and behaviors
6.8.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 41. I2S master mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
2 x tSYS
S2
I2S_MCLK pulse width high/low
S3
I2S_BCLK cycle time
S4
I2S_BCLK pulse width high/low
S5
I2S_BCLK to I2S_FS output valid
S6
I2S_BCLK to I2S_FS output invalid
S7
ns
45%
55%
MCLK period
5 x tSYS
—
ns
45%
55%
BCLK period
—
15
ns
-2.5
—
ns
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 24. I2S timing — master mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
52
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 42. I2S slave mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
8 x tSYS
—
ns
S11
I2S_BCLK cycle time (input)
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
10
—
ns
S14
I2S_FS input hold after I2S_BCLK
3
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
S14
I2S_FS (input)
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 25. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 43. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDDTSI
Operating voltage
1.71
—
3.6
V
Target electrode capacitance range
1
20
500
pF
fREFmax
Reference oscillator frequency
—
5.5
TBD
MHz
fELEmax
Electrode oscillator frequency
—
0.5
TBD
MHz
CELE
Notes
1
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
53
Peripheral operating requirements and behaviors
Table 43. TSI electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Internal reference capacitor
TBD
1
TBD
pF
Oscillator delta voltage
TBD
600
TBD
mV
IREF
Reference oscillator current source base current
TBD
1
TBD
μA
2
IELE
Electrode oscillator current source base current
TBD
1
TBD
μA
2
Pres5
Electrode capacitance measurement precision
—
TBD
TBD
%
3
Pres20
Electrode capacitance measurement precision
—
TBD
TBD
%
4
Pres100
Electrode capacitance measurement precision
—
TBD
TBD
%
5
MaxSens2 Maximum sensitivity @ 20 pF electrode
0
0.003
0.25
—
fF/count
6
MaxSens
0.003
—
—
fF/count
7
Resolution
—
—
16
bits
Response time @ 20 pF
8
15
25
μs
Current added in run mode
—
TBD
—
μA
Low power mode current adder
—
1
TBD
μA
CREF
VDELTA
Res
TCon20
ITSI_RUN
ITSI_LP
Maximum sensitivity
Notes
8
1.
2.
3.
4.
5.
6.
The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 μA, REFCHRG = 4), PS = 128,
NSCN = 2; Iext = 16 (EXTCHRG = 15).
7. Typical value depends on the configuration used.
8. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
6.9.2 LCD electrical characteristics
Table 44. LCD electricals
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fFrame
LCD frame frequency
28
30
58
Hz
CLCD
LCD charge pump capacitance — nominal value
—
100
—
nF
1
CBYLCD
LCD bypass capacitance — nominal value
—
100
—
nF
1
CGlass
LCD glass capacitance
—
2000
8000
pF
VIREG
VIREG — HREFSEL = 0
ΔRTRIM
2
• HREFSEL = 0
0.89
1.00
1.15
V
• HREFSEL = 1
1.49
1.67
1.85
V
3.0
—
—
% VIREG
VIREG TRIM resolution
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
54
Preliminary
Freescale Semiconductor, Inc.
Dimensions
Table 44. LCD electricals (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
VIREG ripple
• HREFSEL = 0
—
—
30
mV
• HREFSEL = 1
—
—
50
mV
—
1
—
µA
IVIREG
VIREG current adder — RVEN = 1
IRBIAS
RBIAS current adder
RRBIAS
• HREFSEL = 0
—
10
—
µA
• HREFSEL = 1
—
1
—
µA
—
0.28
—
MΩ
—
2.98
—
MΩ
• HREFSEL = 0
2.0 − 5%
2.0
—
V
• HREFSEL = 1
3.3 − 5%
3.3
—
V
• HREFSEL = 0
3.0 − 5%
3.0
—
V
• HREFSEL = 1
5 − 5%
5
—
V
RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
VLL3
3
3
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL2
Notes
VLL2 voltage
VLL3 voltage
1. The actual value used could vary with tolerance.
2. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
3. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
121-pin MAPBGA
Then use this document number
TBD
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
55
Pinout
8 Pinout
8.1 K40 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
•
PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
I2C1_SDA
•
PTE1
ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT
UART1_RX
SDHC0_D0
I2C1_SCL
•
PTE2
ADC1_SE6a ADC1_SE6a PTE2
SPI1_SCK
UART1_CTS SDHC0_DCL
_b
K
•
PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS SDHC0_CM
_b
D
•
PTE4
DISABLED
PTE4
SPI1_PCS0
UART3_TX
SDHC0_D3
•
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
•
PTE6
DISABLED
PTE6
SPI1_PCS3
UART3_CTS I2S0_MCLK
_b
•
VDD
VDD
VDD
•
VSS
VSS
VSS
•
USB0_DP
USB0_DP
USB0_DP
•
USB0_DM
USB0_DM
USB0_DM
•
VOUT33
VOUT33
VOUT33
•
VREGIN
VREGIN
VREGIN
•
ADC0_DP1
ADC0_DP1
ADC0_DP1
•
ADC0_DM1
ADC0_DM1
ADC0_DM1
•
ADC1_DP1
ADC1_DP1
ADC1_DP1
•
ADC1_DM1
ADC1_DM1
ADC1_DM1
•
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
•
PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
•
PGA1_DP/
ADC1_DP0/
ADC0_DP3
•
PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
•
VDDA
PGA1_DP/
ADC1_DP0/
ADC0_DP3
VDDA
ALT7
EzPort
I2S0_CLKIN
PGA1_DP/
ADC1_DP0/
ADC0_DP3
VDDA
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
56
Preliminary
Freescale Semiconductor, Inc.
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
•
VREFH
VREFH
VREFH
•
VREFL
VREFL
VREFL
•
VSSA
VSSA
VSSA
•
VREF_OUT/ VREF_OUT
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
•
DAC0_OUT/ DAC0_OUT
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
•
DAC1_OUT/ DAC1_OUT
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP2_IN3/
ADC1_SE23
•
XTAL32
XTAL32
XTAL32
•
EXTAL32
EXTAL32
EXTAL32
•
VBAT
VBAT
VBAT
•
PTE24
ADC0_SE17 ADC0_SE17 PTE24
CAN1_TX
UART4_TX
EWM_OUT_
b
•
PTE25
ADC0_SE18 ADC0_SE18 PTE25
CAN1_RX
UART4_RX
EWM_IN
•
PTE26
DISABLED
PTE26
UART4_CTS
_b
RTC_CLKO
UT
•
PTA0
JTAG_TCLK/ TSI0_CH1
SWD_CLK/
EZP_CLK
PTA0
UART0_CTS FTM0_CH5
_b
JTAG_TCLK/ EZP_CLK
SWD_CLK
•
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
•
PTA2
JTAG_TDO/
TRACE_SW
O/EZP_DO
TSI0_CH3
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_SW
O
EZP_DO
•
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
PTA3
UART0_RTS FTM0_CH0
_b
JTAG_TMS/
SWD_DIO
•
PTA4
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4
FTM0_CH1
•
PTA5
DISABLED
PTA5
FTM0_CH2
•
PTA10
DISABLED
PTA10
FTM2_CH0
FTM2_QD_P TRACE_D0
HA
•
PTA11
DISABLED
PTA11
FTM2_CH1
FTM2_QD_P
HB
•
PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
I2S0_TXD
•
PTA13
CMP2_IN1
CMP2_IN1
PTA13
CAN0_RX
FTM1_CH1
I2S0_TX_FS FTM1_QD_P
HB
•
PTA14
DISABLED
PTA14
SPI0_PCS0
UART0_TX
I2S0_TX_BC
LK
•
PTA15
DISABLED
PTA15
SPI0_SCK
UART0_RX
I2S0_RXD
USB_CLKIN
NMI_b
CMP2_OUT
EZP_CS_b
I2S0_RX_BC JTAG_TRST
LK
FTM1_QD_P
HA
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
57
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
PTA16
ALT2
ALT3
ALT4
ALT5
ALT6
SPI0_SOUT
UART0_CTS
_b
I2S0_RX_FS
SPI0_SIN
UART0_RTS
_b
I2S0_MCLK
ALT7
•
PTA16
DISABLED
•
PTA17
ADC1_SE17 ADC1_SE17 PTA17
•
VDD
VDD
VDD
•
VSS
VSS
VSS
•
PTA18
EXTAL
EXTAL
PTA18
FTM0_FLT2
FTM_CLKIN
0
•
PTA19
XTAL
XTAL
PTA19
FTM1_FLT0
FTM_CLKIN
1
•
RESET_b
RESET_b
RESET_b
•
PTA24
DISABLED
PTA24
•
PTA25
DISABLED
PTA25
•
PTA26
DISABLED
PTA26
•
PTA27
DISABLED
PTA27
•
PTA28
DISABLED
PTA28
•
PTA29
DISABLED
PTA29
•
PTB0
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0
I2C0_SCL
FTM1_CH0
FTM1_QD_P LCD_P0
HA
•
PTB1
LCD_P1/
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
LCD_P1/
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_P LCD_P1
HB
•
PTB2
LCD_P2/
LCD_P2/
PTB2
ADC0_SE12/ ADC0_SE12/
TSI0_CH7
TSI0_CH7
I2C0_SCL
UART0_RTS
_b
FTM0_FLT3
LCD_P2
•
PTB3
LCD_P3/
LCD_P3/
PTB3
ADC0_SE13/ ADC0_SE13/
TSI0_CH8
TSI0_CH8
I2C0_SDA
UART0_CTS
_b
FTM0_FLT0
LCD_P3
•
PTB6
LCD_P6/
LCD_P6/
PTB6
ADC1_SE12 ADC1_SE12
LCD_P6
•
PTB7
LCD_P7/
LCD_P7/
PTB7
ADC1_SE13 ADC1_SE13
LCD_P7
•
PTB8
LCD_P8
LCD_P8
PTB8
•
PTB9
LCD_P9
LCD_P9
PTB9
•
PTB10
•
EzPort
I2S0_CLKIN
LPT0_ALT1
UART3_RTS
_b
LCD_P8
SPI1_PCS1
UART3_CTS
_b
LCD_P9
LCD_P10/
LCD_P10/
PTB10
ADC1_SE14 ADC1_SE14
SPI1_PCS0
UART3_RX
FTM0_FLT1
LCD_P10
PTB11
LCD_P11/
LCD_P11/
PTB11
ADC1_SE15 ADC1_SE15
SPI1_SCK
UART3_TX
FTM0_FLT2
LCD_P11
•
PTB16
LCD_P12/
TSI0_CH9
LCD_P12/
TSI0_CH9
PTB16
SPI1_SOUT
UART0_RX
EWM_IN
LCD_P12
•
PTB17
LCD_P13/
TSI0_CH10
LCD_P13/
TSI0_CH10
PTB17
SPI1_SIN
UART0_TX
EWM_OUT_ LCD_P13
b
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
58
Preliminary
Freescale Semiconductor, Inc.
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
•
PTB18
LCD_P14/
TSI0_CH11
LCD_P14/
TSI0_CH11
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_BC
LK
FTM2_QD_P LCD_P14
HA
•
PTB19
LCD_P15/
TSI0_CH12
LCD_P15/
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FTM2_QD_P LCD_P15
HB
•
PTB20
LCD_P16
LCD_P16
PTB20
SPI2_PCS0
CMP0_OUT
LCD_P16
•
PTB21
LCD_P17
LCD_P17
PTB21
SPI2_SCK
CMP1_OUT
LCD_P17
•
PTB22
LCD_P18
LCD_P18
PTB22
SPI2_SOUT
CMP2_OUT
LCD_P18
•
PTB23
LCD_P19
LCD_P19
PTB23
SPI2_SIN
SPI0_PCS5
LCD_P19
•
PTC0
LCD_P20/
LCD_P20/
PTC0
ADC0_SE14/ ADC0_SE14/
TSI0_CH13 TSI0_CH13
SPI0_PCS4
PDB0_EXTR I2S0_TXD
G
LCD_P20
•
PTC1
LCD_P21/
LCD_P21/
PTC1
ADC0_SE15/ ADC0_SE15/
TSI0_CH14 TSI0_CH14
SPI0_PCS3
UART1_RTS FTM0_CH0
_b
LCD_P21
•
PTC2
LCD_P22/
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
LCD_P22/
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
SPI0_PCS2
UART1_CTS FTM0_CH1
_b
LCD_P22
•
PTC3
LCD_P23/
CMP1_IN1
LCD_P23/
CMP1_IN1
PTC3
SPI0_PCS1
UART1_RX
FTM0_CH2
LCD_P23
•
VSS
VSS
VSS
•
VLL3
VLL3
VLL3
•
VLL2
VLL2
VLL2
•
VLL1
VLL1
VLL1
•
VCAP2
VCAP2
VCAP2
•
VCAP1
VCAP1
VCAP1
•
PTC4
LCD_P24
LCD_P24
PTC4
SPI0_PCS0
UART1_TX
FTM0_CH3
CMP1_OUT
LCD_P24
•
PTC5
LCD_P25
LCD_P25
PTC5
SPI0_SCK
LPT0_ALT2
CMP0_OUT
LCD_P25
•
PTC6
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6
SPI0_SOUT
•
PTC7
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
SPI0_SIN
•
PTC8
LCD_P28/
LCD_P28/
PTC8
ADC1_SE4b/ ADC1_SE4b/
CMP0_IN2 CMP0_IN2
•
PTC9
LCD_P29/
LCD_P29/
PTC9
ADC1_SE5b/ ADC1_SE5b/
CMP0_IN3 CMP0_IN3
•
PTC10
LCD_P30/
LCD_P30/
PTC10
ADC1_SE6b/ ADC1_SE6b/
CMP0_IN4 CMP0_IN4
I2C1_SCL
I2S0_RX_FS
LCD_P30
•
PTC11
LCD_P31/
LCD_P31/
PTC11
ADC1_SE7b ADC1_SE7b
I2C1_SDA
I2S0_RXD
LCD_P31
•
PTC12
LCD_P32
LCD_P32
PTC12
PDB0_EXTR
G
EzPort
LCD_P26
LCD_P27
I2S0_MCLK
I2S0_CLKIN
I2S0_RX_BC
LK
LCD_P28
FTM2_FLT0
UART4_RTS
_b
LCD_P29
LCD_P32
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
59
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
•
PTC13
LCD_P33
LCD_P33
PTC13
UART4_CTS
_b
LCD_P33
•
PTC14
LCD_P34
LCD_P34
PTC14
UART4_RX
LCD_P34
•
PTC15
LCD_P35
LCD_P35
PTC15
UART4_TX
LCD_P35
•
PTC16
LCD_P36
LCD_P36
PTC16
CAN1_RX
UART3_RX
LCD_P36
•
PTC17
LCD_P37
LCD_P37
PTC17
CAN1_TX
UART3_TX
LCD_P37
•
PTC18
LCD_P38
LCD_P38
PTC18
UART3_RTS
_b
LCD_P38
•
PTC19
LCD_P39
LCD_P39
PTC19
UART3_CTS
_b
LCD_P39
•
PTD0
LCD_P40
LCD_P40
PTD0
SPI0_PCS0
UART2_RTS
_b
LCD_P40
•
PTD1
LCD_P41/
LCD_P41/
PTD1
ADC0_SE5b ADC0_SE5b
SPI0_SCK
UART2_CTS
_b
LCD_P41
•
PTD2
LCD_P42
LCD_P42
PTD2
SPI0_SOUT
UART2_RX
LCD_P42
•
PTD3
LCD_P43
LCD_P43
PTD3
SPI0_SIN
UART2_TX
LCD_P43
•
PTD4
LCD_P44
LCD_P44
PTD4
SPI0_PCS1
UART0_RTS FTM0_CH4
_b
EWM_IN
•
PTD5
LCD_P45/
LCD_P45/
PTD5
ADC0_SE6b ADC0_SE6b
SPI0_PCS2
UART0_CTS FTM0_CH5
_b
EWM_OUT_ LCD_P45
b
•
PTD6
LCD_P46/
LCD_P46/
PTD6
ADC0_SE7b ADC0_SE7b
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_FLT0
LCD_P46
•
VSS
VSS
VSS
•
VDD
VDD
VDD
•
PTD7
LCD_P47
LCD_P47
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
FTM0_FLT1
LCD_P47
•
PTD8
DISABLED
PTD8
I2C0_SCL
•
PTD9
DISABLED
PTD9
I2C0_SDA
•
PTD10
DISABLED
PTD10
•
PTD11
DISABLED
PTD11
SPI2_PCS0
SDHC0_CLK
IN
•
PTD12
DISABLED
PTD12
SPI2_SCK
SDHC0_D4
•
PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
•
PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
•
PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7
EzPort
LCD_P44
8.2 K40 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
60
Preliminary
Freescale Semiconductor, Inc.
Revision History
NOTE
The 121 MAPBGA ballmap assignments are currently being
developed.
9 Revision History
The following table provides a revision history for this document.
Table 45. Revision History
Rev. No.
Date
Substantial Changes
1
11/2010
Initial public revision
2
3/2011
Many updates throughout
3
3/2011
Added sections that were inadvertently removed in previous revision
4
3/2011
Reworded IIC footnote in "Voltage and Current Operating Requirements"
table.
Added paragraph to "Peripheral operating requirements and behaviors"
section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals"
section.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
61
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Document Number: K40P121M100SF2
Rev. 4, 3/2011
Preliminary
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