NIS5132 Series +12 Volt Electronic Fuse The NIS5132 is a cost effective, resettable fuse which can greatly enhance the reliability of a hard drive or other circuit from both catastrophic and shutdown failures. It is designed to buffer the load device from excessive input voltage which can damage sensitive circuits. It also includes an overvoltage clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue operation. Two thermal options are available, latching and auto−retry. Features • • • • • • • • • • http://onsemi.com 3.6 AMP, 12 VOLT ELECTRONIC FUSE Integrated Power Device Power Device Thermally Protected No External Current Shunt Required 9 V to 18 V Input Range 44 mW Typical Internal Charge Pump Internal Undervoltage Lockout Circuit Internal Overvoltage Clamp (MN1 and MN2 versions) ESD Ratings: Human Body Model (HBM); 1500 V Machine Model (MM); 200 V These Devices are Pb−Free and are RoHS Compliant DFN10 CASE 485C MARKING DIAGRAM 1 Typical Applications • Hard Drives • Mother Board Power Management 32 32B 32H A Y W G 32 AYWG G Pin 1 2 3 4 5 6−10 11 (flag) Function GND dv/dt Enable/Fault ILIMIT NC SOURCE VCC = Latching Version with VClamp = Latching Version without VClamp = Auto−Retry Version with VClamp = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2012 February, 2012 − Rev. 9 1 Publication Order Number: NIS5132/D NIS5132 Series VCC Enable ENABLE/ FAULT Charge Pump SOURCE Current Limit Thermal Shutdown UVLO Voltage Clamp* ILIMIT dv/dt dv/dt Control (*MN1 and MN2 versions) Figure 1. Block Diagram GND Table 1. FUNCTIONAL PIN DESCRIPTION Pin Function Description 1 Ground 2 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional time delay is not required, this pin should be left open. 3 Enable/Fault The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the device is in thermal shutdown. It can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. 4 ILimit 6−10 Source 11 (belly pad) VCC Negative input voltage to the device. This is used as the internal reference for the IC. A resistor between this pin and the source pin sets the overload and short circuit current limit levels. This pin is the source of the internal power FET and the output terminal of the fuse. Positive input voltage to the device. MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage, operating, steady−state (VCC to GND, Note 1) Transient (100 ms) VIN −0.6 to 18 −0.6 to 25 V Thermal Resistance, Junction−to−Air 0.1 in2 copper (Note 2) 0.5 in2 copper (Note 2) qJA Thermal Resistance, Junction−to−Lead (Pin 1) qJL 27 °C/W Thermal Resistance, Junction−to−Case qJC 20 °C/W Pmax 1.3 10.4 W mW/°C Operating Temperature Range (Note 3) TJ −40 to 150 °C Nonoperating Temperature Range TJ −55 to 155 °C Lead Temperature, Soldering (10 Sec) TL 260 °C Total Power Dissipation @ TA = 25°C Derate above 25°C 227 95 °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package. 2. 1 oz. copper, double−sided FR4. 3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the maximum ratings for extended periods of time. http://onsemi.com 2 NIS5132 Series ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 12 V, CL = 100 mF, dv/dt pin open, RLIMIT = 10 W, Tj = 25°C unless otherwise noted.) Characteristics Symbol Min Typ Max Unit POWER FET Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load) Kelvin ON Resistance (Note 4) TJ = 140°C (Note 5) Tdly RDSon Off State Output Voltage (VCC = 18 Vdc, VGS = 0 Vdc, RL = R) 220 35 Voff Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 1 MHz) Continuous Current (TA = 25°C, 0.5 (TA = 80°C, minimum copper) in2 pad) (Note 5) ID ID ms 44 62 55 mW 190 300 mV 250 pF 3.6 1.7 A THERMAL LATCH Shutdown Temperature (Note 5) TSD Thermal Hysteresis (Decrease in die temperature for turn on, does not apply to latching parts) THyst 150 175 200 45 °C °C UNDER/OVERVOLTAGE PROTECTION Output Clamping Voltage (Overvoltage Protection) (VCC = 18 V) (Note 6) VClamp 14 15 16.2 V Undervoltage Lockout (Turn on, voltage going high) VUVLO 7.7 8.5 9.3 V UVLO Hysteresis VHyst − 0.80 − V Kelvin Short Circuit Current Limit (RLimit = 15.4 W, Note 7) ILim−SS 2.75 3.44 4.25 A Kelvin Overload Current Limit (RLimit = 15.4 W, Note 7) ILim−OL CURRENT LIMIT 4.6 A dv/dt CIRCUIT Output Voltage Ramp Time (Enable to VOUT = 11.7 V) tslew Maximum Capacitor Voltage Vmax 0.5 0.9 1.8 ms VCC V ENABLE/FAULT Logic Level Low (Output Disabled) Vin−low 0.35 0.58 0.81 V Logic Level Mid (Thermal Fault, Output Disabled) Vin−mid 0.82 1.4 1.95 V Logic Level High (Output Enabled) Vin−high 1.96 2.64 3.30 V High State Maximum Voltage Vin−max 3.40 4.30 5.2 V −17 −25 mA Logic Low Sink Current (Venable = 0 V) Iin−low Logic High Leakage Current for External Switch (Venable = 3.3 V) Iin−leak 1.0 mA Fan 3.0 Units 2.5 mA Maximum Fanout for Fault Signal (Total number of chips that can be connected to this pin for simultaneous shutdown) TOTAL DEVICE 4. 5. 6. 7. 8. Bias Current (Operational) IBias 1. 8 Bias Current (Shutdown) IBias 1.0 Minimum Operating Voltage (Notes 5 and 8) Vmin Pulse test: Pulse width 300 us, duty cycle 2%. Verified by design. VClamp only in MN1 & MN2 versions. Refer to explanation of short circuit and overload conditions in application note AND8140. Device will shut down prior to reaching this level based on actual UVLO trip point. http://onsemi.com 3 mA 7.6 V NIS5132 Series 60 50_C 50 POWER (W) 25_C 40 30 20 80_C 10 0 0.1 1 10 100 1000 10000 100000 TIME (ms) Figure 2. Power Dissipation vs. Thermal Trip Time +12 V 11 V CC SOURCE NIS5132 3 ILIMIT RS 4 ENABLE GND dv/dt 1 ENABLE 10 9 8 7 6 LOAD 2 GND Figure 3. Application Circuit with Direct Current Sensing +12 V 11 V CC SOURCE NIS5132 3 ILIMIT 4 RS ENABLE GND ENABLE 10 9 8 7 6 dv/dt 1 2 GND Figure 4. Application Circuit with Kelvin Current Sensing http://onsemi.com 4 LOAD NIS5132 Series VCC VCC SOURCE SOURCE RS NIS5135 ILIMIT LOAD dv/dt NIS5132 ENABLE ILIMIT ENABLE GND GND ENABLE Figure 5. Common Thermal Shutdown http://onsemi.com 5 dv/dt LOAD NIS5132 Series 9 0.86 8.8 0.84 0.82 8.4 HYST (V) UVLO (V) 8.6 8.2 8 0.78 0.76 7.8 0.74 7.6 7.4 −50 0.8 −25 0 25 50 75 100 125 0.72 −50 150 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. UVLO Turn−On Figure 7. UVLO Hysteresis 15.3 125 150 1.05 15.2 1 RAMP TIME (ms) 15 14.9 14.8 14.7 0.95 0.9 14.6 14.5 −50 −25 0 25 50 75 100 125 0.85 −50 150 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Output Clamping Voltage (MN1 & MN2 only) Figure 9. Output Voltage dv/dt Rate 1600 1200 CURRENT (mA) VOLTAGE (V) 15.1 800 400 0 0.5 0.6 0.7 FORWARD VOLTAGE (V) Figure 10. Input Transient Response Figure 11. Body Diode Forward Characteristics http://onsemi.com 6 0.8 NIS5132 Series 9 10 OL −40°C CURRENT (A) CURRENT (A) 8 0°C 7 25°C 50°C 6 85°C 5 4 SC 1 0 0.5 1 COPPER AREA 1.5 0.1 2 10 100 (in2) 1000 Rlimit (W) Figure 12. Thermal Limit vs. Copper Area and Ambient Temperature Figure 13. Current Limit vs. Rsense for Direct Current Sensing 4.5 10 4 3 CURRENT (A) CURRENT (A) OL OL 3.5 SC 2.5 2 1.5 SC 1 1 0.5 0 −50 0 50 100 0.1 150 1 10 100 TEMPERATURE (°C) Rsense (W) Figure 14. Direct Current Sensing Levels vs. Temperature for 27 W Sense Resistor Figure 15. Current Limit vs. Rsense for Kelvin Current Sensing 6 4 5.5 3.5 5 OL CURRENT (A) CURRENT (A) OL 4.5 4 SC 3 2.5 2 SC 1.5 3.5 3 −40 −20 0 20 40 60 TEMPERATURE (°C) 80 1 100 −40 Figure 16. Kelvin Current Sensing Levels vs. Temperature for 15 W Sense Resistor −20 0 20 40 60 TEMPERATURE (°C) 80 Figure 17. Kelvin Current Sensing Levels vs. Temperature for 33 W Sense Resistor http://onsemi.com 7 100 NIS5132 Series ON RESISTANCE (mW) 55 50 45 40 7.0 9.0 11 13 15 VCC (V) Figure 18. On Resistance vs. VCC APPLICATION INFORMATION Basic Operation actively limiting the current and the gate is at an intermediate level. For a more detailed description of this circuit please refer to application note AND8140. There are two methods of biasing the current limit circuit for this device. They are shown in the two application figures. Direct current sensing connects the sense resistor between the current limit pin and the load. This method includes the bond wire resistance in the current limit circuit. This resistance has an impact on the current limit levels for a given resistor and may vary slightly depending on the impedance between the sense resistor and the source pins. The on resistance of the device will be slightly lower in this configuration since all five source pins are connected in parallel and therefore, the effective bond wire resistance is one fifth of the resistance for any given pin. The other method is Kelvin sensing. This method uses one of the source pins as the connection for the current sense resistor. This connection senses the voltage on the die and therefore any bond wire resistance and external impedance on the board have no effect on the current limit levels. In this configuration the on resistance is slightly increased relative to the direct sense method since only for of the source pins are used for power. This device is a self−protected, resettable, electronic fuse. It contains circuits to monitor the input voltage, output voltage, output current and die temperature. On application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. The dv/dt of the output voltage will be controlled by the internal dv/dt circuit. The output voltage will slew from 0 V to the rated output voltage in 2 ms, unless additional capacitance is added to the dv/dt pin. The device will remain on as long as the temperature does not exceed the 175°C limit that is programmed into the chip. The current limit circuit does not shut down the part but will reduce the conductivity of the FET to maintain a constant current at the internally set current limit level. The input overvoltage clamp also does not shutdown the part, but will limit the output voltage to 15 V in the event that the input exceeds that level. An internal charge pump provides bias for the gate voltage of the internal n−channel power FET and also for the current limit circuit. The remainder of the control circuitry operates between the input voltage (VCC) and ground. Current Limit The current limit circuit uses a SENSEFET along with a reference and amplifier to control the peak current in the device. The SENSEFET allows for a small fraction of the load current to be measured, which has the advantage of reducing the losses in the sense resistor as well as increasing the value and decreasing the power rating of the sense resistor. Sense resistors are typically in the tens of ohms range with power ratings of several milliwatts making them very inexpensive chip resistors. The current limit circuit has two limiting values, one for overload events which are defined as the mode of operation in which the gate is high and the FET is fully enhanced. The short circuit mode of operation occurs when the device is Overvoltage Clamp (MN1 & MN2 Versions) The overvoltage clamp consists of an amplifier and reference. It monitors the output voltage and if the input voltage exceeds 15 V, the gate drive of the main FET is reduced to limit the output. This is intended to allow operation through transients while protecting the load. If an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the FET combined with the load current. In this event, the thermal protection circuit would shut down the device. http://onsemi.com 8 NIS5132 Series Undervoltage Lockout When this pin is low, the output of the fuse will be turned off. When this pin is high the output of the fuse will be turned−on. If a thermal fault occurs, this pin will be pulled low to an intermediate level by an internal circuit. To use as a simple enable pin, an open drain or open collector device should be connected to this pin. Due to its tri−state operation, it should not be connected to any type of logic with an internal pullup device. If the chip shuts down due to the die temperature reaching its thermal limit, this pin will be pulled down to an intermediate level. This signal can be monitored by an external circuit to communicate that a thermal shutdown has occurred. If this pin is tied to another device in this family (NIS5132 or NIS5135), a thermal shutdown of one device will cause both devices to disable their outputs. Both devices will turn on once the fault is removed for the auto−retry devices. For the latching thermal device, the outputs will be enabled after the enable pin has been pulled to ground with an external switch and then allowed to go high or after the input power has been recycled. For the auto retry devices, both devices will restart as soon as the die temperature of the device in shutdown has been reduced to the lower thermal limit. The thermal options are listed in the ordering table. The undervoltage lockout circuit uses a comparator with hysteresis to monitor the input voltage. If the input voltage drops below the specified level, the output switch will be switched to a high impedance state. dv/dt Circuit The dv/dt circuit brings the output voltage up under a linear, controlled rate regardless of the load impedance characteristics. An internal ramp generator creates a linear ramp, and a control circuit forces the output voltage to follow that ramp, scaled by a factor. The default ramp time is approximately 2 ms. This can be modified by adding an external capacitor at the dv/dt pin. This pin includes an internal current source of approximately 85 nA. Since the current level is very low, it is important to use a ceramic cap or other low leakage capacitor. Aluminum electrolytic capacitors are not recommended for this circuit. The ramp time from 0 to the nominal output voltage can be determined by the following equation, where t is in seconds: t 0*12 + 24e6 @ ǒ50 pF ) C extǓ C ext + t 0−12 24e6 * 50 pF Thermal Protection The NIS5132 includes an internal temperature sensing circuit that senses the temperature on the die of the power FET. If the temperature reaches 175°C, the device will shut down, and remove power from the load. Output power can be restored by either recycling the input power or toggling the enable pin. Power will automatically be reapplied to the load for auto−retry devices once the die temperature has been reduced by 45°C. The thermal limit has been set high intentionally, to increase the trip time during high power transient events. It is not recommended to operate this device above 150°C for extended periods of time. Where: C is in Farads t is in seconds Any time that the unit shuts down due to a fault, enable shut−down, or recycling of input power, the timing capacitor will be discharged and the output voltage will ramp from 0 at turn on. Enable/Fault The Enable/Fault pin is a multi−function, bidirectional pin that can control the output of the chip as well as send information to other devices regarding the state of the chip. Figure 19. Fault/Enable Signal Levels http://onsemi.com 9 NIS5132 Series 4.3 V Startup Blanking* 12 mA 2.64 V En/Fault 1.4 V 0.58 V SD Thermal Shutdown Enable SD + − − + Thermal Reset Thermal SD (*MN1 and MN2 versions) Figure 20. Enable/Fault Simplified Circuit ORDERING INFORMATION Features Package Shipping† NIS5132MN1TXG Thermal Latching with VClamp DFN10 (Pb−Free) 3000 / Tape & Reel NIS5132MN2TXG Thermal Auto−Retry with VClamp DFN10 (Pb−Free) 3000 / Tape & Reel NIS5132MN3TXG Thermal Latching without VClamp DFN10 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NIS5132 Series PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE B D PIN 1 REFERENCE 2X 2X DETAIL A Bottom View (Optional) E EXPOSED Cu TOP VIEW MOLD CMPD 0.15 C (A3) DETAIL B 0.10 C A1 A 10X SIDE VIEW A1 D2 10X 1 DETAIL B Side View (Optional) DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.70 1.90 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 SOLDERING FOOTPRINT* 5 2.6016 E2 K 10 10X 1.8508 2.1746 6 3.3048 b 0.10 C A B 0.05 C A3 C DETAIL A e L ÉÉÉ ÉÉÉ SEATING PLANE 0.08 C 10X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. L1 ÇÇÇ ÇÇÇ ÇÇÇ 0.15 C EDGE OF PACKAGE A B BOTTOM VIEW NOTE 3 10X 0.5651 10X 0.5000 PITCH 0.3008 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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