Rev. 1.0, May. 2010 K4S280832O K4S281632O 128Mb O-die SDRAM 54TSOP(II) with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. -1- Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM Revision History Revision No. 1.0 History - First Spec. Release -2- Draft Date Remark Editor May. 2010 - S.H.Kim K4S280832O K4S281632O datasheet Table Of Contents 128Mb O-die SDRAM 1. KEY FEATURES........................................................................................................................................................... 4 2. GENERAL DESCRIPTION ........................................................................................................................................... 4 3. ORDERING INFORMATION ........................................................................................................................................ 4 4. PACKAGE PHYSICAL DIMENSION ............................................................................................................................ 5 5. FUNCTIONAL BLOCK DIAGRAM ................................................................................................................................ 6 6. PIN CONFIGURATION (TOP VIEW) ............................................................................................................................ 7 7. INPUT/OUTPUT FUNCTION DESCRIPTION .............................................................................................................. 7 8. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... 8 9. DC OPERATING CONDITIONS ................................................................................................................................... 8 10. CAPACITANCE .......................................................................................................................................................... 8 11. DC CHARACTERISTICS (x8)..................................................................................................................................... 9 12. DC CHARACTERISTICS (x16)................................................................................................................................... 10 13. AC OPERATING TEST CONDITIONS ....................................................................................................................... 11 14. OPERATING AC PARAMETER ................................................................................................................................. 12 15. AC CHARACTERISTICS ............................................................................................................................................ 13 16. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS................................................................................................. 13 17. IBIS SPECIFICATION................................................................................................................................................. 14 18. SIMPLIFIED TRUTH TABLE ...................................................................................................................................... 18 -3- Rev. 1.0 SDRAM Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 1. KEY FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM (x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (4K Cycle) • 54pin TSOP II Lead-Free and Halogen-Free package • RoHS compliant 2. GENERAL DESCRIPTION The K4S280832O / K4S281632O is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. 3. ORDERING INFORMATION Part No. Orgainization Max Freq. K4S280832O-LC/L75 16Mb x 8 133MHz (CL=3) K4S280832O-LC/L60 16Mb x 8 166MHz (CL=3) K4S281632O-LC/L75 8Mb x 16 133MHz (CL=3) K4S281632O-LC/L60 8Mb x 16 166MHz (CL=3) [ Table 1 ] Row & Column address configuration Organization Row Address Column Address 16Mx8 A0~A11 A0-A9 8Mx16 A0~A11 A0-A8 -4- Interface Package LVTTL 54pin TSOP(II) Lead-Free & Halogen-Free Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM #27 (10.76) 0.075 MAX NOTE : 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY Detail A (0.50) 0.45 ~ 0.75 [ 0. 25 ) Detail B (R Detail A (R (10°) (4°) 0.05 MIN 0. 15 ) (0.71) 0.80TYP [0.80 ± 0.08] 0. 25 ) 1.20 MAX 1.00 ± 0.10 (10°) 0.10 MAX (R (10°) (10°) (0.80) (1.50) 0.210 ± 0.05 0.1 5) 0.125 - 0.035 [ 0.665 ± 0.05 +0.075 22.22 ± 0.10 (R Unit : mm 11.76 ± 0.20 #1 (1.50) (0.80) #28 10.16 ± 0.10 #54 (0.50) 4. PACKAGE PHYSICAL DIMENSION 0.25TYP Detail B (0° ∼ 8°) +0.10 0.30 - 0.05 +0.10 0.35 - 0.05 Figure 1. 54Pin TSOP(II) Package Dimension -5- Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 5. FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 4M x 8 / 2M x 16 4M x 8 / 2M x 16 Output Buffer 4M x 8 / 2M x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter Column Decoder Col. Buffer LCBR LRAS Address Register CLK 4M x 8 / 2M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LCAS LWE LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE * Samsung Electronics reserves the right to change products or specification without notice. -6- L(U)DQM DQi Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 6. PIN CONFIGURATION (TOP VIEW) x16 x8 VDD VDD DQ0 DQ0 VDDQ VDDQ DQ1 N.C DQ2 DQ1 VSSQ VSSQ DQ3 N.C DQ4 DQ2 VDDQ VDDQ DQ5 N.C DQ6 DQ3 VSSQ VSSQ DQ7 N.C VDD VDD LDQM N.C WE WE CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD x8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS 54Pin TSOP (400mil x 875mil) (0.8 mm Pin pitch) 7. INPUT/OUTPUT FUNCTION DESCRIPTION Pin Name Description CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins. (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. -7- Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 8. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Storage temperature Power dissipation PD 1 W Short circuit current IOS 50 mA NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 9. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit NOTE VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current NOTE : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 10. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol Min Max Unit CCLK 2.5 3.5 pF CIN 2.5 3.8 pF Clock RAS, CAS, WE, CS, CKE, DQM Address CADD 2.5 3.8 pF (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) COUT 4.0 6.0 pF -8- Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 11. DC CHARACTERISTICS (x8) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in powerdown mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P ICC2NS ICC3P ICC3NS 1 40 40 CKE ≤ VIL(max), tCC = 10ns 2 2 2 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 15 15 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 10 CKE ≤ VIL(max), tCC = 10ns 5 5 5 5 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 25 25 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 20 20 mA 60 60 mA 1 ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC ≥ tRC(min) ICC6 mA Burst length = 1 tRC ≥ tRC(min) IO = 0 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N NOTE 75 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N Unit 60 Operating current (Burst mode) Self refresh current Version Test Condition CKE ≤ 0.2V NOTE : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S280832O-LC 4. K4S280832O-LL 5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). -9- mA mA mA 100 100 mA 2 C 2 2 mA 3 L 0.8 0.8 mA 4 Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 12. DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in powerdown mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P ICC2NS ICC3P ICC3NS 1 40 40 CKE ≤ VIL(max), tCC = 10ns 2 2 2 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 15 15 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 10 CKE ≤ VIL(max), tCC = 10ns 5 5 5 5 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 25 25 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 20 20 mA 60 60 mA 1 ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC ≥ tRC(min) ICC6 mA Burst length = 1 tRC ≥ tRC(min) IO = 0 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N NOTE 75 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N Unit 60 Operating current (Burst mode) Self refresh current Version Test Condition CKE ≤ 0.2V NOTE : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S281632O-LC 4. K4S281632O-LL 5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). - 10 - mA mA mA 100 100 mA 2 C 2 2 mA 3 L 0.8 0.8 mA 4 Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 13. AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Figure 3 3.3V 1200Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω 50pF Figure 2. DC output load circuit Vtt = 1.4V 50Ω Output Z0 = 50Ω 50pF Figure 3. AC output load circuit - 11 - Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 14. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version 60 75 Unit Row active to row active delay tRRD(min) 12 15 ns RAS to CAS delay tRCD(min) 18 20 ns tRP(min) 18 20 ns tRAS(min) 42 45 ns 65 ns Row precharge time Row active time tRAS(max) 100 tRC(min) Last data in to row precharge tRDL(min) 2 CLK Last data in to Active delay tDAL(min) 2 CLK + tRP - Last data in to new col. address delay tCDL(min) 1 CLK Last data in to burst stop tBDL(min) 1 CLK 1 CLK Col. address to col. address delay Number of valid output data 60 us Row cycle time tCCD(min) CAS latency=3 2 CAS latency=2 - NOTE : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. 6. tRC = tRFC, tRDL = tWR - 12 - 1 ea Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 15. AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK cycle time 60 Symbol CAS latency=2 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 CAS latency=2 CAS latency=2 Min 6 tCC 1000 - tSAC tOH 75 Max Min 7.5 10 5.4 - 6 2.5 3 - 3 tCH 2.5 2.5 CLK low pulse width tCL 2.5 2.5 Input setup time tSS 1.5 1.5 Input hold time tSH 1 0.8 tSLZ 1 CAS latency=3 CLK to output in Hi-Z CAS latency=2 1000 5 CLK high pulse width CLK to output in Low-Z Max 1 tSHZ 5 5.4 - 6 NOTE : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 4. tSS applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time. tSH applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time. 16. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Typ Max Unit NOTE 1.37 4.37 Volts/ns 3 3.8 Volts/ns 3 Output rise time trh Measure in linear region : 1.2V ~ 1.8V Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6 Volts/ns 1,2 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 2.0 2.9 5.0 Volts/ns 1,2 NOTE : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS. - 13 - Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 17. IBIS SPECIFICATION [ Table 2 ] IOH Characteristics (Pull-up) 200MHz 166MHz 133MHz Min I (mA) Voltage (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 200MHz 166MHz 133MHz Max I (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0 0 0.5 1 1.5 2 2.5 3 0 -100 mA -200 -300 -400 -500 -600 Voltage IOH Min (200MHz/166MHz/133MHz) IOH Max (200MHz/166MHz/133MHz) Figure 4. 200MHz/166MHz/133MHz Pull-up - 14 - 3.5 Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM [ Table 3 ] IOL Characteristics (Pull-down) 200MHz 166MHz 133MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 Voltage (V) 0.0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 200MHz 166MHz 133MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 250 200 mA 150 100 50 0 0 0.5 1 1.5 2 2.5 3 Voltage IOL Min (200MHz/166MHz/133MHz) IOL Max (200MHz/166MHz/133MHz) Figure 5. 200MHz/166MHz/133MHz Pull-down - 15 - 3.5 Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM [ Table 4 ] VDD Clamp @ CLK, CKE, CS, DQM & DQ VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 20 mA 15 10 5 0 0 1 2 Voltage I (mA) Figure 6. Minimum VDD clamp current (Referenced to VDD) - 16 - 3 Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM [ Table 5 ] VSS Clamp @ CLK, CKE, CS, DQM & DQ VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 -3 -2 -1 0 -10 mA -20 -30 -40 -50 -60 Voltage I (mA) Figure 7. Minimum VSS clamp current - 17 - 0 Rev. 1.0 datasheet K4S280832O K4S281632O SDRAM 18. SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Command Register CKEn-1 Mode register set H Auto refresh Refresh Entry Self refresh Exit H CKEn CS RAS CAS WE DQM X L L L L X OP code L L L H X X L H H H X X H L BA0,1 L H H X X X Bank active & row addr. H X L L H H X V Read & column address Auto precharge disable H X L H L H X V Write & column address Auto precharge disable H X L H L L X V H X L H H L X Auto precharge enable Auto precharge enable Burst stop Precharge Bank selection H X Entry H L Exit L H Entry H L Exit L H All banks Clock suspend or active power down Precharge power down mode DQM No operation command L L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V H H X X H X X X L H H H NOTE : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) - 18 - X X A10/AP A0 ~ A9, A11, NOTE 1,2 3 3 3 3 Row address L H L H 4,5 Column address 4,5 X V L X H 4 Column address 4 6 X X X X X X V X X X 7