STi7200 Triple display, HDTV set-top box, dual decoder for H.264 and VC-1 Data brief Features Single-chip, high-definition STB decoder: – H.264 and Microsoft® VC-1 compatible – Linux®, Windows® CE and OS21 compatible ST40 CPU core – Supports NAND flash, NOR flash and Sflash – Local memory 2 × DDR2 333 MHz – Transport filtering and descrambling – Dual H.264, MPEG-2, VC-1 video decoding – SVP compliant – Windows® DRM support – Triple display composition – Integrated VHF channel 3/4 modulator – Dual audio decoder, including Windows Media® Audio 9 (WMA-9) and WMA-9 Pro – DVD data retrieval and decryption DDR2 Hard SDRAM disks 32 32 ST40 core 16 K Icache UDI LMI0 2× SATA Int. control MMU LMI1 32 K Dcache Peripheral I/O and external interrupts Stereo DACs 2× Ethernet MII/RMII 2× FDMA 3× USB 2.0 Connectivity: – Triple USB 2.0 host controller/PHY interface – Digital audio and video auxiliary inputs – Low-cost modem support – Dual 100BT ethernet controller, MAC and MII/RMII interface for external PHY – Dual serial ATA (SATA) – High speed synchronous interface (MPX) to STVi498 cable and DOCSIS front-end chip S/PDIF MII/RMII for 100BT Ethernet ■ PCM in PCM out 1 PCM out 2 analog out 1 analog out 2 ■ – HD DVD/BD compliant – DVR capable – HDMI/HDCP interface with CEC line controller – IQI (Image Quality Improvement) support Audio interfaces Audio decoder Audio decoder ST231 core ST231 core 2× 2× MAFE IR SmartCard interface Tx/Rx interface PWM 2× 4× 5× 8× DISEqC GPIO ILC UARTs SSCs Video decoder VC-1 (inc WMV-9) H264/MPEG-2 6 TSG DMA in 4 TSG DMA out SECTP 6 4 TS inputs February 2011 Clock generator and system services Flex VPE 2D gamma blitter DVP ST231 core Display compositor mix 1 to 3 HD disp proc HDMI HD disp proc EMI EMPI Video decoder VC-1 (inc WMV-9) H264/MPEG-2 Local HD VHF mod Local TLTXT SD Remote TLTXT SD ST231 core DACs VHF DAC DENC DACs DENC DACs Local video output (SD) Remote video output (SD) HDMI PTI 2 DV in PTI 1 Descrmblr STBus DV Local video CH 3/4 out output (HD) out Doc ID 12876 Rev 2 DV out Flash or companion chip 1/4 www.st.com 4 Description 1 STi7200 Description The STi7200 is a new generation, high-definition set-top box/DVD decoder chip that provides very high performance for low-cost HD systems. With enhanced performance over the STi7109, it includes both Windows Media Video 9 and H.264 video decoders for new, low bitrate applications. The STi7200 is able to decode two HD programs. Based on the STBus architecture, this system-on-chip is a full back-end processor for digital terrestrial, satellite, cable and IP high-definition set-top boxes, compliant with ATSC, SMPTE VC-1, DVB, DIRECTV, DCII, OpenCable and ARIB BS4 specifications. The STi7200 includes all processing for DVD applications. 2 Applications The STi7200 demultiplexes, decrypts and decodes HD or SD video streams with associated multichannel audio. Video is output to three independently formatted displays: ● a full resolution display intended for a local HDTV monitor ● a downsampled display intended for a VCR or local SDTV ● an SD resolution display intended for a remote SDTV monitor Connection to the main TV or display panel can be analog (RGB/YUV) through HD DACs, or digital through a copy protected DVI/HDMI. Composite outputs are provided for connection to local and remote TVs or VCR with Rovi™ or Dwight Cavendish protection. Audio is output with optional PCM mixing to an S/PDIF interface, dual PCM interface, or through integrated dual stereo audio DACs. Digitized analog programs can also be input to the STi7200 for reformatting and display. The STi7200 includes a graphics rendering and display capability with a 2D graphics accelerator. A triple display compositor mixes graphics and video with independent composition for each of the TV and VCR or SDTV outputs. Picture In Picture (PIP) is supported. The STi7200 handles up to six external transport streams from different sources. Four transport stream inputs, two transport stream input/outputs and two transport stream outputs are supported. Applications include DVR time-shifted viewing of a terrestrial program, while acquiring an EPG/data stream from a satellite or cable front end. The transport architecture uncouples the transport packet processing from the transport packet collection. The input transport streams are stored in SDRAM after PID filtering and time stamp collection. DMAs fetch data from external memory and inject them to PTIs or transport stream output ports. The flexible descrambling engine is compatible with required standards including DVB, DES, AES and Multi2. The STi7200 has an ST40-210 CPU for applications and device control. A dual 32-bit DDR2 SDRAM interface provides the required bandwidth for dual HD VC-1/H.264 video decoding, and for the CPU and the rest of the system. 2/4 Doc ID 12876 Rev 2 STi7200 Revision history A second memory bus is provided for flash memory, storing resident software, and for connection of peripherals. This bus also has a high speed synchronous mode that can be used to exchange data between two STi7200 devices. A 32-bit MPX initiator (EMI module) and target (EMPI module) interconnect external devices such as the STVi498. A Blu-ray disc and hard disk drive (HDD) can be connected through the serial ATA interfaces (2×). An expansion hard disk drive can be connected through a USB 2.0 port (3×). For IP-TV and home network applications, the two integrated 100BT Ethernet controllers with MII/RMII interface can be used for IP delivery and distribution. The USB or Ethernet interfaces can also be used to connect to a DOCSIS 2.0 CM gateway for interactive cable applications. The STi7200 is supported by STMicroelectronics’ STAPI software. 3 Revision history Table 1. Document revision history Date Revision Changes 07-Dec-2006 1 Initial release. 10-Feb-2011 2 Minor updates to formatting and spelling. Content revised and simplified. Disclaimer page amended. Doc ID 12876 Rev 2 3/4 STi7200 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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