CTLDM8120-M832D SURFACE MOUNT DUAL, P-CHANNEL ENHANCEMENT-MODE SILICON MOSFETS w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CTLDM8120-M832D is an Enhancement-mode Dual P-Channel Field Effect Transistor, manufactured by the P-Channel DMOS Process, designed for high speed pulsed amplifier and driver applications. This MOSFET offers Low rDS(ON) and Low Threshold Voltage. MARKING CODE: CFV • Device is Halogen Free by design TLM832D CASE FEATURES: • Switching Circuits • DC - DC Converters • Battery powered portable devices • ESD protection up to 2kV • Low rDS(ON) (0.24Ω MAX @ VGS=1.8V) • High current (ID=0.95A) • Logic level compatibility MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (Steady State) Continuous Drain Current, t<5.0s Continuous Source Current (Body Diode) Maximum Pulsed Drain Current, tp=10μs Maximum Pulsed Source Current, tp=10μs Power Dissipation (Note 1) Operating and Storage Junction Temperature Thermal Resistance (Note 1) SYMBOL VDS VGS ID ID IS IDM ISM PD TJ, Tstg ΘJA APPLICATIONS: 20 8.0 0.86 0.95 0.36 4.0 4.0 1.65 -65 to +150 76 ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN TYP MAX IGSSF, IGSSR VGS=8.0V, VDS=0 1.0 50 IDSS VDS=20V, VGS=0 5.0 500 BVDSS VGS=0, ID=250μA 20 24 VGS(th) VDS=VGS, ID=250μA 0.45 0.76 1.0 VSD VGS=0, IS=360mA 0.9 rDS(ON) VGS=4.5V, ID=0.95A 0.085 0.150 rDS(ON) VGS=4.5V, ID=0.77A 0.085 0.142 rDS(ON) VGS=2.5V, ID=0.67A 0.130 0.200 rDS(ON) VGS=1.8V, ID=0.2A 0.190 0.240 Qg(tot) VDS=10V, VGS=4.5V, ID=1.0A 3.56 Qgs VDS=10V, VGS=4.5V, ID=1.0A 0.36 Qgd VDS=10V, VGS=4.5V, ID=1.0A 1.52 gFS VDS=10V, ID=810mA 2.0 Crss VDS=16V, VGS=0, f=1.0MHz 80 Ciss VDS=16V, VGS=0, f=1.0MHz 200 Coss VDS=16V, VGS=0, f=1.0MHz 60 ton VDD=10V, VGS=4.5V, ID=0.95A, RG=6.0Ω 20 toff VDD=10V, VGS=4.5V, ID=0.95A, RG=6.0Ω 25 Notes: (1) FR-4 Epoxy PCB with copper mounting pad area of 54mm2 UNITS V V A A A A A W °C °C/W UNITS nA nA V V V Ω Ω Ω Ω nC nC nC S pF pF pF ns ns R2 (2-August 2011) CTLDM8120-M832D SURFACE MOUNT DUAL, P-CHANNEL ENHANCEMENT-MODE SILICON MOSFETS TLM832D CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Gate Q1 2) Source Q1 3) Gate Q2 4) Source Q2 5) Drain Q2 6) Drain Q2 7) Drain Q1 8) Drain Q1 MARKING CODE: CFV R2 (2-August 2011) w w w. c e n t r a l s e m i . c o m