TI SN75LBC174ADW

SLLS446C − OCTOBER 2000 − REVISED MAY 2003
D Designed for TIA/EIA-485, TIA/EIA-422 and
D Driver Positive- and Negative-Current
ISO 8482 Applications
Signaling Rates† up to 30 Mbps
Propagation Delay Times < 11 ns
Low Standby Power Consumption
1.5 mA Max
Output ESD Protection Exceeds 13 kV
D
D
D
D
D
D
D
Limiting
Power-Up and Power-Down Glitch-Free for
Line Insertion Applications
Thermal Shutdown Protection
Industry Standard Pin-Out, Compatible
With SN75174, MC3487, DS96174, LTC487,
and MAX3042
description
The SN65LBC174A and SN75LBC174A are quadruple differential line drivers with 3-state outputs, designed
for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications.
These devices are optimized for balanced multipoint bus transmission at signalling rates up to 30 million bits
per second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate
rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise
coupling to the environment.
N PACKAGE
(TOP VIEW)
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
16-DW PACKAGE
(TOP VIEW)
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
logic diagram (positive logic)
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
1A
1,2EN
2A
3A
3,4EN
4A
20-DW PACKAGE
(TOP VIEW)
1A
1Y
NC
1Z
1,2EN
2Z
NC
2Y
2A
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
7
9
6
5
10
11
12
15
14
13
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
logic diagram (positive logic)
VCC
4A
4Y
NC
4Z
3,4EN
3Z
NC
3Y
3A
1A
1,2EN
2A
3A
3,4EN
4A
1
2
4
5
9
11
8
6
12
14
15
19
18
16
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Copyright  2001 − 20003, Texas Instruments Incorporated
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#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0 !)) '!!&"&#+
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1
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
description (continued)
Each driver features current limiting and thermal-shutdown circuitry making it suitable for high-speed multipoint
applications in noisy environments. These devices are designed using LinBiCMOSt, facilitating low power
consumption and robustness.
The two EN inputs provide pair-wise driver enabling, or can be externally tied together to provide enable control
of all four drivers with one signal. When disabled or powered off, the driver outputs present a high-impedance
to the bus for reduced system loading.
The SN75LBC174A is characterized for operation over the temperature range of 0°C to 70°C. The
SN65LBC174A is characterized for operation over the temperature range of −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
16-PIN PLASTIC
SMALL OUTLINE†
(JEDEC MS-013)
20-PIN PLASTIC
SMALL OUTLINE†
(JEDEC MS-013)
16-PIN PLASTIC
THROUGH-HOLE
(JEDEC MS-001)
SN75LBC174A16DW
SN75LBC174ADW
SN75LBC174AN
0°C to 70°C
Marked as 75LBC174A
SN65LBC174A16DW
SN65LBC174ADW
−40°C to 85°C
Marked as 65LBC174A
† Add R suffix for taped and reeled version.
FUNCTION TABLE
(EACH DRIVER)
INPUT
ENABLE
A
G
L
H
OUTPUTS
Y
Z
H
L
H
H
H
L
OPEN
H
H
L
L
OPEN
L
H
H
OPEN
H
L
OPEN
OPEN
H
L
X
L
Z
Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
LinBiCMOS is a trademark of Texas Instruments.
2
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SN65LBC174AN
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
equivalent input and output schematic diagrams
Y or Z Output
A or EN Input
VCC
VCC
16 V
20 V
100 kΩ
16 V
1 kΩ
Input
Output
16 V
17 V
9V
16 V
absolute maximum ratings†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Voltage range at any bus (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V
Voltage range at any bus (transient pulse through 100 Ω, see Figure 8) . . . . . . . . . . . . . . . . . . . . . −30 V to 30 V
Input voltage range at any A or EN terminal, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Electrostatic discharge: Human body model (see Note 2)
Y, Z, and GND . . . . . . . . . . . . . . . . . . . . . 13 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV
Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to GND.
2. Tested in accordance with JEDEC standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC standard 22, Test Method C101.
PACKAGE
16-PIN DW
20-PIN DW
16-PIN N
DISSIPATION RATING TABLE
DERATING FACTOR‡
ABOVE TA = 25°C
JEDEC
BOARD
MODEL
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
Low K
1200 mW
9.6 mW/°C
769 mW
625 mW
High K
2240 mW
17.9 mW/°C
1434 mW
1165 mW
Low K
1483 mW
11.86 mW/°C
949 mW
771 mW
High K
2753 mW
22 mW/°C
1762 mW
1432 mW
Low K
1150 mW
9.2 mW/°C
736 mW
598 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.
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3
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
recommended operating conditions
Supply voltage, VCC
Voltage at any bus terminal
High-level input voltage, VIH
Low-level input voltage, VIL
NOM
MAX
UNIT
4.75
5
Y, Z
A, EN
Output current
Operating free-air temperature, TA
MIN
5.25
V
−7
12
V
2
0
VCC
0.8
V
−60
60
SN75LBC174A
0
70
SN65LBC174A
−40
85
mA
°C
electrical characteristics over recommended operating conditions
PARAMETER
VIK
VO
Input clamp voltage
VOD(SS)
Steady-state differential output
voltage magnitude‡
TEST CONDITIONS
II = −18 mA
Y or Z, No load
Open-circuit output voltage
MIN
TYP†
−1.5
−0.77
0
1.6
2.5
1
1.6
2.5
VOC(SS)
Steady-state common-mode
output voltage
See Figure 3
2
∆VOC(SS)
Change in steady-state
common-mode output voltage
between logic states
See Figure 3
II
Input current
A, G, G
High-impedance-state output
current
IO(OFF)
Output current with power off
ICC
Supply current
V
1
With common-mode loading, See Figure 2
−0.1
IOZ
V
3
See Figure 1
Short-circuit output current
V
RL = 54 Ω, See Figure 1
Change in steady-state differential
output voltage between logic
states
VTEST = −7 V to 12 V,
See Figure 7
VI = 0 V or VCC,
No load
UNIT
VCC
VCC
No load (open circuit)
∆VOD(SS)
IOS
MAX
0.1
V
2.8
V
−0.02
0.02
V
2.4
−50
50
µA
VI = 0 V
VI = VCC
−200
200
mA
EN at 0 V
−50
50
VCC = 0 V
All drivers enabled
−10
10
All drivers disabled
µA
23
1.5
mA
† All typical values are at VCC = 5 V and 25°C.
‡ The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
of lower output signal into account in determining the maximum signal transmission distance.
4
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SLLS446C − OCTOBER 2000 − REVISED MAY 2003
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high level output
5.5
8
11
ns
Propagation delay time, high-to-low level output
5.5
8
11
ns
tr
tf
Differential output voltage rise time
3
7.5
11
ns
3
7.5
11
ns
0.6
2
0.6
2
Differential output voltage fall time
RL = 54 Ω, CL = 50 pF,
See Figure 4
tsk(p)
Pulse skew |tPLH – tPHL|
tsk(o)
Output skew†
2
ns
tsk(pp)
tPZH
Part-to-part skew‡
3
ns
25
ns
tPHZ
tPZL
Propagation delay time, high-level-output-to-high impedance
25
ns
Propagation delay time, high-impedance-to-high-level output
See Figure 5
ns
Propagation delay time, high-impedance-to-low-level output
30
ns
See Figure 6
tPLZ
Propagation delay time, low-level-output-to-high impedance
20
ns
† Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
‡ Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
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5
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
IOY
Y
II
A
Z
IOZ
VOD
54 Ω
VOY
GND
VI
VOZ
Figure 1. Test Circuit, VOD Without Common-Mode Loading
375 Ω
Y
A
Input
VOD
60 Ω
Z
VTEST = −7 V to 12 V
375 Ω
VTEST
VI
Figure 2. Test Circuit, VOD With Common-Mode Loading
Y
27 Ω
A
Z
Signal
Generator†
27 Ω
CL = 50 pF‡
50 Ω
† PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡ Includes probe and jig capacitance
Figure 3. VOC Test Circuit
6
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• DALLAS, TEXAS 75265
VOC
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
Y
A
CL = 50 pF‡ VOD
RL = 54 Ω
Z
Signal
Generator†
50 Ω
† PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡ Includes probe and jig capacitance
3V
1.5 V
Input
0V
tPLH
tPHL
≈ 1.5 V
90%
0V
10%
Output
tr
≈ −1.5 V
tf
Figure 4. Output Switching Test Circuit and Waveforms
POST OFFICE BOX 655303
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7
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
Y
S1
A
3 V or 0 V w
Output
Z
CL = 50 pF‡
Input
EN
Signal
Generator†
50 Ω
† PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡ Includes probe and jig capacitance
§ 3 V if testing Y output, 0 V if testing Z output
3V
1.5 V
Input
0V
tPZH
0.5 V
VOH
2.3 V
0V
Output
tPHZ
Figure 5. Enable Timing Test Circuit and Waveforms, tPZH and tPHZ
8
POST OFFICE BOX 655303
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RL = 110 Ω
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
5V
RL = 110 Ω
Y
S1
A
0 V or 3 V w
Output
Z
CL = 50 pF‡
Input
EN
Signal
Generator†
50 Ω
† PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡ Includes probe and jig capacitance
§ 3 V if testing Y output, 0 V if testing Z output
3V
1.5 V
Input
0V
tPZL
tPLZ
5V
Output
2.3 V
VOL
0.5 V
Figure 6. Enable Timing Test Circuit and Waveforms, tPZL and tPLZ
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9
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
Y
IO
VI
Z
VTEST
Voltage Source
VTEST = −7 V to 12 V
Slew Rate ≤ 1.2 V/µs
Figure 7. Test Circuit, Short-Circuit Output Current
Y
Z
100 Ω
VTEST
0V
Pulse Generator
15 µs Duration,
1% Duty Cycle
15 µs
1.5 ms
Figure 8. Test Circuit Waveform, Transient Over-Voltage Test
10
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−VTEST
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.5
3.5
VOD − Differential Output Voltage − V
VOD − Differential Output Voltage − V
4
3
VCC = 5.25 V
2.5
VCC = 5 V
2
1.5
VCC = 4.75 V
1
0.5
0
0
20
40
60
80
IO − Output Current − mA
VCC = 5.25 V
2
VCC = 5 V
1.5
VCC = 4.75 V
1
0.5
0
−60
100
−40
Figure 9
SUPPLY CURRENT (FOUR CHANNELS)
vs
SIGNALING RATE
8.5
I CC − Supply Current (Four Channels) − mA
144
Propigation Delay Time − ns
8
VCC = 5.25 V
VCC = 4.75 V
7
6.5
6
5.5
5
−40
100
Figure 10
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
7.5
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
RL = 54 Ω
CL = 50 pF
(Each Channel)
142
140
138
136
134
132
130
128
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
1
Figure 11
10
Signaling Rate − Mbps
100
Figure 12
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11
SLLS446C − OCTOBER 2000 − REVISED MAY 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
3
VOD − Differential Output Voltage − V
RL = 54 Ω
2.5
2
1.5
1
0.5
0
0
0.5 1
1.5 2 2.5 3 3.5 4 4.5 5
VCC − Supply Voltage − V
5.5 6
Figure 13
RL = 54 Ω
CL = 50 pF
Figure 14. Eye Pattern, Pseudorandom Data at 30 Mbps
12
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SLLS446C − OCTOBER 2000 − REVISED MAY 2003
APPLICATION INFORMATION
TMS320F243
DSP
(Controller)
SN65LBC174A
SN65LBC175A
TMS320F241
DSP
(Embedded
Application)
SPISIMO
SPISIMO
IOPA1
(Enable)
IOPA1
SPISTE
SPISTE
SPICLK
SPICLK
IOPA2
(Enable)
IOPA2
IOPA0
(Handshake
/Status)
IOPA0
SPISOMI
SPISOMI
Figure 15. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface
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13
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LBC174A16DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174A16DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174A16DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174A16DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174ADWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC174AN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPD
SN75LBC174A16DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174A16DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174A16DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174A16DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174ADWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC174AN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPD
N / A for Pkg Type
SN75LBC174ANE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPD
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65LBC174A16DWR
DW
16
SITE 60
330
16
10.75
10.7
2.7
12
16
Q1
SN65LBC174ADWR
DW
20
SITE 60
330
24
10.8
13.1
2.65
12
24
Q1
SN75LBC174A16DWR
DW
16
SITE 60
330
16
10.75
10.7
2.7
12
16
Q1
SN75LBC174ADWR
DW
20
SITE 60
330
24
10.8
13.1
2.65
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN65LBC174A16DWR
DW
16
SITE 60
346.0
346.0
33.0
SN65LBC174ADWR
DW
20
SITE 60
346.0
346.0
41.0
SN75LBC174A16DWR
DW
16
SITE 60
346.0
346.0
33.0
SN75LBC174ADWR
DW
20
SITE 60
346.0
346.0
41.0
Pack Materials-Page 2
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