FREESCALE MC68VZ328AG

深圳市南天星电子科技有限公司
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MC68VZ328P/D
Rev. 1, 10/2001
MC68VZ328
MC68VZ328 (DragonBall™ VZ)
Integrated Portable System Processor
Product Brief
The MC68VZ328 (DragonBall VZ) microprocessor, the third generation of the DragonBall™ family of
products, is designed to save time, power, and cost in the design and operation of new products.
DragonBall VZ requires less board space and allows for reduced pin count and fewer programming steps
in designing your product. The major differences between previous versions of DragonBall processors and
the new VZ product are system-speed improvement and SDRAM support.
All these features combine to make the MC68VZ328 the microprocessor of choice among many system
designers. Its functionality and glue logic are all optimally connected, timed with the same clock, fully
tested, and uniformly documented. Also, only the essential signals are brought out to the pins. The
MC68VZ328’s primary package consists of TQFP and MBGA, designed to occupy the smallest possible
footprint on your board.
Although the DragonBall VZ is the integrated processor of choice for some of the most popular PDA
designs, it can be used in a wide variety of applications including exercise monitors, navigation systems,
and smart phones. Figure 1 on page 2 shows a simplified block diagram of the MC68VZ328.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Motorola, Inc., 2001. All rights reserved.
PORT F
PF2/CLKO
SYSTEM
INTEGRATION
MODULE
BUSW/DTACK/PG0
LWE/LB
UWE/UB
OE
PG1/A0
PK[2:1]/UDS,LDS,RW
PORT B
PORT M
PB7/PWMO1
PB6/TOUT/TIN
/PB1CSB1/SDWE
PB2/CSC0/RAS0
PB3/CSC1/RAS1
PB4/CSD0/CAS0
PB5/CSD1/CAS1
PM0/SDCLK
PM1/SDCE
PM2/DQMH
PM3/DQML
PM4/SDA10
PM5/DMOE
VOLTAGE
REGULATOR
CSA0
PF7/CSA1
PB0/CSB0
VDD
LVDD
GND
PORT B
MEMORY
CONTROLLER
CHIP SELECT
MA[15:0]/A[16:1]
MASTER
LCD
CONTROLLER
SPI
M/S
SPI
WITH
FIFO
UART
UART
WITH
IRDA1.0
INTERRUPT
CONTROLLER
PROCESSOR
CONTROL,
EMULATION
AND
BOOTSTRAP
PORT E
PORT J & K
PORT E
PE4/RXD1
PE5TXD1
PE6/RTS1
PE7/CTS1
PORTS D & F
PORT G
8/16-BIT
PWM
68000 INTERNAL BUS
PORTS C, F & K
RESET
16-BIT
TIMER
CLOCK
SYNTHESIZER
AND
POWER
CONTROL
REAL-TIME
CLOCK
EMUIRQ/PG2
PG3/HIZ/P/D
EMUCS/PG4
EMUBRK/PG5
16-BIT
TIMER
PJ0/MISO
PJ1/MOSI
PJ2/SPICLK1
PJ3/SS
PK0/SPIRDY/PWMO2
PJ4/RXD2
PJ5TXD2
PJ6/RTS2
PJ7/CTS2
EXTAL
XTAL
PD0/INT0
PD1/INT1
PD2/INT2
PD3/INT3
PD4/IRQ1
PD5/IRQ2
PD6/IRQ3
PD7/IRQ6
PF1/IRQ5
FLX68000
STATIC
CORE
PC[3:0]/LD[3:0]
PK[7:4]/LD[7:4]
PC4/LFLM
PC5/LLP
PC6/LCLK
PC7/LACD
PF0/LCONTRAST
A[23:20]/PF[6:3]
8-/16-BIT
68000 BUS
INTERFACE
PORT F
D[7:0]/PA[7:0]
PORT A
D[15:8]
PE0/SPITXD
PE1/SPIRXD
PE2/SPICLK2
PE3/DWE/UCLK
A[19:17]
Figure 1. MC68VZ328 Simplified Block Diagram
2
MC68VZ328 Product Brief
1
Features
The features of the DragonBall VZ include the following:
•
Static FLX68000 CPU—identical to MC68EC000 microprocessor
— Full compatibility with MC68000 and MC68EC000
— 32-bit internal address bus
— Static design that allows processor clock to be stopped to provide power savings
— 5.4 MIPS performance at 33 MHz processor clock
— External M68000 bus interface with selectable bus sizing for 8-bit and 16-bit data ports
•
System Integration Module (SIM) incorporating many functions typically related to external array
logic, reducing parts counts in design, with functions that include the following:
— System configuration and programmable address mapping
— Glueless interface to SRAM, DRAM, SDRAM, EPROM, and FLASH memory
— Eight programmable chip selects with wait state generation logic
— Four programmable interrupt I/Os, with keyboard interrupt capability
— Five general-purpose, programmable edge/level/polarity interrupt IRQs
— Other programmable I/O, multiplexed with peripheral functions of up to 47 parallel I/O lines
— Programmable interrupt vector response for on-chip peripheral modules
— Low-power mode control
•
Synchronous DRAM controller
— Support for CAS-before-RAS refresh cycles and self-refresh mode DRAM
— Support for 8-bit / 16-bit port DRAM
— EDO or Automatic Fast Page Mode for LCDC access
— Programmable refresh rate
— Support for up to two banks of DRAM / EDO DRAM
— Programmable column address size
•
76 general-purpose ports
•
Two UART ports
•
Two Serial Peripheral Interface (SPI) ports
•
Two 16-bit general-purpose counters/timers
— Automatic interrupt generation
— 30 ns resolution at 33 MHz system clock
— Timer input/output pin
•
Real-time clock / sampling timer
— Separate power supply for the RTC
— One programmable alarm
— Capability of counting up to 512 days
3
— Sampling timer with selectable frequency (4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz, 128 Hz, 256 Hz,
512 Hz)
— Interrupt generation for digitizer sampling or keyboard debouncing
•
LCD controller
— Software-programmable screen size (up to 640 x 480) to support single (non-split)
monochrome panels
— Capability of directly driving popular LCD drivers/modules from Motorola, Sharp, Hitachi,
Toshiba, and numerous other manufacturers
— Support for up to 16 gray levels out of 16 palettes
— Utilization of system memory as display memory
— LCD contrast control using 8-bit PWM
•
Two Pulse Width Modulation (PWM) modules
— Audio-effects support
— 16- and 8-bit resolution
— 5-byte FIFO that provides more flexibility on performance
— Sound and melody generation
•
Built-in emulation function
— Dedicated memory space for emulator debug monitor with chip select
— Dedicated interrupt (interrupt level 7) for ICE
— One address-signal comparator and one control-signal comparator, with masking to support
single or multiple hardware execution
— Breakpoint
— One breakpoint instruction insertion unit
•
Boot Strap mode function
— Allows user to initialize system and download program/data to system memory through UART
— Accepts execution command to run program stored in system memory
— Provides an 8-byte-long instruction buffer for 68000 instruction storage and execution
•
Power management
— Fully static HCMOS technology
— Programmable clock synthesizer using 32.768 kHz / 38.4 kHz crystal for full frequency control
— Low-power stop capabilities
— Modules that can be individually shut down
— Operation from DC to 33 MHz (processor clock)
— Operating voltage of (3.0 ± 10%) V
— Compact 144-lead Thin Quad Flat Pack (TQFP) and MAP BGA
4
MC68VZ328 Product Brief
2
DragonBall Series
The DragonBall VZ marks the third generation in the DragonBall series. Table 1 compares the new
processor with previous versions.
Table 1. DragonBall Series Comparison
Feature
DragonBall
DragonBall EZ
DragonBall VZ
CPU
68EC000
68EC000
Synthesizable 68000
Chip Selects
16
8
8
LCD Controller
4 gray levels
16 gray levels
16 gray levels
LCD Resolution
Up to 1024 * 512
Up to 640 * 512
Up to 640 * 480
Timer
2 * 16-bit
1 * 16-bit
2 * 16-bit
Master and Slave
Master
Master and Config.
Master/Slave
16-bit
8-bit with FIFO
16-bit, 8-bit with FIFO
UART 1
UART 1
UART 1
UART 2
RTC
Yes
512 day count
512 day count
PCMCIA 1.0
Yes
No
No
DRAM Controller
No
EDO/Fast Page DRAM
EDO/Fast Page DRAM
GPIO
Up to 78
Up to 54
Up to 76
Boot Strap Mode
No
Yes
Yes
Speed
16 MHz
16/20 MHZ
33 MHz
Voltage
3.3 V ± 10%
3.3 V ± 10%
3.0 V ± 10%
Package
144 TQFP
100 TQFP,144 MAP BGA
144 TQFP,144 MAP BGA
SPI
PWM
UART
5
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© Motorola, Inc. 2001.
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MC68VZ328P/D