SN74AUC1G08 SINGLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES374O – SEPTEMBER 2001 – REVISED APRIL 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 2.4 ns at 1.8 V • DBV PACKAGE (TOP VIEW) A 1 B 2 GND 3 5 4 Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) A 1 B 2 GND 3 VCC DRL PACKAGE (TOP VIEW) VCC 5 Y 4 A 1 B 2 GND 3 5 VCC 4 Y Y DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) 3 4 6 GND 2 V E R 4 GNDP 3 B 2 A 1 5 A 1 B WVCC I5E NC Y Y VCC See mechanical drawings for dimensions. NC – No internal connection DESCRIPTION/ORDERING INFORMATION This single 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G08 performs the Boolean function Y + A • B or Y + A ) B in positive logic. ORDERING INFORMATION PACKAGE (1) (2) TA –40°C to 85°C (1) (2) (3) ORDERABLE PART NUMBER TOP-SIDE MARKING (3) NanoFree™ – WCSP (DSBGA) Reel of 3000 0.23-mm Large Bump – YZP (Pb-free) SN74AUC1G08YZPR _ _ _UE_ SON – DRY Reel of 5000 SN74AUC1G08DRYR PREVIEW SOT (SOT-23) – DBV Reel of 3000 SN74AUC1G08DBVR U08_ SOT (SC-70) – DCK Reel of 3000 SN74AUC1G08DCKR UE_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2007, Texas Instruments Incorporated SN74AUC1G08 SINGLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES374O – SEPTEMBER 2001 – REVISED APRIL 2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS A B OUTPUT Y H H H L X L X L L LOGIC DIAGRAM (POSITIVE LOGIC) 1 A 4 2 B Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 3.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 3.6 V VO Output voltage range (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) DBV package 206 DCK package 252 DRL package 142 DRY package 234 YZP package Tstg (1) (2) (3) 2 UNIT Storage temperature range °C/W 132 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74AUC1G08 SINGLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES374O – SEPTEMBER 2001 – REVISED APRIL 2007 Recommended Operating Conditions VCC (1) Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH VCC = 0.8 V to 1.95 V MAX 0.8 2.7 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0 TA Operating free-air temperature (1) 3.6 V VCC V VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V Input transition rise or fall rate V 0.7 0 ∆t/∆v V 1.7 VCC = 0.8 V to 1.95 V Low-level output current UNIT 0.65 × VCC VCC = 2.3 V to 2.7 V High-level output current IOL MIN mA mA 9 VCC = 0.8 V to 1.95 V 20 VCC = 2.3 V to 2.7 V 10 –40 ns/V °C 85 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC MIN TYP (1) MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 UNIT VCC – 0.1 0.55 V 0.2 0.25 V VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA ICC VI = VCC or GND, 0.8 V to 2.7 V 10 µA CI VI = VCC or GND II (1) A or B input IO = 0 2.5 V 3 pF All typical values are at TA = 25°C. Submit Documentation Feedback 3 SN74AUC1G08 SINGLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES374O – SEPTEMBER 2001 – REVISED APRIL 2007 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX A or B Y 4.7 0.9 3.3 0.6 2.3 0.4 1.1 1.7 0.2 1.6 tpd UNIT ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN TYP MAX 0.7 1.3 2.4 UNIT MIN MAX 0.5 2 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP f = 10 MHz 15 15 15 15 19 Submit Documentation Feedback UNIT pF SN74AUC1G08 SINGLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES374O – SEPTEMBER 2001 – REVISED APRIL 2007 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 VCC/2 Data Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL VCC/2 VCC/2 VOL tPZL tPLZ VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC Output Control VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 6-Jan-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AUC1G08DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G08YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74AUC1G08DBVR SOT-23 DBV 5 3000 180.0 9.2 SN74AUC1G08DCKR SC70 DCK 5 3000 180.0 SN74AUC1G08DRLR SOT DRL 5 4000 180.0 SN74AUC1G08YZPR DSBGA YZP 5 3000 178.0 3.23 3.17 1.37 4.0 8.0 Q3 9.2 2.24 2.34 1.22 4.0 8.0 Q3 9.2 1.78 1.78 0.69 4.0 8.0 Q3 9.2 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC1G08DBVR SN74AUC1G08DCKR SOT-23 DBV 5 3000 205.0 200.0 33.0 SC70 DCK 5 3000 205.0 200.0 33.0 SN74AUC1G08DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74AUC1G08YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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