Data Sheet 26185.116B A6833 DABiC-5 32-Bit Serial Input Latched Sink Drivers Designed to reduce logic supply current, chip size, and system cost, the A6833 integrated circuits offer high-speed operation for thermal printers. These devices can also be used to drive multiplexed LED displays or incandescent lamps within their 125 mA peak output current rating. The combination of bipolar and MOS technologies gives the A6833 smart power ICs an interface flexibility beyond the reach of standard buffers and power driver circuits. 40 41 42 43 1 44 2 3 4 5 6 A6833SEP 44-pin PLCC 17 29 28 30 27 31 16 26 32 15 25 33 14 24 34 13 23 35 12 22 36 11 21 37 10 20 38 9 19 39 8 18 7 These 32-bit drivers have bipolar open-collector npn Darlington outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS shift register, and CMOS control circuitry. The high-speed CMOS shift registers and latches allow operation with most microprocessor-based systems. Use of these drivers with TTL may require input pull-up resistors to ensure an input logic high. CMOS serial data outputs permit cascading for applications requiring additional drive lines. The A6833 is supplied in a 44-lead plastic chip carrier (quad pack), intended for surface mounting on solder lands with 0.050 in. (1.27 mm) centers. These devices are lead (Pb) free, with 100% matte tin plated leadframes. FEATURES ABSOLUTE MAXIMUM RATINGS Output Voltage, VOUT .........................................30 V Logic Supply Voltage, VDD...................................7 V Input Voltage Range, VIN ..............–0.3 V to VDD +0.3 V Continuous Output Current (each output), IOUT ... 125 mA Package Power Dissipation, PD A6833SA................................................ 3.5 W* A6833SEP .............................................. 2.5 W* Operating Temperature Range Ambient Temperature, TA ............–20°C to +85°C Storage Temperature, TS ..........–55°C to +150°C *Derate linearly to 0 W at +150ºC. Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. 3.3 V to 5 V logic supply range To 10 MHz data input rate 30 V minimum output breakdown Darlington current-sink outputs Low-power CMOS logic and latches Schmitt trigger inputs for improved noise immunity APPLICATIONS Thermal printheads Multiplexed LED displays Incandescent lamps Use the following complete part numbers when ordering: Part Number Pins Package A6833SEP-T 44 PLCC Data Sheet 26185.116B A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Functional Block Diagram V DD C LOC K S E R IAL DATA IN S E R IAL DATA OUT 32-B IT S HIF T R E G IS T E R S T R OB E LAT C HE S OUT P UT E NAB LE LOG IC G R OUND MOS B IP OLAR S UB OUT 2 OUT3 OUT1 OUT 30 OUT31 OUT32 P OWE R G R OUND Typical Input Circuit Typical Output Driver OUT VDD IN SUB www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Data Sheet 26185.116B A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Vdd = 3.3 V Characteristic Min. Typ. Typ. Max. Units VOUT = 30 V – – 10 – – 10 μA IOUT = 50 mA – – 0.7 – – 0.7 V IOUT = 100 mA – – 1.0 – – 1.0 V 2.2 – – 3.3 – – V – – 1.1 – – 1.7 V – < 0.01 1.0 – < 0.01 1.0 μA μA Symbol Output Leakage Current ICEX Collector–Emitter Saturation Voltage VCE(SAT) Test Conditions VIN(1) Input Voltage VIN(0) Input Current Serial Data Output Voltage Vdd = 5 V IIN(1) VIN = VDD IIN(0) VIN = 0 V Max. Min. – < –0.01 –1.0 – < –0.01 –1.0 VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V Maximum Clock Frequency2 10 – – 10 – – MHz IDD(1) fc One output on, IOUT = 100 mA – – 2.0 – – 2.0 mA IDD(0) All outputs off – – 100 – – 100 μA tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Fall Time tf VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 500 – – 500 ns Output Rise Time tr VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 500 – – 500 ns IOUT = ±200 μA – 50 – – 50 – ns Logic Supply Current Output Enable-to-Output Delay Strobe-to-Output Delay Clock-to-Serial Data Out Delay 1Positive tp(CH-SQX) (negative) current is defined as conventional current going into (coming out of) the specified device pin. at a clock frequency greater than the specified minimum value is possible but not warranteed. 2Operation Truth Table Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Data Strobe Output Input Latch Contents I1 I2 I3 ... IN-1 IN Output Enable Input Output Contents I1 I2 I3 ... IN-1 I N H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN H P1 P2 P3 ... PN-1 PN X X L H H H ... H X X ... P1 P2 P3 ... L = Low Logic Level H = High Logic Level X = Irrelevant X PN-1 PN X X ... X H P = Present State R = Previous State www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Data Sheet 26185.116B A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) C 50% C LOC K A S E R IAL DAT A IN B DAT A 50% t p(C H-S QX) S E R IAL DAT A OUT DAT A 50% D 50% S T R OB E OUT P UT E NAB LE E HIG H = ALL OUT P UT S E NAB LE D t p(S TH-QH) t p(S T H-QL) 90% DAT A OUT N 10% LOW = ALL OUT P UT S B LANK E D (DIS AB LE D) OUT P UT E NAB LE 50% t en(B Q) tr tf t dis (B Q) OUT N 10% Key Description A Data Active Time Before Clock Pulse (Data Set-Up Time) B DAT A 90% 50% Symbol tsu(D) Time (ns) Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50 NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The 25 latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry. When the OUTPUT ENABLE input is low, the output sink drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input high, the outputs are controlled by the state of their respective latches. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Data Sheet 26185.116B A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers OUT32 NC 40 OUTPUT ENABLE 41 SERIAL DATA OUT 43 OE 42 LOGIC SUPPLY CLOCK CLK 44 SERIAL DATA IN VDD 1 POWER GROUND 2 STROBE 3 NC 5 ST 4 OUT1 6 A6833SEP OUT 2 7 39 OUT31 OUT 3 8 38 OUT30 37 OUT29 36 OUT28 OUT 6 11 OUT 7 12 LATCHES REGISTER REGISTER 9 10 LATCHES OUT 4 OUT 5 35 OUT27 34 OUT26 OUT 8 13 33 OUT25 OUT 9 14 32 OUT24 OUT10 15 31 OUT23 OUT11 16 30 OUT22 OUT 12 17 29 OUT21 NC 28 OUT20 27 OUT19 26 OUT18 25 OUT17 24 LOGIC GROUND 23 OUT16 22 OUT15 21 OUT14 20 OUT13 19 NC 18 SUB www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 Data Sheet 26185.116B A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers A6833SEP Dimensions in Inches (controlling dimensions) 18 28 29 17 0.032 0.026 0.319 0.291 0.695 0.685 0.021 0.013 0.656 0.650 0.319 0.291 0.050 INDEX AREA BSC 39 7 40 0.020 44 1 2 6 0.656 0.650 MIN 0.695 0.685 0.180 0.165 Dwg. MA-005-44A in Dimensions in Millimeters (for reference only) 28 18 29 17 0.812 0.661 8.10 7.39 17.65 17.40 0.533 0.331 16.662 16.510 8.10 7.39 INDEX AREA 1.27 BSC 39 7 40 0.51 MIN 4.57 4.20 44 1 2 6 16.662 16.510 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6 Data Sheet 26185.116B A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2003, 2004, 2005 AllegroMicrosystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7