5800 AND 5801 BiMOS II LATCHED DRIVERS Data Sheet 26180.10B 5800 AND 5801 BiMOS II LATCHED DRIVERS UCN5800L 1 14 UCN5800A 1 14 OUTPUT ENABLE STROBE 2 VDD 13 SUPPLY IN 1 3 12 OUT 1 IN 2 4 11 OUT 2 IN 3 5 10 OUT 3 IN 4 6 9 OUT 4 GROUND 7 8 COMMON LATCHES CLEAR Dwg. PP-014A Note the UCN5800A (DIP) and the UCN5800L (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at +25 °C Free-Air Temperature Output Voltage, VCE . . . . . . . . . . . . . . 50 V Supply Voltage, VDD . . . . . . . . . . . . . . 15 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Continuous Collector Current, lC . . . . . . . . . . . . . . . . . . . . . . 500 mA Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . . -55°C to +150°C Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (‘D’ type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar npn Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The UCN5800A and UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight latched drivers. The UCN5800A/L and UCN5801A/EP/LW supersede the original BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These second-generation devices are capable of much higher data input rates and will typically operate at better than 5 MHz with a 5 V logic supply. Circuit operation at 12 V affords substantial improvement over the 5 MHz figure. The CMOS inputs are compatible with standard CMOS and NMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small dc motors, etc. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 500 mA and will withstand at least 50 V in the OFF state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. The UCN5800A is furnished in a standard 14-pin DIP; the UCN5800L and UCN5801LW in surface-mountable SOICs; the UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the UCN5801EP in a 28-lead PLCC. FEATURES ■ Output Transient Protection ■ To 4.4 MHz Data Input Rate ■ Internal Pull-Down Resistors ■ High-Voltage, ■ Low-Power CMOS Latches High-Current Outputs ■ Automotive Capable ■ CMOS, NMOS, TTL Compatible Inputs Always order by complete part number, e.g., UCN5801EP . 5800 AND 5801 BiMOS II LATCHED DRIVERS FUNCTIONAL BLOCK DIAGRAM SUPPLY COMMON VDD IN N OUT N STROBE CLEAR GROUND OUTPUT ENABLE COMMON MOS CONTROL TYPICAL MOS LATCH TYPICAL BIPOLAR DRIVE Dwg. FP-016-1 TYPICAL INPUT CIRCUIT IN Dwg. EP-010-4A 22-PIN DIP, R θJA = 50°C/W ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS VDD 2.5 28-LEAD PLCC, R θJA = 55°C/W 14-PIN DIP, R θJA = 60°C/W 2.0 24-LEAD SOIC, R θJA = 68°C/W 1.5 1.0 0.5 0 14-LEAD SOIC, R θJA = 95°C/W 25 50 75 100 125 150 AMBIENT TEMPERATURE IN °C Dwg. GP-023-1 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1985, 1997, Allegro MicroSystems, Inc. 5800 AND 5801 BiMOS II LATCHED DRIVERS ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted). Characteristic Output Leakage Current Collector-Emitter Saturation Voltage Input Voltage Symbol Typ. VCE = 50 V, TA = +25°C — — 50 µA VCE = 50 V, TA = +70°C — — 100 µA IC = 100 mA — 0.9 1.1 V IC = 200 mA — 1.1 1.3 V IC = 350 mA, VDD = 7.0 V — 1.3 1.6 V — — 1.0 V VDD = 12 V 10.5 — — V VDD = 10 V 8.5 — — V VDD = 5.0 V (See Note) 3.5 — — V VDD = 12 V 50 200 — kΩ VDD = 10 V 50 300 — kΩ VDD = 5.0 V 50 600 — kΩ VDD = 12 V, Outputs Open — 1.0 2.0 mA VDD = 10 V, Outputs Open — 0.9 1.7 mA VDD = 5.0 V, Outputs Open — 0.7 1.0 mA IDD(OFF) VDD = 12 V, Outputs Open, Inputs = 0 V — — 200 µA (Total) VDD = 5.0 V, Outputs Open, Inputs = 0 V — 50 100 µA VR = 50 V, TA = +25°C — — 50 µA VR = 50 V, TA = +70°C — — 100 µA IF = 350 mA — 1.7 2.0 V VCE(SAT) VIN(0) VIN(1) Input Resistance Supply Current Limits Max. Min. I CEX Test Conditions rIN I DD(ON) (Each Stage) Clamp Diode Leakage Current IR Clamp Diode Forward Voltage VF Units 27 SUPPLY 26 V DD NC CLEAR 1 28 OUTPUT ENABLE C OE NC 3 ST 2 4 25 OUT1 IN 2 6 24 OUT 2 IN 3 7 23 OUT 3 22 OUT4 21 OUT 5 IN 6 10 20 OUT 6 IN 7 11 19 OUT7 OUT8 18 17 NC 16 CLAMP DIODE COMMON K 15 GROUND 9 13 NC 8 IN 5 14 NC IN 4 LATCHES 5 12 (additional pinout diagrams are on next page) IN1 IN 8 UCN5801EP NC STROBE NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic “1”. Dwg. PP-037 5800 AND 5801 BiMOS II LATCHED DRIVERS UCN5801A CLEAR F 1 22 OUTPUT ENABLE STROBE 2 VDD 21 SUPPLY IN 1 3 20 OUT 1 IN 2 4 19 OUT 2 IN 3 5 18 OUT 3 IN 4 6 17 OUT 4 IN 5 7 16 OUT 5 IN 6 8 15 OUT 6 IN 7 9 14 OUT 7 IN 8 10 13 OUT 8 GROUND 11 12 COMMON LATCHES CLEAR STROBE A C OUTPUT ENABLE B B C C A G B G INN E D E OUTN Dwg. No. A-10,895A TIMING CONDITIONS (Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time) .......................................................... 50 ns B. Minimum Data Active Time After Strobe Disabled (Data Hold Time) .............................................................. 50 ns C. Minimum Strobe Pulse Width ..................................................125 ns Dwg. PP-015 D. Typical Time Between Strobe Activation and Output On to Off Transition ............................................500 ns E. Minimum Time Between Strobe Activation and Output Off to On Transition ............................................500 ns UCN5801LW F. Minimum Clear Pulse Width ....................................................300 ns 24 OUTPUT ENABLE 23 SUPPLY 3 22 OUT 1 IN 2 4 21 OUT 2 IN 3 5 20 OUT 3 IN 4 6 19 OUT 4 IN5 7 18 OUT 5 IN 6 8 17 OUT 6 IN 7 9 16 OUT 7 IN 8 10 15 OUT 8 GROUND 11 14 COMMON 13 NO CONNECTION 1 STROBE 2 IN1 NO CONNECTION 12 VDD LATCHES CLEAR NC NC Dwg. PP-015-1 G. Minimum Data Pulse Width .....................................................225 ns Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. TRUTH TABLE OUT N OUTPUT IN N STROBE CLEAR ENABLE t-1 t 0 1 X X X X 1 1 X X 0 0 0 0 1 X 0 0 0 0 X 1 0 0 X X X X ON OFF OFF ON OFF OFF ON OFF X = irrelevant. t-1 = previous output state. t = present output state. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5800 AND 5801 BiMOS II LATCHED DRIVERS TYPICAL APPLICATION UNIPOLAR STEPPER-MOTOR DRIVE +30 V OUTPUT ENABLE (ACTIVE LOW) CLEAR IN 1 µρ IN 2 IN 3 IN 4 1 14 2 VDD 13 3 12 4 5 LATCHES STROBE VDD OUT 1 OUT 2 11 OUT 3 10 OUT 4 6 9 7 8 UCN-5800A +30 V Dwg. No. B-1537 UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE STROBE STROBE IN 1 IN 1 IN 2 IN 2 IN 3 IN 3 IN 4 IN 4 OUT 1 OUT 1 OUT 2 OUT 2 OUT 3 OUT 3 OUT 4 OUT 4 Dwg. GP-060 Dwg. GP-060-1 5800 AND 5801 BiMOS II LATCHED DRIVERS UCN5800A Dimensions in Inches (controlling dimensions) 0.014 0.008 14 8 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 0.775 0.735 7 BSC 0.005 MIN 0.210 MAX 0.015 0.150 0.115 MIN 0.022 0.014 Dwg. MA-001-14A in Dimensions in Millimeters (for reference only) 0.355 0.204 8 14 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 19.68 18.67 BSC 7 0.13 MIN 5.33 MAX 3.81 2.93 0.39 MIN 0.558 0.356 Dwg. MA-001-14A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5800 AND 5801 BiMOS II LATCHED DRIVERS UCN5800L Dimensions in Inches (for reference only) 14 8 0.0098 0.0075 0.1574 0.1497 0.020 0.013 0.2440 0.2284 1 2 3 0.050 0° TO 8° BSC 0.3444 0.3367 0.050 0.016 0.0688 0.0532 0.0040 MIN. Dwg. MA-007-14 in Dimensions in Millimeters (controlling dimensions) 14 8 0.25 0.19 4.00 3.80 0.51 0.33 6.20 5.80 1 2 1.27 3 8.75 8.55 BSC 1.27 0.40 0° TO 8° 1.75 1.35 0.10 MIN. NOTES: 1. 2. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Dwg. MA-007-14A mm 5800 AND 5801 BiMOS II LATCHED DRIVERS UCN5801A Dimensions in Inches (controlling dimensions) 22 0.015 0.008 12 0.500 MAX 0.380 0.330 0.400 BSC 1 2 0.070 0.030 3 11 0.100 1.120 1.050 BSC 0.005 MIN 0.210 MAX 0.015 0.160 0.115 MIN 0.022 0.014 Dwg. MA-002-22 in Dimensions in Millimeters (for reference only) 22 0.381 0.204 12 12.70 MAX 9.65 8.39 10.16 BSC 1 2 0.070 0.030 3 2.54 28.44 26.67 BSC 11 0.13 MIN 5.33 MAX 0.39 4.06 2.93 MIN 0.558 0.356 Dwg. MA-002-22 mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5800 AND 5801 BiMOS II LATCHED DRIVERS UCN5801EP Dimensions in Inches (controlling dimensions) 18 0.013 0.021 12 19 0.219 0.191 11 0.026 0.032 0.456 0.450 0.495 0.485 0.050 INDEX AREA BSC 0.219 0.191 25 5 26 0.020 28 1 4 0.456 0.450 0.495 0.485 MIN 0.165 0.180 Dwg. MA-005-28A in Dimensions in Millimeters (for reference only) 18 0.331 0.533 12 19 5.56 4.85 11 0.812 0.661 11.58 11.43 12.57 12.32 1.27 INDEX AREA BSC 5.56 4.85 25 5 26 0.51 MIN 4.57 4.20 28 1 4 11.582 11.430 12.57 12.32 Dwg. MA-005-28A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 5800 AND 5801 BiMOS II LATCHED DRIVERS UCN5801LW Dimensions in Inches (for reference only) 24 13 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0° TO 8° BSC 0.6141 0.5985 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-24A in Dimensions in Millimeters (controlling dimensions) 24 13 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 15.60 15.20 BSC 0° TO 8° 2.65 2.35 0.10 MIN. NOTES: 1. 2. Dwg. MA-008-24A mm Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5800 AND 5801 BiMOS II LATCHED DRIVERS This page intentionally left blank 5800 AND 5801 BiMOS II LATCHED DRIVERS BiMOS II (Series 5800) & DABiC IV (Series 6800) INTELLIGENT POWER INTERFACE DRIVERS SELECTION GUIDE Function Output Ratings * Part Number † SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit -120 mA 350 mA 350 mA 350 mA 350 mA 50 V‡ 50 V 80 V 50 V‡ 80 V‡ 5895 5821 5822 5841 5842 1.6 A 50 V 5829 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10 12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) -25 mA 100 mA 100 mA 60 V 30 V 40 V 5818-F and 6818 5833 5832 9-Bit PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit 8-Bit -25 mA 350 mA 60 V 50 V‡ 5815 5801 SPECIAL-PURPOSE FUNCTIONS Unipolar Stepper Motor Translator/Driver Addressable 28-Line Decoder/Driver 1.25 A 450 mA 50 V‡ 30 V * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection. 5804 6817 Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000