AS7C33256NTD32A AS7C33256NTD36A November 2004 ® 3.3V 256K×32/36 Pipelined burst Synchronous SRAM with NTDTM Features • Organization: 262,144 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Common data inputs and data outputs • Asynchronous output enable control • Available in 100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3 core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Logic Block Diagram 18 A[17:0] Q D Address register Burst logic 18 CLK D Q Write delay addr. registers CE0 CE1 CE2 18 CLK R/W BWa BWb BWc BWd ADV / LD Control logic DQ [a:d] Write Buffer LBO ZZ CLK CLK 36/32 D Data Q Input Register 36/32 36/32 CLK 256K x 32/36 SRAM Array 36/32 36/32 CLK CEN CLK Output Register OE 36/32 DQ[a:d] OE Selection Guide -166 -133 Units 6 7.5 ns Maximum clock frequency 166 133 MHz Maximum clock access time 3.5 4 ns Maximum operating current 475 400 mA Maximum standby current 130 100 mA Maximum CMOS standby current (DC) 30 30 mA Minimum cycle time 11/30/04, v. 2.1 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. 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AS7C33256NTD32A AS7C33256NTD36A ® 8 Mb Synchronous SRAM products list1,2 Org 512KX18 256KX32 Part Number AS7C33512PFS18A AS7C33256PFS32A Mode PL-SCD PL-SCD Speed 166/133 MHz 166/133 MHz 256KX36 512KX18 256KX32 256KX36 512KX18 256KX32 256KX36 512KX18 256KX32 256KX36 AS7C33256PFS36A AS7C33512PFD18A AS7C33256PFD32A AS7C33256PFD36A AS7C33512FT18A AS7C33256FT32A AS7C33256FT36A AS7C33512NTD18A AS7C33256NTD32A AS7C33256NTD36A PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 512KX18 256KX32 256KX36 AS7C33512NTF18A AS7C33256NTF32A AS7C33256NTF36A NTD-PL NTD-FT NTD-FT NTD-FT 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 11/30/04, v. 2.1 Alliance Semiconductor P. 2 of 19 AS7C33256NTD32A AS7C33256NTD36A ® 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A A A TQFP 14x20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 Vss NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQP/NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPc/NC DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 NC VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd/NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD NC Pin arrangement for TQFP (top view) Note: Pins 1, 30, 51 , and 80 are NC for ×32 11/30/04, v. 2.1 Alliance Semiconductor P. 3 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Functional description The AS7C33256NTD32/36A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 32 or 36 bits and incorporates a LATE LATE Write. This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD™, write and read operations can be used in any order without producing dead bus cycles. Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write operations to be completed. Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C33256NTD36A and AS7C33256NTD32A operate with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a separate power supply (VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package Capacitance Parameter Symbol CIN* CI/O* Input capacitance I/O capacitance * Test conditions Min Max Unit Vin = 0V - 5 pF Vin = Vout = 0V - 7 pF Units °C/W °C/W °C/W Guaranteed not tested TQFP thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1–layer Symbol θJA 4–layer θJA Typical 40 22 θJC 8 1 This parameter is sampled 11/30/04, v. 2.1 Alliance Semiconductor P. 4 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, CE2 I SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. ADV/LD I SYNC Advance or Load. When sampled high, the internal burst address counter will increment in the order defined by the LBO input value. (refer to table on page 2) When low, a new address is loaded. R/W I SYNC A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. BW[a,b,c,d] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO I STATIC Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connect. Note that pin 84 will be used for future address expansion to 16Mb density. Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 11/30/04, v. 2.1 Alliance Semiconductor P. 5 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Burst Order Interleaved Burst Order (LBO=1) Linear Burst Order (LBO=0) A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 Starting Address 00 01 10 11 Starting Address 00 01 10 11 First increment 01 00 11 10 First increment 01 10 11 00 Second increment 10 11 00 01 Second increment 10 11 00 01 Third increment 11 10 01 00 Third increment 11 00 01 10 Synchronous truth table[5,6,7,8,9] CE0 CE1 CE2 ADV/LD R/W BWn OE CEN Address source CLK Operation DQ H X X L X X X L NA L to H DESELECT Cycle High-Z X X H L X X X L NA L to H DESELECT Cycle High-Z X L X L X X X L NA L to H DESELECT Cycle High-Z X X X H X X X L NA L to H CONTINUE DESELECT Cycle High-Z L H L L H X L L READ Cycle (Begin Burst) Q X X X H X X L L READ Cycle (Continue Burst) Q L H L L H X H L X X X H X X H L L H L L L L X L X X X H X L X L L H L L L H X L X X X H X H X L X X X X X X X H External L to H Next L to H External L to H NOP/DUMMY READ (Begin Burst) High-Z Next L to H External L to H Next L to H DUMMY READ (Continue Burst) L to H 1,10 2 High-Z 1,2,10 D 3 WRITE CYCLE (Continue Burst) D 1,3,10 High-Z 2,3 WRITE ABORT (Continue Burst) High-Z 1,2,3, 10 INHIBIT CLOCK - 4 Current L to H Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or more byte write signals are LOW. Notes: 1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first. 2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements. 4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle. 5 BWa enables WRITEs to byte “a” (DQa pins/balls); BWb enables WRITEs to byte “b” (DQb pins/balls); BWc enables WRITEs to byte “c” (DQc pins/ balls); BWd enables WRITEs to byte “d” (DQd pins/balls). 6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 7 Wait states are inserted by setting CEN HIGH. 8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up. 9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE. 10 The address counter is incremented for all CONTINUE BURST cycles. 11 ZZ pin is always Low in this truth table. 11/30/04, v. 2.1 1 WRITE CYCLE (Begin Burst) External L to H NOP/WRITE ABORT (Begin Burst) Next Notes Alliance Semiconductor P. 6 of 19 AS7C33256NTD32A AS7C33256NTD36A ® State Diagram for NTD SRAM Burst Read Read Read W r it e Dsel Burst l Dse ite Wr Burst Write Dsel Write Dsel ad Re Write Read Write Burst Dsel Dse l Re ad Burst Read Burst Write Burst Absolute maximum ratings1 Parameter Symbol Min Max Unit VDD, VDDQ –0.5 +4.6 V Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V Power dissipation PD – 1.8 W DC output current IOUT – 50 mA Storage temperature (plastic) Tstg –65 +150 o +150 oC Power supply voltage relative to GND Temperature under bias (Junction) Tbias –65 C 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions at 3.3V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 3.135 3.135 0 Nominal 3.3 3.3 0 Max 3.465 3.465 0 Unit V V V Min 3.135 2.375 0 Nominal 3.3 2.5 0 Max 3.465 2.625 0 Unit V V V Recommended operating conditions at 2.5V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply 11/30/04, v. 2.1 Symbol VDD VDDQ Vss Alliance Semiconductor P. 7 of 19 AS7C33256NTD32A AS7C33256NTD36A ® DC electrical characteristics for 3.3V I/O operation Parameter Input leakage current1 Output leakage current Sym |ILI| |ILO| Input high (logic 1) voltage VIH Input low (logic 0) voltage VIL Output high voltage Output low voltage VOH VOL Conditions VDD = Max, 0V < VIN < VDD OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = –4 mA, VDDQ = 3.135V IOL = 8 mA, VDDQ = 3.465V Min -2 -2 2* 2* -0.3** -0.5** 2.4 – Max 2 2 VDD+0.3 VDDQ+0.3 0.8 0.8 – 0.4 Unit µA µA V V V V 1 LBO, and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA. DC electrical characteristics for 2.5V I/O operation Parameter Input leakage current Output leakage current Sym |ILI| |ILO| Input high (logic 1) voltage VIH Input low (logic 0) voltage VIL Output high voltage Output low voltage VOH VOL Conditions VDD = Max, 0V < VIN < VDD OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = –4 mA, VDDQ = 2.375V IOL = 8 mA, VDDQ = 2.625V *V max < VDD +1.5V for pulse width less than 0.2 IH ** VIL min = -1.5 for pulse width less than 0.2 X tCYC Min -2 -2 1.7* 1.7* -0.3** -0.3** 1.7 – Max 2 2 VDD+0.3 VDDQ+0.3 0.7 0.7 – 0.7 Unit µA µA V V V V V V -166 -133 Unit 475 400 mA 130 100 X tCYC IDD operating conditions and maximum limits Parameter Sym Operating power supply current1 ICC ISB Standby power supply current Test conditions CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL All VIN ≤ 0.2V or > VDD – 0.2V, Deselected, f = fMax, ZZ < VIL ISB1 Deselected, f = 0, ZZ < 0.2V, all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30 ISB2 Deselected, f = fMax, ZZ ≥ VDD – 0.2V, all VIN ≤ VIL or ≥ VIH 30 30 mA 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 11/30/04, v. 2.1 Alliance Semiconductor P. 8 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Timing characteristics for 3.3 V I/O operation –166 Parameter –133 Notes1 Symbol Min Max Min Max Unit Clock frequency fMax – 166 – 133 MHz Cycle time tCYC 6 – 7.5 – ns Clock access time tCD – 3.5 – 4.0 ns Output enable low to data valid tOE – 3.5 – 4.0 ns Clock high to output low Z tLZC 0 – 0 – ns 2,3,4 Data output invalid from clock high tOH 1.5 – 1.5 – ns 2 Output enable low to output low Z tLZOE 0 – 0 – ns 2,3,4 Output enable high to output High Z tHZOE – 3.5 – 4.0 ns 2,3,4 Clock high to output High Z tHZC – 3.5 – 4.0 ns 2,3,4 tOHOE 0 – 0 – ns Clock high pulse width tCH 2.4 – 2.5 – ns 5 Clock low pulse width tCL 2.3 – 2.5 – ns 5 Address and control setup to clock high tAS 1.5 – 1.5 – ns 6 Data setup to clock high tDS 1.5 – 1.5 – ns 6 Write setup to clock high tWS 1.5 – 1.5 – ns 6,7 Chip select setup to clock high tCSS 1.5 – 1.5 – ns 6,8 Address hold from clock high tAH 0.5 – 0.5 – ns 6 Data hold from clock high tDH 0.5 – 0.5 – ns 6 Write hold from clock high tWH 0.5 – 0.5 – ns 6,7 Chip select hold from clock high tCSH 0.5 – 0.5 – ns 6,8 Clock enable setup to clock high tCENS 1.5 – 1.5 – ns 6 Clock enable hold from clock high tCENH 0.5 – 0.5 – ns 6 ADV/LD setup to clock high tADVS 1.5 – 1.5 – ns 6 ADV/LD hold from clock high tADVH 0.5 – 0.5 – ns 6 Output enable high to invalid output 1 Refer to “notes” on page 16. 11/30/04, v. 2.1 Alliance Semiconductor P. 9 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Timing characteristics for 2.5 V I/O operation –166 Parameter –133 Notes1 Symbol Min Max Min Max Unit Clock frequency fMax – 166 – 133 MHz Cycle time tCYC 6 – 7.5 – ns Clock access time tCD – 3.8 – 4.2 ns Output enable low to data valid tOE – 3.5 – 4.0 ns Clock high to output low Z tLZC 0 – 0 – ns 2,3,4 Data output invalid from clock high tOH 1.5 – 1.5 – ns 2 Output enable low to output low Z tLZOE 0 – 0 – ns 2,3,4 Output enable high to output High Z tHZOE – 3.5 – 4.0 ns 2,3,4 Clock high to output High Z tHZC – 3.5 – 4.0 ns 2,3,4 tOHOE 0 – 0 – ns Clock high pulse width tCH 2.4 – 2.5 – ns 5 Clock low pulse width tCL 2.3 – 2.5 – ns 5 Address setup to clock high tAS 1.7 – 1.7 – ns 6 Data setup to clock high tDS 1.7 – 1.7 – ns 6 Write setup to clock high tWS 1.7 – 1.7 – ns 6,7 Chip select setup to clock high tCSS 1.7 – 1.7 – ns 6,8 Address hold from clock high tAH 0.7 – 0.7 – ns 6 Data hold from clock high tDH 0.7 – 0.7 – ns 6 Write hold from clock high tWH 0.7 – 0.7 – ns 6,7 Chip select hold from clock high tCSH 0.7 – 0.7 – ns 6,8 Clock enable setup to clock high tCENS 1.7 – 1.7 – ns 6 Clock enable hold from clock high tCENH 0.7 – 0.7 – ns 6 ADV/LD setup to clock high tADVS 1.7 – 1.7 – ns 6 ADV/LD hold from clock high tADVH 0.7 – 0.7 – ns 6 Output enable high to invalid output 1 Refer to “notes” on page 16. Snooze Mode Electrical Characteristics Description Current during Snooze Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current 11/30/04, v. 2.1 Conditions Symbol ZZ > VIH ISB2 tPDS tPUS tZZI tRZZI Alliance Semiconductor Min Max Units 30 mA cycle cycle cycle 2 2 2 0 P. 10 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Key to switching waveforms Rising input don’t care Falling input Undefined Timing waveform of read cycle tCH tCL tCYC CLK tCES tCEH CEN tAS Address tAH A1 A2 A3 tWS tWH R/W tWS tWH BWn tCSH CE0,CE2 CE1 tADVS tADVH ADV/LD OE tOE tLZOE Dout tHZOE Q(A1) tHLZC Q(A2Y‘10) Q(A2) Q(A2Y‘11) Q(A2Y‘01) Read Q(A1) 11/30/04, v. 2.1 DSEL Read Q(A2) Continue Read Q(A2Y‘01) Continue Read Q(A2Y‘10) Continue Read Q(A2Y‘11) Alliance Semiconductor Q(A3) Inhibit Clock Read Q(A3) Continue Read Q(A3Y‘01) P. 11 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Timing waveform of write cycle tCH tCL tCYC CLK tCES tCEH CEN tAS Address tAH A1 A2 A3 R/W BWn tCSH CE0,CE2 CE1 tADVS tADVH ADV/LD OE tDS D(A1) Din Q(n-2) D(A2Y‘01) D(A2Y‘10) D(A2Y‘11) Q(n-1) Write D(A1) 11/30/04, v. 2.1 D(A3) D(A2) tHZOE Dout tDH DSEL Write D(A2) Continue Write D(A2Y‘01) Continue Write D(A2Y‘10) Continue Write D(A2Y‘11) Alliance Semiconductor Inhibit Clock Write D(A3) Continue Write D(A3Y‘01) P. 12 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Timing waveform of read/write cycle tCH tCL tCYC CLK tCENS tCENH CEN CE1 tCSS tCSH CE0, CE2 tADVS tADVH ADV/LD tWS tWH tWS tWH tAS tAH R/W BWn ADDRESS A1 A3 A2 A4 A6 A5 A7 tCD tDS tDH D/Q D(A1) tLZC D(A2) D(A2Ý01) tOH tOE Q(A3) Q(A4) tHZC Q(A4Ý01) D(A5) Q(A6) tHZOE tLZOE OE Command Write D(A1) Write D(A2) Burst Write D(A2Ý01) Read Q(A3) Read Q(A4) Burst Read Q(A4Ý01) Write D(A5) Read Q(A6) Write D(A7) DSEL Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 11/30/04, v. 2.1 Alliance Semiconductor P. 13 of 19 AS7C33256NTD32A AS7C33256NTD36A ® NOP, stall and deselect cycles CLK CEN CE1 CE0, CE2 ADV/LD R/W BWn Address A2 A1 Q(A1) D/Q Command Read Q(A1) Burst Q(A1Ý01) STALL Q(A1Ý01) Burst Q(A1Ý10) A3 D(A2) Q(A1Ý10) DSEL Burst DSEL Write D(A2) Burst NOP D(A2Ý01) Burst D(A2Ý10) Write NOP D(A3) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low. 11/30/04, v. 2.1 Alliance Semiconductor P. 14 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Timing waveform of snooze mode CLK tPUS ZZ setup cycle ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation Cycle High-Z Dout AC test conditions • Output Load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC see Figure C. • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input and output timing reference levels: 1.5V. +3.0V 90% 10% GND 90% 10% Figure A: Input waveform 11/30/04, v. 2.1 Dout Z0=50Ω 50Ω Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O DOUT VL=1.5V 353Ω/1538Ω 30 pF* Figure B: Output load (A) Alliance Semiconductor 319Ω/1667Ω 5 pF* GND *including scope and jig capacitance Figure C: Output load(B) P. 15 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Notes 1 For test conditions, see AC Test Conditions, Figures A, B, C. 7 2 This parameter measured with output load condition in Figure C 8 3 This parameter is sampled and not 100% tested. 4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temper- 9 ature and voltage. 5 tHZCN is a‘no load’ parameter to indicate exactly when SRAM outputs have stopped driving. 6 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 11/30/04, v. 2.1 Transitions are measured ±500 mV from steady state voltage. Output loading specified with CL = 5 pF as in Figure C. tCH measured as high above VIH, and tCL measured as low below VIL This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. Alliance Semiconductor P. 16 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Package Dimensions 100-pin quad flat pack (TQFP) Hd D b TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.80 14.20 E 19.80 20.20 e e α He E 0.65 nominal A2 c Hd 15.80 16.20 He 21.80 22.20 L1 L 0.45 0.75 L L1 α A1 1.00 nominal 0° 7° Dimensions in millimeters 11/30/04, v. 2.1 Alliance Semiconductor P. 17 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Ordering information Package Width 166 MHz 133 MHz TQFP ×32 AS7C33256NTD32A-166TQC AS7C33256NTD32A-133TQC TQFP ×32 AS7C33256NTD32A-166TQI AS7C33256NTD32A-133TQI TQFP ×36 AS7C33256NTD36A-166TQC AS7C33256NTD36A-133TQC TQFP ×36 AS7C33256NTD36A-166TQI AS7C33256NTD36A-133TQI Note: Add suffix ‘N’ to he above part numbers for Lead Free Parts (Ex. AS7C33256NTD32A-166TQCN) Part numbering guide AS7C 33 256 NTD 32/36 A –XXX TQ C/I X 1 2 3 4 5 6 7 8 9 10 1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33 = 3.3V 3.Organization: 256 = 256K 4.NTDTM = No Turn-around Delay. Pipelined mode. 5.Organization: 32 = x32; 36 = x36 6.Production version: A = first production version 7.Clock speed (MHz) 8.Package type: TQ = TQFP. 9.Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C) 10. N = Lead free part 11/30/04, v. 2.1 Alliance Semiconductor P. 18 of 19 AS7C33256NTD32A AS7C33256NTD36A ® Alliance Semiconductor Corporation Copyright © Alliance Semiconductor 2575, Augustine Drive, All Rights Reserved Santa Clara, CA 95054 Part Number:AS7C33256NTD36A AS7C33256NTD32A ® Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 Document Version: v. 2.1 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. 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