INTEGRATED CIRCUITS INC.
APR6008
Voice Recording & Playback Device
8 Minute Duration
Features
• Multi-level analog storage
- High quality audio recording and playback
• Dual mode storage of analog and/or digital data
- Eliminates the need for separate digital memory
• Advanced, non-volatile Flash memory technology
- No battery backup required
• SPI interface
- Allows any commercial microcontroller to control
the device
• Programmable Sampling Clock
- Allows user to choose quality and duration levels
• Single 3V power supply
• Low power consumption
- Playback operating current: 15 mA typical
- Standby current: 1 u A maximum
- Automatic power-down
• Multiple package options available
- CSP, SOP, PDIP, Bare Die
• On-board clock prescaler
- Eliminates the need for external clock dividers
• Automatic squelch circuit
- Reduces background noise during quiet passages
General Description
The APR6008 offers non-volatile storage of voice and/or data
in advanced Multi-Level Flash memory. Up to 8 minutes of
audio recording and playback can be accommodated. A maximum of 30K bits of digital data can be stored. APR6008
devices can be cascaded for longer duration recording or
greater digital storage. Device control is accomplished
through an industry standard SPI interface that allows a
microcontroller to manage message recording and playback.
This flexible arrangement allows for the widest variety of
messaging options. The APR6008 is ideal for use in cellular
and cordless phones, telephone answering devices, personal
digital assistants, personal voice recorders, and voice pagers.
APLUS Integrated
achieves this high level of storage capabiby using a proprietary analog multi-level storage te chnol logy i mplemented in an advanced non-volatile Flash memory
process. Each memory cell can typically store 256 voltage
levels. This allows the APR6008 voice to reproduce audio
signals in their natural form, eliminating the need for encoding and compression which can introduce distortion.
lity
2002/5/10
Figure 1 APR6008 Pinout Diagrams
28 pin DIP
/C S
DI
DO
VSSD
NC
NC
NC
A NA O UTAN AO U T+
NC
/R E S E T
VSSA
AUDO UT
SQ LCAP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCLK
VCCD
EX TC LK
/IN T
SAC
VSSA
NC
/B U S Y
NC
NC
VCCA
A N A IN +
A N A IN /S Q LO U T
Page 1
APR6008
Functional Description
The EXTCLK pin allows the use of an external sampling
clock. This input can accept a wide range of frequencies
depending on the divider ratio programmed into the divider
that follows the clock. Alternatively, the programmable internal oscillator can be used to supply the sampling clock. The
Mux following both signals automatically selects the EXTCLK
signal if a clock is present, otherwise the internal oscillator
source is chosen. Detailed information on how to program the
divider and internal oscillator can be found in the explanation
of the PWRUP command, which appears in the OpCode
Command Description section. Guidance on how to choose
the appropriate sample clock frequency can be found in the
Sampling Rate & Voice Quality section.
The audio signal containing the content you wish to record
should be fed into the differential inputs ANAIN-, and
ANAIN+. After pre-amplification the signal is routed into the
anti-aliasing filter. The anti-aliasing filter automatically adapts
its response based on the sample rate being used. No external anti-aliasing filter is therefore required.
After passing through the anti-alias filter, the signal is fed into
the sample and hold circuit which works in conjunction with
the Analog Write Circuit to store each analog sample in a
flash memory cell.
Figure 2
When a read operation is desired the Analog Read Circuit
extracts the analog data from the memory array and feeds
the signal to the Internal Low Pass Filter. The low pass filter
converts the individual samples into a continuous output. The
output signal then goes to the squelch control circuit and differential output driver. The differential output driver feeds the
ANAOUT+ and ANAOUT- pins. Both differential output pins
swing around a 1.23V potential.
The squelch control circuit automatically reduces the output
signal by 6 dB during quiet passages. A copy of the squelch
control signal is present on the SQLOUT pin to facilitate
reducing gain in the external amplifier as well. For more information, refer to the Squelch section.
After passing through the squelch circuit the output signal
goes to the output amplifier. The output amplifier drives a single ended output on the AUDOUT pin. The single ended output swings around a 1.23V potential.
All SPI control and hand shaking signals are routed to the
Master Control Circuit. This circuit decodes all the SPI signals
and generates all the internal control signals. It also contains
the status register used for examining the current status of
the APR6008 .
APR6008 Block Diagram
/RESET
PreAmp
1.92 Mcell Memory Array
ANAIN+
/INT
DO
DI
/CS
Master Control Circuit
SAC
Row
Address
R ow D ecoder
ANAIN/BUSY
Low Pass
Single Analog
Memory Cell
Write Circuit
Column Decoder
Read Circuit
ANAOUT+
Column Address
Analog input/output
to Memory array
Amp
ANAOUT-
Low Pass
SCLK
Squelch
Mux
Page 2
AUDOUT
SQLCAP
Programmable Internal
Oscillator
EXTCLK
Amp
/SQLOUT
Programmable
Divider
Voice Recording & Playback Device
Revision 2.1
APR6008
Memory Organization
SPI Interface
The APR6008 memory array is organized to allow the greatest flexibility in message management and digital storage.
The smallest addressable memory unit is called a “sector”.
The APR6008 contains 640 sectors.
All memory management is handled by an external host processor. The host processor communicates with the APR6008
through a simple Serial Peripheral Interface (SPI) Port. The
SPI port can run on as little as three wires or as many as
seven depending on the amount of control necessary. This
section will describe how to manage memory using the
APR6008 SPI Port and associated OpCode commands.
This topic is broken down into the following sections:
Figure 3
Memory Map.
SAC Trigger Point
• Sending Commands to the Device
• OpCode Command Description
Sector 0
• Receiving Device Information
Sector 1
• Current Device Status (CDS)
• Reading the Silicon Identification (SID)
• Writing Digital Data
• Reading Digital Data
• Recording Audio Data
• Playing Back Audio Data
Sector 639
Can Not be Used for Digital Data
Sectors 0 through 639 can be used for analog storage. Du ring audio recording one memory cell is used per sample
clock cycle. When recording is stopped an end of data (EOD)
bit is programed into the memory. This prevents playback of
silence when partial sectors are used. Unused memory that
exists between the EOD bit and the end of the sector can not
be used.
Sectors 0 through 9 are tested and guaranteed for digital
storage. Other sectors, with the exception of sector 639, can
store data but have not been tested, and are thus not guaranteed to provide 100% good bits. This can be managed with
error correction or forward check-before-store methods.
Once a write cycle is initiated all previously written data in the
chosen sector is lost.
Mixing audio signals and digital data within the same sector is
not possible.
Note: There are a total of 15bits reserved for addressing. The
APR6008 only requires 10 bits. The additional 5 bits are used
for larger devices within the APR6008 family.
Voice Recording & Playback Device
Revision 2.1
• Handshaking Signals
Sending Commands to the Device
This section describes the process of sending OpCodes to
the APR6008 All Opcodes are sent in the same way with the
exception of the DIG_WRITE and DIG_READ commands.
The DIG_WRITE and DIG_READ commands are described
in the Writing Digital Data and Reading Digital Data sections
that follow. The minimum SPI configuration needed to send
commands uses the DI, /CS, and SCLK pins. The device will
accept inputs on the DI pin whenever the /CS pin is low.
OpCode commands are clocked in on the rising edge of the
SPI clock. Figure 4 shows the timing diagram for shifting
OpCode commands into the device. Figure 5 is a description
of the OpCode stream.
You must wait for a command to finish executing before sending a new command. This is accomplished by monitoring the /
BUSY pin. You can substitute monitoring of the busy pin by
inserting a fixed delay between commands. The required
delay is specified as T next1 ,T next2 ,T next3 or T next4 . Figure 6
shows the timing diagram for sending consecutive commands. Table 1 describes which T next specification to use.
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APR6008
Figure 4 Sending SPI Commands
~~
/CS
~~
ThiSCLK
TfCS
DI
T next1 , T next2 , T next3 , T next4
~~
SCLK
Op4
~~
TpSCLK
Op2
Op3
TloSCLK
~~
Op1
A2
T suDI
TrCS
~~
A0
A1
ThDI
Figure 5 OpCode Format
F irst b it sh ifte d in
L a st b it s h ifted in
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
{
{
O p4 O p3 O p2 O p1 O p0 A14 A13 A12 A11 A10
OpC ode C om m and
OpCode Param eter
Figure 6 Opcode Stream Timing
SCLK
/CS
DI
C urre nt C om m and
N ext C om m and
T next1 ,T next2 ,T next3 ,T next4
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Voice Recording & Playback Device
Revision 2.1
APR6008
Table 1
Sequential Command Timing
Current Command
NOP
Next command
Timing Symbol
Any Command
Tnext1 5u SEC
PWRUP
Any Command
Tnext2 5m SEC
STOP_PWDN
PWRUP
Tnext2 5m SEC
SET_REC
STOP, STOP_PWDN, SET_REC, REC,NOP
Within SAC Low Time
SID
REC
SET_PLAY
STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP
PLAY
SET_FWD
SET_FWD, FWD, STOP, STOP_PWDN
FWD
DIG_WRITE
Any Digital Command, STOP, STOP_PWDN
Tnext3
DIG_READ
Note: For partial DIG_READ Tnext2 is measured from the extra clock low that follows the
rise of /CS, not from the rise of /CS
8K sampling rate: 376m SEC
4K sampling rate: 752 m SEC
DIG_ERASE
STOP
Any Command
OpCode Command Description
Designers have access to a total of 14 OpCodes. These
OpCodes are listed in Table 2. The name of the Opcode
appears in the left hand column. The following two columns
represent the actual binary information contained in the 20 bit
data stream. Some commands have limits on which com-
Tnext4 470m SEC
mand can follow them. These limits are shown in the “Allowable Follow on Commands” column. The last column
summarizes each command.
Combinations of OpCodes can be used to accommodate
almost any memory management scheme.
Table 2 APR6008 Operational Codes
Instruction
Name
OpCode
(5 bits)
Opcode Parameters (15bits)
[Op4 - Op0]
[Address MSB - Address LSB]
[Address 14 - Address 0]
NOP
[00000]
SID
[00001]
[Don’t care]
SET_FWD
[00010]
Sector Address
[Don’t Care]
[A14 - A0]
FWD
[00011]
PWRUP
[00100]
[Don’t care]
[A14-A10]: all zeros
Allowable Follow
on Commands
All Commands
All Commands
No Operation
Causes the silicon ID to be read.
SET_FWD,
FWD, STOP,
STOP_PWDN
Starts a fast forward operation from the
sector address specified.
SET_FWD,
FWD, STOP,
STOP_PWDN
Starts a fast forward operation from the
current sector address.
All Commands
Resets the device to initial conditions.
Sets the sample frequency and divider
ratios.
Stops the current operation.
[A9-A2]: EXTCLK divider ratio
[A1-A0]: Sample Rate Frequency
STOP
[00110]
[Don’t care]
All Commands
STOP_PWDN
[00111]
[Don’t care]
PWRUP
Voice Recording & Playback Device
Revision 2.1
Summary
Stops the current operation. Causes the
device to enter power down mode.
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APR6008
Instruction
Name
SET_REC
OpCode
(5 bits)
Opcode Parameters (15bits)
[Op4 - Op0]
[Address MSB - Address LSB]
[Address 14 - Address 0]
[01000]
Sector Address
[A14 - A0]
Allowable Follow
on Commands
Summary
STOP,
STOP_PWDN,
SET_REC,
REC,NOP
Starts a record operation from the sector
address specified.
REC
[01001]
[Don’t care]
STOP,
STOP_PWDN,
SET_REC,
REC,NOP
Starts a record operation from the current
sector address.
DIG_ERASE
[01010]
Sector Address
All Commands
Erases all data contained in specified sector. You must not erase a sector before
recording voice signals into it. You must
erase a sector before storing digital data in
it.
[A14 - A0]
DIG_WRITE
[01011]
[A14 - A0][XXXX][D0 - D3004][XXXX]
All Commands
This command writes data bits D0 - D3003
starting at the specified address. All 3004
bits must be written.
DIG_READ
[01111]
Sector Address
All Commands
This command reads data bits D0 - D3003
starting at the specified address.
[A14 - A0]
SET_PLAY
[01100]
Sector Address
[A14 - A0]
PLAY
[01101]
[Don’t care]
The NOP command performs no operation in the device. It is
most often used when reading the current device status. For
more information on reading device status see the Current
Device Status section.
THE SID operation instructs the device to return the contents
of its silicon ID register. For more information see the Reading the SID section.
The SET_FWD command instructs the device to fast forward
from the beginning of the sector specified in the OpCode
parameter field. The device will fast forward until either an
EOD bit, or the end of the sector is reached. If no EOD bit or
forthcoming command has been received when the end of
the sector is reached, the device will loop back to the beginning of the same sector and begin the same process again. If
an EOD bit is found the device will stop and generate an
interrupt on the /INT pin. The output amplifiers are muted during this operation.
The FWD command instructs the device to fast forward from
the start of the current sector to the next EOD marker. If no
EOD marker is found within the current sector the device will
increment to the next sequential sector and continue looking.
Page 6
STOP,
STOP_PWDN,
SET_FWD, FWD,
SET_PLAY,PLAY,
NOP
Starts a play operation from the sector
address specified.
STOP,
STOP_PWDN,
SET_FWD, FWD,
SET_PLAY,PLAY,
NOP
Starts a play operation from the current
sector address.
The device will continue to fast forward in this manner until
either an EOD is reached, a new command is sent, or the end
of the memory array is reached. When an EOD is reached
the device will stop and generate an interrupt on the /INT pin.
The output amplifiers are muted during this operation.
The PWRUP command causes the device to enter power up
mode and set the internal clock frequency and EXTCLK
divider ratio. To select an Internal oscillator frequency set the
[A1 - A0] bits according to the following binary values:
A1
A0
Sample rate
0
0
6.4 kHz
0
1
4.0 kHz
1
0
8.0 kHz
1
1
5.3 kHz
If you are using an external sample clock signal you must
also set the EXTCLK divider ratio. This divider ratio is equal
to N:1 where N is an integer between 1 and 256, excluding 2.
The N value should be selected to satisfy the following equa-
Voice Recording & Playback Device
Revision 2.1
APR6008
tion as closely as possible:
EXTCLK freq = (N) * (128) * (selected sampling frequency)
Example:
Suppose that 8.0 KHz sampling is desired. Assume that
the frequency of the signal present on EXTCLK = 8MHz.
8000000
N = -------------------------- = 7.8125
128 ( 8000 )
Rounding up, N = 8
The Op Code Parameter bit stream, composed of bits
[A9 - A2][A1 - A0], therefore becomes binary
[00001000][10].
The STOP Command causes the device to stop the current
operation.
The STOP_PWDN command causes the device to stop the
current command and enter power down mode. During power
down the device consumes significantly less power. The
PWRUP command must be used to force the device into
power up mode before any commands can be executed.
The SET_REC command instructs the device to begin
recording at the sector address specified. The device will
continue to record until the end of the current sector is
reached. If no forthcoming command has been received
when the end of the sector is reached the device will loop
back to the beginning of the same sector and overwrite the
previously recorded material. If the next command is another
SET_REC or REC command the device will execute the command immediately following the end of the current sector so
that no audio information is lost. For more information see the
section entitled Recording Audio Data.
digital data that was previously written to the specified sector.
The first bit shifted out is the first bit that was written. The last
bit shifted out is the last bit that was written. For more information on reading digital data see the section entitled Reading Digital Data.
The SET_PLAY command instructs the device to begin playback at the specified sector. If no forthcoming command is
received, or EOD bit encountered, before the end of the sector is reached the device will loop back to the beginning of the
same sector and continue playback with no noticeable gap in
the audio output. If the next command is another SET_PLAY
or PLAY command the device will execute the command
immediately following the end of the current sector so that no
gap in playback is present. For more information see the section entitled Playing Back Audio Data.
The PLAY command instructs the device to begin playback at
the current sector. If no forthcoming command is received, or
EOD bit encountered, before the device reaches the end of
the sector the device will automatically increment to the next
sequential sector and continue playing. The device will continue to play in this manner until the memory is exhausted or
a STOP or STOP_PWDN command is received. For more
information see the section entitled Playing Back Audio Data.
The REC command instructs the device to begin recording in
the current sector. If no new command is received before the
device reaches the end of the sector the device will automatically increment to the next sequential sector and continue
recording. The device will continue to record in this manner
until the memory is exhausted or a STOP or STOP_PWDN
command is received. For more information see the section
entitled Recording Audio Data.
The DIG_ERASE command erases all data contained in the
sector specified. Erase should not be done before recording
voice signals into a sector. Erase must be done before storing
digital data in a sector.
The DIG_WRITE command stores 3K bits of digital data in
the specified sector. All 3K bits must be written, no partial
usage of the sector is possible. The memory acts as a FIFO,
the first data bit shifted in will be the first data bit shifted out. A
sector must be erased using the DIG_ERASE command
BEFORE data can be written to the sector. For more information on storing digital data, see the section entitled Writing
Digital Data.
The DIG_READ command instructs the device to retrieve
Voice Recording & Playback Device
Revision 2.1
Page 7
APR6008
Receiving Device Information
out three different types of data streams: Device status, Silicon ID, and user stored data. Device status and silicon ID are
described in the next two sections. Retrieval of user data is
described in the Reading Digital Data section.
The device communicates data to the user by shifting out
data on the DO pin. The device will shift out data according to
the timing parameters given in figure 7. The device can shift
Figure 7
Data Out Timing
/CS
~~
~~
SCLK
DI
Op4
D0
DO
TfcsDO
Op2
Op3
D1
Op1
~~
A3
D3~
D2
D16
D15
~
A1
A2
D17
A0
D18
D19
ThzD0
TfSCLK
Current Device Status (CDS)
As described in the previous section, three different types of
data streams are shifted out on the DO pin as data is shifted
in on the DI pin. One of these steams is the current device
status. The CDS will be shifted out unless the previous command is SID command. Figure 8 shows the format of the
CDS bit stream. The first bit shifted out, D0, is the Overflow
flag. The Overflow flag is set to a binary 1 if an attempt was
made to record beyond the available memory. The Overflow
flag is set to a 0 if an overflow has not occurred. This flag is
cleared after it has been read. The D1 bit is the End of Data
flag. The EOD flag is set when the device stops playing, or
fast forwarding as a result of an EOD bit in memory. The EOD
flag is cleared after it has been read. The D2 bit is the Illegal
Address flag. The Illegal Address flag is set whenever an illegal address is sent to the device. The D3 bit is the Lbat flag.
This flag is set when the device senses a supply voltage
below specification. The D4 bit is not used and should be
ignored. The last fifteen bits represent the address of the current or last active sector.
Figure 8 Format for CDS Bit Stream
Last bit shifted out
D19
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
}
~
~
First bit shifted out
OVF
EOD
Sector Address
Sector Add res s LSB
Illegal Address
Sector Address MSB
Lbat
Page 8
Voice Recording & Playback Device
Revision 2.1
APR6008
Reading the SID
OpCode commands; a SID command followed by any other
command, usually a NOP command. The device will clock
the SID data out on the DO pin as the command that follows
the SID command is clocked in. Figure 9 is a diagram that
describes the process necessary for reading SID information.
Each device in the APR60XX series family contains an
embedded Silicon Identification (SID). The SID can be read
by the host processor to identify which family / family member
is being used. Reading the device SID requires issuing two
Figure 9 SID Timing
SCLK
/CS
S ID C om m and
DI
N e xt C om m and
C D S O utput D ata
DO
S ID O utpu t D ata
The SID information follows the format given in Figure 10.
The first bit shifted out, D0, is the Overflow bit. The Overflow
bit is set to a binary 1 if an attempt was made to record
beyond the available memory. The Overflow bit is set to a 0 if
an overflow has not occurred. This bit is cleared after it has
been read. The D1 bit is the End Of Data (EOD) bit. The EOD
bit is set when the device stops playing or fast forwarding as
a result of EOD bit in memory. The EOD bit is cleared after it
has been read. The D2 bit is the Illegal Address Bit. The Illegal Address Bit is set whenever an illegal address is sent to
the device. The D3 bit is the Lbat bit. This bit is set when the
device senses a supply voltage below specification. The following five bits represent the product family. The APR60XX
product family code is binary 01000 as shown in Figure 10.
The next four bits represent the device code. The APR6008
device code is binary 0100 as shown in Figure 10 The last
seven bits are random data and should be ignored.
Figure 10 SID Bit Stream
Last bit shifted out
D19
D14
D13
D11
D10
Device
Code
0
1
0
APR6008 Device
Code (Binary)
Voice Recording & Playback Device
Revision 2.1
D9
0
D8
D7
D6
D5
D4
} }
Ignore These
Bits
D12
} }
}
~
~
First bit shifted out
D3
D2
1
0
0
0
D0
OVF
EOD
Product
Family
0
D1
Illegal Address
Lbat
APR60XX Series
Family (Binary)
Page 9
APR6008
Writing Digital Data
Digital data is written into the device using the DIG_WRITE
command. No mixing of analog data and digital data within a
sector is possible. Sectors 0 through 9 are tested and guaranteed for digital storage. Other sectors, with the exception of
sector 639, can store data but have not been tested, and are
thus not guaranteed to provide 100% good bits. This can be
managed with error correction or forward check-before-store
methods. Issuing a DIG_ERASE command on sector 639 will
cause data throughout all sectors to be lost.
A sector must be erased, using the DIG_ERASE command,
before digital data can be written to it. This requirement is
necessary whether analog data or digital data was previously
stored in the sector. A sector should not be erased more than
once between analog or digital write operations. Executing
multiple erase operations on a sector will permanently damage the sector. A sector can be reallocated to either analog
storage or digital storage at any time.
The process of storing digital data begins by sending a
DIG_WRITE command. The DIG_WRITE command is followed immediately by four buffer bits. These bits will not be
stored in the array and must be considered don’t care bits.
Immediately following the four buffer bits should be the data
that you wish to store. All 3004 bits must be stored. Four
additional buffer bits must be clocked into the device following the stored data. These bits will not be stored in the array
and must be considered don’t care bits. Ending a digital write
command early will permanently damage the sector.
The DO pin will clock out the normal 20 bit CDS followed by
five don’t care bits, a copy of the 3004 data bits, and finally
three don’t care bits.
Figure 11 shows a timing diagram which describes the digital
storage process. All timing with the exception of TpSCLK
should adhere to the specifications given in Figure 4 and Figure 7. The TpSCLK specification is replaced by the DTpSCLK
when storing digital data.
Note: The DIG_ERASE command should not be used before
storing analog data. The device will perform its own internal
erase before analog storage.
Figure 11 does not show the DIG_ERASE command which
must be executed on a sector before digital data can be
stored.
Figure 11 Writing Digital Data
SCLK
Total 3032 clock cycles
/CS
DI
DIG_WRITECOMMAND X
X X
X
3004 bits of data to be stored
X
X X X
Four Don’t Care Bits
DO
Page 10
CDS
X
X X X X
Copy of the input data (delayed one clock cycle)
X
X X
Voice Recording & Playback Device
Revision 2.1
APR6008
Reading Digital Data
Digital data is read from the device using the DIG_READ
command. To read data you must send a DIG_READ command immediately followed by 3012 don’t care bits during the
same /CS cycle. The data previously stored in the specified
sector will begin to appear on the DO pin after the current
device status or SID and four buffer bits. The next 3004 bits
are the previously stored data. The first bit shifted out is the
first bit that was written. The last bit shifted out is the last bit
that was written. There are four random don’t care bits following the 3004 bits of user data.
An incomplete read of the sector is allowed. An incomplete
read is defined a a read with less than 3032 clock cycles. All
incomplete read cycles require one extra SCLK cycle after
the /CS signal returns high.
Figure 12 shows a timing diagram which describes the entire
process for a complete sector read. All timing with the exception of TpSCLK should adhere to the specifications given in
Figure 4 and Figure 7. The TpSCLK specification is replaced
by the DTpSCLK when reading digital data.
Figure 12 Reading Digital Data
SCLK
Total 3032 clock cycles
/CS
DI
DIG_READ COMMAND
DO
SID or CDS
Voice Recording & Playback Device
Revision 2.1
3012 don’t Care Bits
X
X X
X
3004 bits of previously stored data
X
X X X
Page 11
APR6008
Recording Audio Data
When a SET_REC or REC command is issued the device will
begin sampling and storing the data present on ANAIN+ and
ANAIN- to the specified sector. After half the sector is used
the SAC pin will drop low to indicate that a new command can
be accepted. The device will accept commands as long as
the SAC pin remains low. Any command received after the
SAC returns high will be queued up and executed during the
next SAC cycle.
Figure 13 shows a typical timing diagram and OpCode
sequence for a recording operation. In this example the
SET_REC command begins recording at the specified memory location after Tarec time has passed. Some time later the
low going edge on the SAC pin alerts the host processor that
the first sector is nearly full. The host processor responds by
issuing a REC command before the SAC pin returns high.
The REC command instructs the APR6008 to continue
recording in the sector immediately following the current sector. When the first sector is full the device automatically jumps
to the next sector and returns the SAC signal to a high state
to indicate that the second sector is now being used. At this
point the host processor decides to issue a STOP command
during the next SAC cycle. The device follows the STOP
command and terminates recording after TSarec.The /BUSY
pin indicates when actual recording is taking place.
Figure 13 Typical Recording Sequence
SCLK
/CS
DI
REC
SET_REC
STOP
SAC
ANAOUT+
ANAOUTANAOUT
Tarec
TS arec
/BUSY
Page 12
Voice Recording & Playback Device
Revision 2.1
APR6008
Playing Back Audio Data
When a SET_PLAY or PLAY command is issued the device
will begin sampling the data in the specified sector and produce a resultant output on the AUDOUT, ANAOUT-, and
ANAOUT+ pins. After half the sector is used the SAC pin will
drop low to indicate that a new command can be accepted.
The device will accept commands as long as the SAC pin
remains low. Any command received after the SAC returns
high will be queued up and executed during the next SAC
cycle.
Figure 14 shows a typical timing diagram and OpCode
sequence for a playback operation. The SET_PLAY command begins playback at the specified memory location after
Taplay time has passed. Some time later the low going edge
on the SAC pin alerts the host processor that half of the first
sector has been played back. The host processor responds
by issuing a PLAY command during the SAC low time. The
PLAY command instructs the APR6008 to continue playback
of the sector immediately following the current sector. When
the first sector has been played back the device jumps to the
next sector and returns the SAC signal to a high state to indicate that the second sector is now being played. At this point
the host processor decides to issue a STOP command during
the next available SAC low time. The device follows the
STOP command and terminates playback after TS aplay. The /
BUSY pin indicates when actual playback is taking place.
Figure 14 Typical Playback Sequence
SCLK
/CS
DI
PLAY
SET_PLAY
STOP
SAC
ANAOUT+
ANAOUTANAOUT
Taplay
TS aplay
/BUSY
Note: Command timing is not scale
Handshaking signals
Several signals are included in the device that allow for handshaking. These signals can simplify message management
significantly depending on the message management
scheme used.
The /INT signal can be used to generate interrupts to the processor when attention is required by the APR6008 This pin is
normally high and goes low when an interrupt is requested.
An interrupt is generated whenever a EOD or Overflow
Voice Recording & Playback Device
Revision 2.1
occurs. An interrupt is also generated after a PWRUP command if a low battery VCC is sensed.
The SAC signal is used to determine when the device is
nearing the end of the current memory segment during either
a record, play or forward operation. The SAC signal is in a
normally high state. The signal goes low after half the currently active segment has been played or recorded. The signal returns to a high state after the entire segment has been
played or recorded. The microprocessor should sense the
Page 13
APR6008
low edge of the SAC signal as an indicator that the next segment needs to be selected, and do so before the SAC signal
returns high. Failing to specify the next command before the
current segment is exhausted (either during recording or
playback) will result in a noticeable gap during playback.
The /BUSY pin indicates when the device is performing either
a play, record or fast forward function. The host microprocessor can monitor the busy pin to confirm the status of these
commands. The Busy pin is normally high and goes low while
the device is busy. The low time is governed by the length of
recording or playback specified by the user.
Sampling Rate and Voice Quality
The Nyquist Sampling Theorem requires that the highest frequency component a sampling system can accommodate
without the introduction of aliasing errors is equal to half the
sampling frequency. The APR6008 automatically filters its
input, based on the selected sampling frequency, to meet this
requirement.
Higher sampling rates increase recording bandwidth, and
hence voice quality, but also use more memory cells for the
same amount of recording time. The APR6008 accommodates sampling rates as high as 8kHz.
Storage Technology
The APR6008 stores voice signals by sampling incoming
voice data and storing the sampled signals directly into
FLASH memory cells. Each FLASH cell can support voltage
ranges from 1 to 256 levels. These 256 discrete voltage levels are the equivalent of eight (28=256) bit binary encoded
values. During playback the stored signals are retrieved from
memory, smoothed to form a continuous signal and finally
amplified before being fed to an external speaker amplifier.
Squelch
The APR6008 is equipped with an internal squelch feature.
The Squelch circuit automatically attenuates the output signal
by 6 db during quiet passages in the playback material. Muting the output signal during quiet passages helps eliminate
background noise. Background noise may enter the system
in a number of ways including: present in the original signal,
natural noise present in some power amplifier designs, or
induced through a poorly filtered power supply.
The response time of the squelch circuit is controlled by the
time constant of the capacitor connected to the SQLCAP pin.
The recommended value of this capacitor is 1.0 uF. The
squelch feature can be disabled by connecting the SQLCAP
pin to VCC.
Lower sampling rates use less memory cells and effectively
The active low output /SQL goes low whenever the internal
increase the duration capabilities of the device, but also
reduce recording bandwidth. The APR6008 allows sampling squelch activates. This signal can be used to squelch the output power amplifier. Squelching the output amplifier results in
rates as low as 4 kHz.
further reduction of noise; especially when the power ampliDesigners can thus control the quality/duration trade-off by
fier is run at high gain & loud volumes.
controlling the sampling frequency. Sampling frequency can
be controlled by using the PWRUP command. This command
can change sampling frequency regardless of whether the
internal oscillator is used or an external clock is used.
The APR6008 derives its sampling clock from one of two
sources; internal or external. If a clocking signal is present on
the EXTCLK input the device will automatically use this signal
as the sampling clock source. If no input is present on the
EXTCLK input the device automatically defaults to the internal clock source. When the EXTCLK pin is not used it should
be tied to GND.
An internal clock divider is provided so that external clock signals can be divided down to a desired sampling rate. This
allows high frequency signals of up to 10 MHz to be fed into
the EXTCLK pin. Using this feature simplifies designs by
allowing use of a clock already present in the system, as
opposed to having to generate or externally divide down a
custom clock. Details for programing the clock divider are
described in the SPI interface section under the PWRUP
paragraph.
The default power up condition for the APR6008 is to use the
internal oscillator at a sampling frequency of 6.4 kHz.
Page 14
Voice Recording & Playback Device
Revision 2.1
APR6008
Sample Application
Figure 15 shows a sample application utilizing a generic
microcontroller and SPI interface for message management.
speaker. Several vendors supply integrated speaker amplifiers that can be used for this purpose.
The microcontroller uses three general purpose inputs for the
play, record and skip buttons. Five general purpose I/O signals are utilized in the SPI interface. The /RESET and /BUSY
signal are not used in this design.
A microphone amplifier and AGC are recommended. Both
blocks are optional. Several vendors supply integrated microphone/AGC amplifiers that can be used for this purpose.
The output signal must be amplified in order to drive a
Note that the AGC circuit can be simplified by using the SQLCAP signal as a
peak detector signal.
Figure 15 Sample Schematic using DIP package
V cc
Generic
Microcontroller
All resistors 2.2 K
Play
I/O_1
Record
I/O_2
Skip
I/O_3
Vcc
2.2K
2.2K
I/O_6
I/O_4
/IRQ
I/O_5
I/O_7
I/O_8
0 .1 µ F
APR6008 DIP
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/CS
DI
DO
V S SD
NC
NC
NC
A N AO U TAN A OU T +
NC
/R ES E T
VS SA
A UD O U T
S Q LC AP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
S C LK
V C CD
E XT C LK
/INT
S AC
V SS A
NC
/BU S Y
NC
NC
V C CA
A N AIN +
A N AIN /SQ LO UT
Vcc
M ic
AG C
Block
Mic
Pre-Amp
Vcc
Sp e a k e r
Am p lifie r
1 00K
1 .0 u F
Speaker
Voice Recording & Playback Device
Revision 2.1
Page 15
APR6008
Pin Descriptions
Table three shows pin descriptions for the APR6008 device.
All pins are listed in numerical order with the exception of
Table 3
Pin Name
VCC, VSS and NC pins which are listed at the end of the
table.
APR6008 28 Pin Number & Description
Pin No.
Pin No.
Pad No. (Die)
28 pin
SOP
28 pin
DIP
Reference Figure
18
Functionality
SAC
24
24
27
Sector Address Control Output: This active low output indicates when the
device is nearing the end of the current segment.
/INT
25
25
28
Interrupt Output: This active low open drain output goes low whenever the
device reaches the end of a message or the device overflows. When connected
to the interrupt input of the host microcontroller this output can be used to implement powerful message management options.
EXTCLK
26
26
29
External Clock Input: This input can be used to feed the device an external
sample clock instead of using the internal sampling clock. This pin should be connected to VSSA when not in use.
SCLK
28
28
33
SPI Clock Input: Data is clocked into the device through the DI pin upon the rising edge of this clock. Data is clocked out of the part through the DO pin on the
falling edge.
/CS
1
1
2
Chip Select Input: This active low input selects the device as the currently active
slave on the SPI interface. When this pin is high the device tri-states the DO pin
and ignores data on the DI pin.
DI
2
2
3
Data Input: The DI input pin receives the digital data input from the SPI bus.
Data is clocked on the rising edge of the SCLK input.
DO
3
3
4
Data Output: Data is available after the falling edge of the SCLK input.
ANAOUT-
8
8
9
Negative Audio Output: This is the negative audio output for playback of prerecorded messages. This output is usually fed to the negative input of a differential input power amplifier. The power amplifier drives an external speaker.
ANAOUT+
9
9
10
Positive Audio Output: This is the positive audio output for playback of prerecorded messages. This output is usually fed to the positive input of a differential
input power amplifier. The power amplifier drives an external speaker.
/RESET
11
11
11
Reset Input: This active low input clears all internal address registers and
restores the device to its power up defaults.
AUDOUT
13
13
15
Single Ended Audio Output: This is the audio output for playback of prerecorded messages. This output is usually fed to the input of a power amplifier for
driving an external speaker.
SQLCAP
14
14
16
Squelch Capacitor I/O: This pin controls the attack time of the squelch circuitry.
Connect his pin to GND through a 1.0 uf capacitor to enable the squelch feature.
The capacitor’s time constant will affect how quickly the squelch circuitry reacts.
/SQL
15
15
17
Squelch Output: This active low output indicates when the internal squelch circuitry has activated. This signal can be used to automatically squelch the external
power amplifier. Squelching the external power amplifier can result in an even
greater reduction of background noise.
ANAIN-
16
16
18
Inverting Analog Input: This input is the inverting input for the analog signal that
the user wishes to record. When the device is used in a differential input configuration this pin should receive a 16 mV peak to peak input coupled through a
0.1uF capacitor. When the device is used in a single ended input configuration
this input should be tied to VSSA through a 0.1 uF capacitor.
Connect this pin to VCCA to disable the squelch feature.
Page 16
Voice Recording & Playback Device
Revision 2.1
APR6008
Pin Name
Pin No.
Pin No.
Pad No. (Die)
28 pin
SOP
28 pin
DIP
Reference Figure
18
ANAIN+
17
17
19
Non-Inverting Analog Input: This input is the non-inverting input for the analog
signal that the user wishes to record. When the device is used in a differential
input configuration this pin should receive a 16 mV peak to peak input coupled
through a 0.1 uF capacitor. When the device is used in a single ended input configuration this pin should receive a 32 mV peak to peak input coupled through a
0.1 uF capacitor.
/BUSY
21
21
23
Busy Output: This active low output is low during either a record, playback or
fast forward operation. The pin is tri-stated otherwise. This pin can be connected
to an LED to indicate playback/record operation to the user. This pin can also be
connected to an external microcontroller as an indication of the status of playback, record, forward, or digital operation.
VCCD
27
27
30, 31, 32
Functionality
Digital Power Supply: This connection supplies power for all on-chip digital circuitry. This pin should be connected to the 3.0 V power plane through a via. This
pin should also be connected to a 0.1 uF bypass cap as close to the pin as possible.
VCCA
18
18
20, 21
Analog Power Supply: This connection supplies power for all on-chip analog
circuitry. This pin should be connected to the 3.0 V power plane through a via.
This pin should also be connected to a 0.1 uF bypass cap as close to the pin as
possible.
VSSA
12,23
12,23
12, 13, 14, 24,
25, 26
Analog Ground: These pins should be connected to the ground plane through a
via. The connection should be made as close to the pin as possible.
VSSD
4
NC
5, 6, 7,
10, 19,
20, 22
4
5, 6, 7,
10, 19,
20, 22
5, 6
1, 7, 8, 22
Digital Ground: This pin should be connected to the ground plane through a via.
The connection should be made as close to the pin as possible.
No Connect: These pins should not be connected to anything on the board. Connection of these pins to any signal, GND or VCC may result in incorrect device
behavior or cause damage to the device.
Electrical Characteristics
mended DC Characteristics, and recommended AC Characteristics for the APR6008 device.
The following tables list Absolute Maximum Ratings, Recom-
Absolute Maximum Ratings
mended DC Characteristics or recommended AC Characteristics of this specification is not implied. Maximum conditions
for extended periods may affect reliability.
Stresses greater than those listed in Table 4 may cause permanent damage to the device. These specifications represent a stress rating only. Operation of the device at these or
any other conditions above those specified in the recom-
Table 4
Absolute Maximum Ratings.
Item
Power Supply voltage
Symbol
Condition
Min
Max
Unit
VCC
TA = 25 C
-0.3
7.0
V
VIN
TA = 25 C
Device VCC = 3.0 V
-0.3
5.5
V
TSTG
-
-65
150
o
125
o
300
o
Input Voltage
Storage Temperature
Temperature Under Bias
TBS
-
Lead Temperature
TLD
<10s
Voice Recording & Playback Device
Revision 2.1
-65
C
C
C
Page 17
APR6008
Table 5
DC Characteristics
Item
Min
Typ
Max
Unit
VCCA
VCCD
2.9
3.0
3.3
V
Operating Temperature
TA
0
Input High Voltage
VIH
VCC = 2.9V
2.4
3
5.5
V
Input Low Voltage
VIL
VCC = 3.3V
VSS - 0.3V
0
.4
V
Output High Voltage
VOH
VCC = 2.7V
IOH=-1.6mA
VCCD - 0.5V
Output Low Voltage
VOL
VCC = 2.7V
IOL=1.0mA
Input Leakage Current
IIH
VCC = 3.3V
VIH=VCC
Input Leakage Current
IIL
VCC = 3.3V
VIL=VSS
Output Tristate Leakage Current
IOZ
VCC = 3.3V
VOUT=VCC
or
VOUT=Vss
Operating Voltage
Operating Current Consumption
Standby Current Consumption
Table 6
Symbol
ICC
ICCS
Condition
+70
o
C
V
0.4
V
0.3
1
uA
0
-1
uA
+1
uA
VCC = 3.3V
Recording
25
mA
Playback
15
mA
Idle
2.5
mA
VCC = 3.3V
After 20 sec.
uA
1
AC Characteristics
Item
Symbol
ANAIN+ or ANAIN- input voltage
Condition
Min
Typ
Max
Unit
VMI
45
50
mVP-P
ANAIN+ input resistance
RANAIN
3
ANAIN+/ANAIN- Gain
GANAIN
22
23
dB
ANAOUT Output Voltage
VANOUT
560
700
mVP-P
Total Harmonic Distortion
THD
@ 1kHz & 45mV P-P input
0.5
1
%
VCC ready to fall /CS
Tpwrup
90% of VCC min. specification
/RESET low time
Rise /RESET to fall /CS
k Ohm
10
ms
TloRST
1
ms
TRdone
1
ms
/CS fall to clock edge
Tfcs
500
ns
SPI Data set-up time
TsuDI
200
ns
Period SPI clock
TpSCLK
1000
ns
SPI data hold time
ThDI
200
ns
SPI clock low time
TloSCLK
400
ns
Page 18
Voice Recording & Playback Device
Revision 2.1
APR6008
Item
SPI clock high time
Clock to rising edge of /CS
Symbol
Condition
Min
Typ
Max
Unit
ThiSCLK
400
ns
TrCS
200
ns
Fall of /CS to DO output
TfcsDO
200
ns
Fall of SCLK to data out valid
TfSCLK
1000
ns
Rise of /CS to DO high Z
ThzDO
500
ns
Period SPI clock for digital read,
write
First SET_REC command to start
recording
DTpSCLK
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
500
250
Equation 1
uS
uS
S
Tarec
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
376
188
Equation 2
ms
ms
S
Rise of SAC after STOP Command to end of recording
TSarec
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
376
188
Equation 2
ms
ms
S
First SET_PLAY command to
audio output
Taplay
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
376
188
Equation 2
ms
ms
S
TSaplay
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
376
188
Equation 2
ms
ms
S
TpSAC
REC, PLAY @4kHz
REC, PLAY @8kHz
REC, PLAY EXTCLK
FWD @4kHz
FWD @8kHz
FWD @ EXTCLK
752
376
Equation 3
2
1
Equation 4
ms
ms
REC, PLAY @4kHz
REC, PLAY @8kHz
REC, PLAY EXTCLK
FWD @4kHz
FWD @8kHz
FWD @ EXTCLK
94
47
equation 5
0.25
0.125
Equation 6
ms
ms
STOP after SET_PLAY or PLAY
to end of audio output
SAC period
SAC low time
TloSAC
ms
ms
S
ms
ms
S
See Figure 6 and Table 1
Tnext1
5
uS
See Figure 6 and Table 1
Tnext2
5
mS
See Figure 6 and Table 1
Tnext3
Voice Recording & Playback Device
Revision 2.1
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
752
376
Equation 3
ms
ms
S
Page 19
APR6008
Item
See Figure 6 and Table 1
Symbol
Condition
Min
Typ
Max
Unit
Tnext4
Previous command =
SET_REC, REC,
SET_PLAY, PLAY
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
470
235
Equation 7
ms
ms
S
Previous command =
SET_FWD, FWD
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
1.25
0.625
Equation 8
ms
ms
Previous command =
All Others
@4kHz Internal sample clock
@8kHz Internal sample clock
External sample clock
5
5
5
uS
uS
uS
Notes:
ExternalClockPeriod
Equation1 = --------------------------------------------------------2 ( PrescalerValue )
1504 ( ExternalClockPeriod )
Equation2 = -------------------------------------------------------------------------PrescalerValue
3008 ( ExternalClockPeriod )
Equation3 = -------------------------------------------------------------------------PrescalerValue
8 ( ExternalClockPeriod )
Equation4 = ----------------------------------------------------------------PrescalerValue
376 ( ExternalClockPeriod )
Equation5 = ----------------------------------------------------------------------PrescalerValue
ExternalClockPeriod
Equation6 = --------------------------------------------------------PrescalerValue
1880 ( ExternalClockPeriod )
Equation7 = -------------------------------------------------------------------------PrescalerValue
5 ( ExternalClockPeriod )
Equation8 = ----------------------------------------------------------------PrescalerValue
Page 20
Voice Recording & Playback Device
Revision 2.1
APR6008
Figure 18 Bond Pad Layout and Coordinates
Origin
0
X Coordinate
NC
8
NC
9A
1
NA
11 0 AN
OU
AO
/R
ES
TET UT+
12 VSSA
13 VSSA
7
0
VSSD 6
VSSD 5
DO 4
Y Coordinate
14 VSSA
DI 3
15 AUDOUT
/CS 2
16 SQLCAP
*
Connect substrate
NC 1
to ground.
SCLK 33
17 / SQLOUT
VCCD 32
18 ANAIN-
VCCD 31
19 ANAIN+
VCCD 30
20 VCCA
EXTCLK 29
21 VCCA
22
NC
23
/B
US
Y
27
C
SA 6
2
SA
VS A 25
S
VS 24
SA
VS
/INT 28
Table 7
Pad
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
Coordinate Information
Pad
X
Y
Name
Coordinate Coordinate
NC
5149
2069
/CS
5149
1622
DI
5149
1243
DO
5149
901
VSSD
5149
610
VSSD
5149
383
NC
4795
108
NC
4412
108
ANAOUT560
108
ANAOUT+
108
288
/RESET
373
108
VSSA
108
655
VSSA
108
827
VSSA
108
1113
AUDOUT
108
1426
SQLCAP
108
1834
/SQLOUT
108
2518
ANAIN108
2795
ANAIN+
108
3066
VCCA
108
3397
VCCA
108
3627
Pad
Number
22
23
24
25
26
27
28
29
30
31
32
33
Pad
Name
NC
/BUSY
VSSA
VSSA
VSSA
SAC
/INT
EXTCLK
VCCD
VCCD
VCCD
SCLK
X
Y
Coordinate Coordinate
248
4106
548
4106
4314
4106
4486
4106
4658
4106
4906
4106
5149
3777
5149
3478
5149
2992
5149
2760
5149
2588
5149
2362
DIE SIZE : 4340µm x 5380µm
PAD SIZE : 100µm x 100µm
DIE THICKNESS : Approximately 25 mils
Voice Recording & Playback Device
Revision 2.1
•APPLICATION CIRCUIT DIAGRAM
•POWER APPLICATION CIRCUIT DIAGRAM
Page 22
Voice Recording & Playback Device
APR6008
APR6008 SOP Pin-out Diagram