MSC1201 MSC1202 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Precision, Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory FEATURES ANALOG FEATURES D MSC1201: D D D D D D D D D D D − 24 Bits No Missing Codes − 22 Bits Effective Resolution At 10Hz − Low Noise: 75nV MSC1202: − 16 Bits No Missing Codes − 16 Bits Effective Resolution At 200Hz − Noise: 600nV PGA From 1 to 128 Precision On-Chip Voltage Reference 6 Differential/Single-Ended Channels On-Chip Offset/Gain Calibration Offset Drift: 0.02ppm/°C Gain Drift: 0.5ppm/°C On-Chip Temperature Sensor Selectable Buffer Input Burnout Detect 8-Bit Current DAC DIGITAL FEATURES Microcontroller Core D 8051-Compatible D High-Speed Core: − 4 Clocks per Instruction Cycle D DC to 33MHz D On-Chip Oscillator D PLL with 32kHz Capability D Single Instruction 121ns D Dual Data Pointer Memory D 4kB or 8kB of Flash Memory D Flash Memory Partitioning D Endurance 1M Erase/Write Cycles, 100-Year Data Retention D 256 Bytes Data SRAM D In-System Serially Programmable D Flash Memory Security D 1kB Boot ROM Peripheral Features D 16 Digital I/O Pins D Additional 32-Bit Accumulator D Two 16-Bit Timer/Counters D System Timers D Programmable Watchdog Timer D Full-Duplex USART D Basic SPI D Basic I2C D Power Management Control D Internal Clock Divider D Idle Mode Current < 200mA D Stop Mode Current < 100nA D Digital Brownout Reset D Analog Low-Voltage Detect D 20 Interrupt Sources GENERAL FEATURES D D D D D Each Device Has Unique Serial Number Package: QFN-36 Low Power: 3mW at 3.0V, 1MHz Industrial Temperature Range: −40°C to +125°C Power Supply: 2.7V to 5.25V APPLICATIONS D D D D D D D D D D D Industrial Process Control Instrumentation Liquid/Gas Chromatography Blood Analysis Smart Transmitters Portable Instruments Weigh Scales Pressure Transducers Intelligent Sensors Portable Applications DAS Systems Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. I2C is a trademark of Philips Corporation. All other trademarks are the property of their respective owners. Copyright 2004−2005, Texas Instruments Incorporated ! ! www.ti.com "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 PACKAGE/ORDERING INFORMATION(1) PRODUCT FLASH MEMORY (BYTES) ADC RESOUTION (BITS) PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING MSC1201Y2 4k 24 QFN-36 RHH −40°C to +125°C MSC1201Y2 MSC1201Y3 MSC1202Y2 8k 24k QFN-36 RHH −40°C to +125°C MSC1201Y3 4k 16 QFN-36 RHH −40°C to +125°C MSC1202Y3 MSC1202Y2 8k 16 QFN-36 RHH −40°C to +125°C MSC1202Y3 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet, or refer to our web site at www.ti.com. MSC1201Yx/MSC1202Yx FAMILY FEATURES FEATURES(1) MSC120xY2(2) MSC120xY3(2) Flash Program Memory (Bytes) Up to 4k Up to 8k Flash Data Memory (Bytes) Up to 2k Up to 4k 256 256 Internal Scratchpad RAM (Bytes) (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents the onboard flash size = (2 N)kBytes. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS(1) MSC1201Yx, MSC1202Yx UNITS Momentary 100 mA Continuous 10 mA AGND − 0.3 to AVDD + 0.3 V DVDD to DGND AVDD to AGND −0.3 to +6 V −0.3 to +6 V AGND to DGND −0.3 to +0.3 V VREF to AGND −0.3 to AVDD + 0.3 V Digital input voltage to DGND −0.3 to DVDD + 0.3 V Digital output voltage to DGND −0.3 to DVDD + 0.3 V Maximum junction temperature +150 °C Operating temperature range −40 to +125 °C Storage temperature range −65 to +150 °C +235 °C Analog Inputs Input current Input voltage Power Supply Lead temperature (soldering, 10s) Package power dissipation Output current, all pins Output pin short-circuit Thermal Resistance Junction to ambient (qJA) (TJ Max − TAMBIENT)/qJA W 200 mA 10 s High K (2s 2p) 21.9 °C/W Low K (1s) 103.7 °C/W Junction to case (qJC) 21.9 °C/W Continuous Digital Outputs Output current 100 mA I/O source/sink current 100 mA Power pin maximum 300 mA (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER CONDITION MIN TYP MAX UNITS Analog Input (AIN0-AIN5, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (In+) − (In−) Differential Input Impedance Buffer OFF Input Current Buffer ON Bandwidth ±VREF/PGA V 7/PGA(1) MΩ 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA Sinc2 Filter −3dB 0.318 • fDATA Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer ON Input Leakage Current Multiplexer Channel OFF, T = +25°C 0.5 pA Burnout Current Sources Buffer ON ±2 µA ±VREF/(2 • PGA) V Offset DAC Full-Scale Gain Error ±1.0 % of Range Offset DAC Full-Scale Gain Error Drift 0.6 ppm/°C 7 pF ADC Offset DAC Offset DAC Range Offset DAC Resolution 8 Bits System Performance Resolution ENOB MSC1201 24 Bits MSC1202 16 Bits MSC1201 22 Bits MSC1202 16 Bits Output Noise No Missing Codes See Typical Characteristics MSC1201, Sinc3 Filter, Decimation > 360 24 Bits MSC1202, Sinc3 Filter 16 Bits ±0.0004 ±0.0015 Integral Nonlinearity End Point Fit, Differential Input Offset Error After Calibration 1.5 ppm of FS % of FSR Offset Drift(2) Before Calibration 0.02 ppm of FS/°C Gain Error(3) After Calibration 0.005 % Gain Error Drift(2) Before Calibration 0.5 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS Common-Mode Rejection Normal-Mode Rejection Power-Supply Rejection (1) (2) (3) (4) At DC 120 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fCM = 50Hz, fDATA = 50Hz 100 dB fCM = 60Hz, fDATA = 60Hz 100 dB At DC, dB = −20log(∆VOUT/∆VDD)(4) 100 dB The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 3 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER CONDITION MIN TYP MAX UNITS AVDD(3) V AVDD V Voltage Reference Input Reference Input Range REF IN+, REF IN− ADC VREF VREF ≡ (REFIN+) − (REFIN−) VREF Common-Mode Rejection At DC Input Current VREF = 2.5V, PGA = 1 AGND 0.1 2.5 115 dB 1 µA VREFH = 1 at +25°C 2.5 V VREFH = 0 1.25 V Short-Circuit Current Source 8 mA Short-Circuit Current Sink 50 mA On-Chip Voltage Reference Output Voltage Short-Circuit Duration Sink or Source Startup Time from Power ON CREFOUT = 0.1µF Indefinite 8 ms Temperature Sensor Temperature Sensor Voltage T = +25°C 115 mV 345 µV/°C IDAC Resolution 8 Bits Full-Scale Output Current 1 mA Temperature Sensor Coefficient IDAC Output Characteristics Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD − 1.5 V Analog Power-Supply Requirements Analog Power-Supply Voltage (1) (2) (3) (4) 4 4.75 5.0 5.25 V BOR OFF, External Clock Mode, Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 <1 nA PGA = 1, Buffer OFF 170 µA PGA = 128, Buffer OFF 430 µA PGA = 1, Buffer ON 230 µA PGA = 128, Buffer ON 770 µA VREF Supply Current (IVREF) ADC ON 360 µA IDAC Supply Current (IIDAC) IDAC = 00h 230 µA Analog Current Analog Power-Supply Current AVDD ADC Current (IADC) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Input (AIN0-AIN5, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Buffer ON AGND + 50mV AVDD − 1.5 V ±VREF/PGA Full-Scale Input Voltage Range (In+) − (In−) Differential Input Impedance Buffer OFF 7/PGA(1) MΩ Input Current Buffer ON 0.5 nA Bandwidth Fast Settling Filter −3dB 0.469 • fDATA Sinc2 Filter −3dB 0.318 • fDATA Sinc3 Filter −3dB 0.262 • fDATA 1 V Programmable Gain Amplifier User-Selectable Gain Range Input Capacitance Buffer ON 128 Input Leakage Current Multiplexer Channel Off, T = +25°C 0.5 pA Burnout Current Sources Buffer ON ±2 µA 7 pF ADC Offset DAC ±VREF/(2 • PGA) Offset DAC Range Offset DAC Resolution V 8 Bits Offset DAC Full-Scale Gain Error ±1.5 % of Range Offset DAC Full-Scale Gain Error Drift 0.6 ppm/°C System Performance Resolution ENOB MSC1201 24 Bits MSC1202 16 Bits MSC1201 22 Bits MSC1202 16 Bits Output Noise No Missing Codes See Typical Characteristics MSC1201, Sinc3 Filter, Decimation > 360 24 MSC1202, Sinc3 Filter 16 Bits Bits ±0.0004 ±0.0015 Integral Nonlinearity End Point Fit, Differential Input Offset Error After Calibration 1.3 ppm of FS Offset Drift(2) Before Calibration 0.02 ppm of FS/°C Gain Error(3) After Calibration 0.005 % Gain Error Drift(2) Before Calibration 0.5 ppm/°C System Gain Calibration Range 80 System Offset Calibration Range Common-Mode Rejection Normal-Mode Rejection Power-Supply Rejection (1) (2) (3) (4) −50 % of FSR 120 % of FS 50 % of FS At DC 130 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB At DC, dB = −20log(∆VOUT/∆VDD)(4) 88 dB The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 5 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS MIN TYP MAX UNITS AVDD(3) V AVDD V Voltage Reference Input Reference Input Range REF IN+, REF IN− AGND ADC VREF VREF ≡ (REFIN+) − (REFIN−) VREF Common-Mode Rejection At DC 110 dB Input Current VREF = 1.25V, PGA = 1 0.5 µA VREFH = 0 at +25°C 1.25 V 8 mA 50 µA 0.1 1.25 On-Chip Voltage Reference Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Sink or Source Indefinite Startup Time from Power ON CREFOUT 8 ms T = +25°C 115 mV 345 µV/°C 8 Bits 1 mA Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient IDAC Output Characteristics IDAC Resolution Full-Scale Output Current Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD − 1.5 V Analog Power-Supply Requirements Analog Power-Supply Voltage Analog Current Analog Power-Supply Current (1) (2) (3) (4) 6 ADC Current (IADC) AVDD 2.7 3.6 V BOR OFF, External Clock Mode, Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 <1 nA PGA = 1, Buffer OFF 150 µA PGA = 128, Buffer OFF 380 µA PGA = 1, Buffer ON 200 µA PGA = 128, Buffer ON 610 µA VREF Supply Current (IVREF) ADC ON 330 µA IDAC Supply Current (IIDAC) IDAC = 00h 220 µA The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V All specifications from TMIN to TMAX, unless otherwise specified. MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS MIN TYP MAX 2.7 3.0 3.6 UNITS Digital Power-Supply Requirements DVDD Normal Mode, fOSC = 1MHz mA 5 mA Internal Oscillator LF Mode (12.8MHz nominal) 7.1 mA Stop Mode, External Clock OFF 100 Normal Mode, fOSC = 8MHz, All Peripherals ON Digital Power-Supply Current DVDD 4.75 nA 5.0 Normal Mode, fOSC = 1MHz Digital Power-Supply Current V 0.6 5.25 V 1.2 mA Normal Mode, fOSC = 8MHz, All Peripherals ON 9 mA Internal Oscillator LF Mode (12.8MHz nominal) 15 mA Internal Oscillator HF Mode (25.6MHz nominal) 29 mA Stop Mode, External Clock OFF 100 nA Digital Input/Output (CMOS) Logic Level VIH (except XIN pin) 0.6 • DVDD DVDD V VIL (except XIN pin) DGND 0.2 • DVDD V Ports 1 and 3, Input Leakage Current, Input Mode VIH = DVDD or VIH = 0V I/O Pin Hysteresis VOL, Ports 1 and 3, All Output Modes VOH, Ports 1 and 3, Strong Drive Output IOL = 1mA 0 µA 700 mV DGND 0.4 IOL = 30mA, 3V (20mA) 1.5 IOH = 1mA DVDD − 0.4 IOH = 30mA, 3V (20mA) V V DVDD − 0.1 DVDD V DVDD − 1.5 V 11 kΩ Ports 1 and 3, Pull-Up Resistors FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V tUSEC = 1µs and tMSEC = 1ms MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS Flash Memory Endurance Flash Memory Data Retention MIN TYP 100,000 1,000,000 MAX cycles 100 Mass and Page Erase Time Set with FER Value in FTCON, from TMIN to TMAX 10 Flash Memory Write Time Set with FWR Value in FTCON 30 UNITS Years ms 40 µs 7 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 AC ELECTRICAL CHARACTERISTICS(1): DVDD = 2.7V to 5.25V MSC1201Yx, MSC1202Yx PARAMETER MIN CONDITION PHASE LOCK LOOP (PLL) Input Frequency Range PLL LF Mode PLL HF Mode PLL Lock Time TYP External Crystal/Clock Frequency (fOSC) PLLDIV = 449 (default) PLLDIV = 899 (must be set by user), DVDD = 5V Within 1% INTERNAL OSCILLATOR (IO) IO LF Mode IO HF Mode IO Settling Time MAX UNITS 2 kHz MHz MHz ms 1 MHz MHz ms 32.768 14.8 29.5 See Typical Characteristics 14.7 29.5 DVDD = 5V Within 1% (1) Parameters are valid over operating temperature range, unless otherwise specified. EXTERNAL CLOCK DRIVE CLK TIMING: SEE FIGURE 1 SYMBOL 2.7V to 3.6V MIN MAX PARAMETER External Clock Mode fOSC(1) 1/tOSC(1) fOSC(1) tHIGH tLOW tR tF External Crystal Frequency (fOSC) External Clock Frequency (fOSC) External Ceramic Resonator Frequency (fOSC) HIGH Time(2) LOW Time(2) Rise Time(2) Fall Time(2) 1 0 1 15 15 4.75V to 5.25V 20 20 12 MIN MAX UNITS 1 0 1 10 10 33 33 12 MHz MHz MHz ns ns ns ns 5 5 5 5 (1) t CLK = 1/fOSC = one oscillator clock period for clock divider = 1. (2) These values are characterized but not 100% production tested. tHIGH VIH tR VIH VIH 0.8V 0.8V tLOW tF VIH 0.8V 0.8V tOSC Figure 1. External Clock Drive CLK SERIAL FLASH PROGRAMMING TIMING: SEE FIGURE 2 SYMBOL tRW tRRD tRFD tRS tRH PARAMETER MIN MAX UNITS RST width RST rise to P1.0 internal pull high RST falling to CPU start Input signal to RST falling setup time RST falling to P1.0 hold time 2 tOSC — — tOSC 18 — 5 18 — — ns µs ms ns ms t RW RST t RRD tRS tRFD, tRH P1.0/PROG NOTE: P1.0 is internally pulled−up with ~11kΩ during RST high. Figure 2. External Clock Drive CLK 8 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 P3.7 P3.6/SCK/SCL/CLKS P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD0 P3.0/RxD0 P1.7/INT5 PIN CONFIGURATION 36 35 34 33 32 31 30 29 28 XIN 1 27 DVDD XOUT 2 26 DGND DGND 3 25 P1.6/INT4 RST 4 24 P1.5/INT3 23 P1.4/INT2/SS MSC1201 MSC1202 P1.2/DOUT AGND 8 20 P1.1 AINCOM 9 19 P1.0/PROG 10 11 12 13 14 15 16 17 18 AIN0 21 AIN1 7 AIN2 AGND AIN3 P1.3/DIN AIN4 22 AIN5 6 REFIN− AVDD REFOUT/REFIN+ 5 IDAC NC 9 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 PIN ASSIGNMENTS PIN # NAME DESCRIPTION 1 XIN 2 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 3, 26 DGND Digital Ground 4 RST A HIGH on the reset input for two tOSC periods will reset the device. 5 NC No connection 6 AVDD Analog Power Supply 7, 8 AGND Analog Ground 9 AINCOM 10 IDAC The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. XIN must not be left floating. Analog Input (can be analog common for single-ended inputs or analog input for differential inputs) IDAC Output 11 REFOUT/REF IN+ 12 REF IN− 13 AIN5 Analog Input Channel 5 14 AIN4 Analog Input Channel 4 15 AIN3 Analog Input Channel 3 16 AIN2 Analog Input Channel 2 17 AIN1 Analog Input Channel 1 18 AIN0 Analog Input Channel 0 19−25, 28 P1.0−P1.7 10 27 DVDD 29−36 P3.0−P3.7 Internal Voltage Reference Output/Voltage Reference Positive Input Voltage Reference Negative Input (tie to AGND for internal voltage reference) Port 1 is a bidirectional I/O port (refer to P1DDRL, SFR AEh, and P1DDRH, SFR AFh, for port pin configuration control). The alternate functions for Port 1 are listed below. Port Alternate Name(s) Alternate Use P1.0 PROG Serial programming mode P1.1 N/A P1.2 DOUT Serial data out P1.3 DIN Serial data in P1.4 INT2/SS External interrupt 2 / Slave Select P1.5 INT3 External interrupt 3 P1.6 INT4 External interrupt 4 P1.7 INT5 External interrupt 5 Digital Power Supply Port 3 is a bidirectional I/O port (refer to P3DDRL, SFR B3h, and P3DDRH, SFR B4h, for port pin configuration control). The alternate functions for Port 3 are listed below. Port Alternate Name(s) Alternate Use P3.0 RxD0 Serial port 0 input P3.1 TxD0 Serial port 0 output P3.2 INT0 External interrupt 0 P3.3 INT1 External interrupt 1 P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 SCK/SCL/CLKS SCK / SCL / various clocks (refer to PASEL, SFR F2h) P1.7 N/A "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS: MSC1201 ONLY AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 22 PGA2 PGA1 PGA1 PGA8 21 PGA32 PGA64 20 PGA4 PGA8 19 PGA128 ENOB (rms) ENOB (rms) EFFECTIVE NUMBER OF BITS vs DATA RATE 18 PGA16 17 PGA32 PGA64 16 15 14 Sinc3 Filter, Buffer OFF Sinc3 Filter, Buffer OFF 13 12 1 10 100 Data Rate (SPS) 1000 0 500 1000 1500 PGA2 PGA1 PGA8 PGA4 21 PGA1 20 20 19 19 ENOB (rms) ENOB (rms) 22 PGA8 PGA4 PGA2 21 fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 2000 fMOD Decimation Ratio = 18 17 PGA128 PGA64 PGA32 16 PGA16 18 17 PGA16 PGA32 PGA128 PGA64 16 15 15 14 14 Sinc3 Filter, Buffer ON AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF 13 13 12 12 0 500 1000 1500 Decimation Ratio = 0 2000 500 f MOD 1000 1500 Decimation Ratio = fDATA 2000 f MOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA2 21 PGA4 PGA2 PGA8 21 PGA1 20 20 19 19 ENOB (rms) ENOB (rms) PGA128 18 17 16 PGA16 15 PGA32 PGA128 PGA64 PGA4 18 17 PGA32 PGA16 PGA64 PGA128 16 15 14 14 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON 13 PGA8 PGA1 Sinc2 Filter 13 12 12 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000 0 500 1000 Decimation Ratio = 1500 2000 fMOD fDATA 11 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS: MSC1201 ONLY (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 25 19 18 fMOD = 203kHz Gain = 1 17 20 ENOB (rms) ENOB (Bits) 16 15 14 Gain = 128 13 12 fMOD = 15.6kHz fMOD = 110kHz 15 fMOD = 31.25kHz 10 11 5 10 fMOD = 62.5kHz Fast Settling Filter 9 0 8 0 500 1000 1500 Decimation Ratio = 1 2000 10 DEC = 2020 2.5 0.7 DEC = 255 Noise (rms, ppm of FS) ENOB (rms) 1.5 NOISE vs INPUT SIGNAL DEC = 500 DEC = 50 DEC = 20 10 5 DEC = 10 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 100 1k Data Rate (SPS) 10k − 2.5 100k − 1.5 − 0.5 HISTOGRAM OF ADC OUTPUT DATA 4000 Number of Occurrences 0.5 VIN (V) 4500 3500 3000 2500 2000 1500 1000 500 0 −2 − 1.5 −1 − 0.5 0 ppm of FS 12 100k 0.8 20 15 10k fDATA EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION 25 100 1k Data Rate (SPS) fMOD 0.5 1 1.5 2 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS: MSC1202 ONLY AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 20 20 19 19 18 18 17 17 16 15 PGA1 14 ENOB (rms) ENOB (rms) EFFECTIVE NUMBER OF BITS vs DATA RATE PGA1 16 PGA128 15 14 13 13 12 12 PGA128 11 Sinc3 Filter, Buffer OFF 11 Sinc3 Filter, Buffer OFF 10 10 1 10 100 Data Rate (SPS) 0 1000 500 1000 Decimation Ratio = 20 20 19 19 18 18 17 ENOB (rms) ENOB (rms) PGA1 16 15 14 PGA128 13 fDATA PGA1 16 PGA128 15 14 13 12 12 Sinc3 Filter, Buffer ON AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF 11 11 10 10 0 500 1000 Decimation Ratio = 1500 0 2000 500 f MOD 20 19 19 18 18 17 ENOB (rms) PGA1 16 PGA128 15 1500 2000 fMOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 20 17 1000 Decimation Ratio = fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO ENOB (rms) 2000 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 17 1500 fMOD 14 PGA1 16 PGA128 15 14 13 13 12 12 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON 11 10 10 0 500 1000 Decimation Ratio = 1500 fMOD fDATA Sinc2 Filter 11 2000 0 500 1000 Decimation Ratio = 1500 2000 fMOD fDATA 13 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS: MSC1202 ONLY (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) 20 20 19 fMOD = 203kHz 18 16 fMOD = 15.6kHz ENOB (rms) ENOB (rms) 17 16 15 14 fMOD = 110kHz fMOD = 31.25kHz 12 13 8 12 Fast Settling Filter 11 fMOD = 62.5kHz 4 10 0 500 1500 1000 Decimation Ratio = 2000 1 10 fMOD 100 1k Data Rate (SPS) fDATA EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION 25 20 DEC > 100 ENOB (rms) DEC = 50 15 DEC = 20 10 5 DEC = 10 0 10 14 100 1k Data Rate (SPS) 10k 100k 10k 100k "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS: MSC1201 AND MSC1202 AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. ADC INTEGRAL NONLINEARITY vs INPUT SIGNAL ADC INTEGRAL NONLINEARITY vs INPUT VOLTAGE 15 15 AVDD = 5V VREF = 2.5V ADC INL (ppm) −55_ C +25_ C 5 0 −5 5 0 −5 −10 −10 +125_C +85_C −15 −2.5 −2.0 −1.5 −1.0 −0.5 −15 0 0.5 1.0 1.5 2.0 VIN = −VREF 2.5 0 VIN = +VREF ADC Input Voltage (V) VIN (V) ADC INTEGRAL NONLINEARITY vs VREF ADC INTEGRAL NONLINEARITY ERROR vs PGA 30 50 VIN = VREF Buffer OFF AVDD = 5V VREF = 2.5V 45 25 40 INL (ppm of FS) INL (ppm of FS) VREF = AVDD = 5V Buffer OFF 10 INL (ppm of FS) 10 −40_C 20 15 AVDD = 3V 10 AVDD = 5V 35 30 25 20 15 10 5 5 0 0 0 1.3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 2 4 8 16 32 VREF (V) PGA Setting ANALOG SUPPLY CURRENT vs ANALOG SUPPLY VOLTAGE ADC POWER−SUPPLY CURRENT vs PGA PGA = 128 DVDD = AVDD VREF = 1.25V 64 128 64 128 0.8 +125_ C 0.7 +85_ C AVDD = 5V, Buffer = ON 0.6 1.2 +25_ C I ADC (µA) Analog Supply Current (mA) 1.4 0.5 1.0 1.5 2.0 1.1 −40_C 1.0 −55_C AVDD = 3V, Buffer = ON 0.5 AVDD = 5V, Buffer = OFF 0.4 0.9 0.3 0.8 0.2 AVDD = 3V, Buffer = OFF 0.1 0.7 2.5 3.0 3.5 4.0 4.5 Analog Supply Voltage (V) 5.0 5.5 1 2 4 8 16 32 PGA Setting 15 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS: MSC1201 AND MSC1202 (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. 14 12 10 8 6 4 2 0 −2 −4 −6 −8 − 10 − 12 − 14 − 16 ADC OFFSET DAC: GAIN vs TEMPERATURE 1.00008 1.00006 1.00004 Normalized Gain Offset (ppm of FSR) ADC OFFSET DAC: OFFSET vs TEMPERATURE 1.00002 1 0.99998 0.99996 0.99994 − 60 − 40 − 20 0.99992 0 +20 +40 − 60 +60 +80 +100 +120 +140 − 40 − 20 0 DIGITAL SUPPLY CURRENT vs EXTERNAL CLOCK FREQUENCY DVDD = 5V Normal Mode DVDD = 3V Normal Mode DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER 100 Divider Values 1 DVDD = 5V Idle Mode 10 1 DVDD = 3V Idle Mode Digital Supply Current (mA) Digital Supply Current (mA) 100 2 4 10 8 16 32 1 1024 0.1 0.1 1 10 1 100 10 DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY VOLTAGE ADC NORMALIZED GAIN vs PGA 101 Buffer ON PGA = 128 DVDD = AVDD VREF = 1.25V 100 +125_ C Normalized Gain (%) Digital Supply Current (mA) 10 9 +85_C 8 +25_C 7 100 Clock Frequency (MHz) Clock Frequency (MHz) 11 +20 +40 +60 +80 +100 +120 +140 Temperature (_C) Temperature (_C) −55_C 6 −40_C 5 99 98 97 96 4 95 3 2.5 3.0 3.5 4.0 4.5 Digital Supply Voltage (V) 16 5.0 5.5 1 2 4 8 16 PGA Setting 32 64 128 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 TYPICAL CHARACTERISTICS: MSC1201 AND MSC1202 (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. VOLTAGE REFERENCE CURRENT vs PGA SETTING DIGITAL OUTPUT PIN VOLTAGE 5.0 40 4.5 5V Low Output 3.5 3V Low Output 3.0 Input Current (µA) Output Voltage (V) 4.0 2.5 2.0 1.5 25 VREF = 2.5V fMOD = 15.6kHz 20 VREF = 1.25V f MOD = 15.6kHz 15 5 0.5 3V 0 0 0 10 20 30 40 50 60 70 1 2 4 8 16 32 64 Output Current (mA) PGA Gain INTERNAL OSCILLATOR LOW−FREQUENCY MODE vs TEMPERATURE INTERNAL OSCILLATOR HIGH−FREQUENCY MODE vs TEMPERATURE 16.0 128 32 5.25V 15.5 31 4.75V 15.0 IO Frequency (MHz) IO Frequency (MHz) VREF = 1.25V f MOD = 62.5kHz 30 10 5V 1.0 14.5 14.0 13.5 3.3V 13.0 2.7V 30 5.25V 29 4.75V 28 27 12.5 26 12.0 −60 −40 −20 0 20 40 60 80 100 −60 120 140 −40 −20 0 20 40 60 80 Temperature (_ C) Temperature (_C) IDAC OUTPUT CURRENT vs IDAC OUTPUT VOLTAGE IDAC OUTPUT CURRENT vs TEMPERATURE 100 120 140 100 120 140 960 1.1 1.0 AVDD = 5V 0.9 IDAC Output Current (µA) IDAC Output Current (mA) VREF = 2.5V fMOD = 62.5kHz 35 0.8 0.7 AVDD = 3V 0.6 0.5 0.4 0.3 0.2 IDAC = FFh 940 920 900 880 860 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IDAC Output Votage (V) 4.5 5.0 5.5 840 −60 −40 −20 0 20 40 60 80 Temperature (_C) 17 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 DESCRIPTION The MSC1201Yx/MSC1202Yx are completely integrated families of mixed-signal devices incorporating a high-resolution, delta-sigma ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect current sources, selectable buffered input, offset DAC, programmable gain amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 3. The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 core, given the same clock source. This makes it possible to run the device at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core. The MSC1201Yx/MSC1202Yx allow the user to uniquely configure the Flash Memory map to meet the needs of their application. The Flash is programmable down to +2.7V using serial programming. Flash endurance is typically 1M Erase/Write cycles. On-chip peripherals include an additional 32-bit accumulator, basic SPI, basic I2C, USART, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, brownout reset, timer/counters, system clock divider, PLL, on-chip oscillator, and external interrupts. The parts have separate analog and digital supplies, which can be independently powered from +2.7V to +5.25V. At +3V operation, the power dissipation for the part is typically less than 3mW. The MSC1201Yx/MSC1202Yx are both packaged in a QFN-36 package. The devices accept low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits (MSC1201) or 16 bits (MSC1202) of resolution and 24 bits (MSC1201) or 16 bits (MSC1202) of no-missing-code performance using a Sinc3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolution single-cycle conversion. AVDD The MSC1201Yx/MSC1202Yx are designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. REFOUT/REFIN+ REF IN− (1) AGND DVDD DGND AVDD Burnout Detect VREF Temperature Sensor ALVD Timers/ Counters DBOR 8−Bit Offset DAC AIN0 WDT AIN1 Alternate Functions AIN2 AIN3 AIN4 MUX BUF PGA Digital Filter Modulator AIN5 AINCOM Burnout Detect 4K or 8K FLASH ACC 128 Bytes SRAM 8051 SFR AGND IDAC POR 8−Bit IDAC System Clock Divider PORT1 DIN DOUT SS EXT (4) PROG PORT3 USART EXT (2) T0 T1 SCK/SCL/CLKS On−Chip Oscillator PLL XIN XOUT NOTE: (1) REF IN− must be tied to AGND when using internal VREF. Figure 3. Block Diagram 18 RST "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ENHANCED 8051 CORE Single−Byte, Single−Cycle Instruction MSC1201/02 Timing All instructions in the MSC1201/02 families perform exactly the same functions as they would in a standard 8051. The effects on bits, flags, and registers are the same; however, the timing is different. The MSC1201/02 families use an efficient 8051 core that results in an improved instruction execution speed of between 1.5 and 3 times faster than the original core for the same external clock speed (4 clock cycles per instruction versus 12 clock cycles per instruction, as shown in Figure 4). This translates into an effective throughput improvement of more than 2.5 times, using the same code and same external clock speed. Therefore, a device frequency of 33MHz for the MSC1201Yx/MSC1202Yx actually performs at an equivalent execution speed of 82.5MHz compared to the standard 8051 core. This allows the user to run the device at slower clock speeds, which reduces system noise and power consumption, but provides greater throughput. This performance difference can be seen in Figure 5. The timing of software loops will be faster with the MSC1201/02. However, the timer/counter operation of the MSC1201/02 may be maintained at 12 clocks per increment or optionally run at 4 clocks per increment. ALE PSEN Internal AD0−AD7 Internal A8−A15 4 Cycles CLK Standard 8051 Timing 12 Cycles ALE PSEN AD0−AD7 PORT 2 Single−Byte, Single−Cycle Instruction Figure 5. Comparison of MSC1201/02 Timing to Standard 8051 Timing The MSC1201Yx/MSC1202Yx also provide dual data pointers (DPTRs). CLK instr_cycle cpu_cycle n+1 C1 C2 n+2 C3 C4 C1 C2 C3 C4 C1 Figure 4. Instruction Timing Cycle 19 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 to add or subtract software functions and to freely migrate between family members. Thus, the MSC1201/02 can become a standard device used across several application platforms. Furthermore, improvements were made to peripheral features that off-load processing from the core, and the user, to further improve efficiency. For instance, 32-bit accumulation can be done through the summation register to significantly reduce the processing overhead for the multiple byte data from the ADC or other sources. This allows for 32-bit addition, subtraction and shifting to be accomplished in a few instruction cycles, compared to hundreds of instruction cycles through software implementation. Family Development Tools The MSC1201Yx/MSC1202Yx are fully compatible with the standard 8051 instruction set. This means that the user can develop software for the MSC1201/02 with their existing 8051 development tools. Additionally, a complete, integrated development environment is provided with each demo board, and third-party developers also provide support. Family Device Compatibility The hardware functionality and pin configuration across the MSC1201/02 families are fully compatible. To the user, the only differences between family members are the memory configuration. This makes migration between family members simple. Code written for the MSC1201Y2 or MSC1202Y2 can be executed directly on an MSC1201Y3 or MSC1202Y3, respectively. This gives the user the ability Power-Down Modes The MSC1201Yx/MSC1202Yx can each power several of the peripherals and put the CPU into IDLE. This is accomplished by shutting off the clocks to those sections, as shown in Figure 6. tSYS SYS CLK C7 tCLK SPICON/ I2CCON 9A SCL/SCK PDCON.0 µs USEC FTCON Flash Write (30µs to 40µs) [3:0] EF Timing FB ms MSECL MSECH FC FD Flash Erase (5ms to 11ms) FTCON [7:4] EF Timing milliseconds interrupt MSINT FA PDCON.1 seconds interrupt SECINT F9 100ms HMSEC WDTCON FF FE watchdog PDCON.2 ACLK F6 divide by 64 ADC Power Down ADC Output Rate Modulator Clock PDCON.3 Timers 0/1 IDLE ADCON3 ADCON2 DF DE Decimation Ratio USART CPU Clock Figure 6. MSC1201/02 Timing Chain and Clock Control 20 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 OVERVIEW The MSC1201/02 ADC structure is shown in Figure 7. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component. AVDD Burnout Detect AIN0 REFIN+ AIN1 AIN2 AIN3 f SAMP Input Multiplexer AIN4 In+ AIN5 AINCOM Sample and Hold Buffer In− Σ PGA Temperature Sensor Burnout Detect D7h ADMUX REFIN+ fMOD Offset DAC REFIN− AGND DCh ADCON0 F6h ACLK E6h ODAC f DATA FAST VIN ∆Σ ADC Modulator SINC2 SINC3 AUTO REFIN− Σ X Offset Calibration Register Gain Calibration Register DDh ADCON1 OCR GCR DEh ADCON2 D3h D2h D1h D6h D5h D4h ADC Result Register Summation Block Σ ADRES DBh(1) DAh D9h SUMR DFh ADCON3 E5h E4h E3h E2h NOTE: (1) For the MSC1202, this register is sign−extended (Bipolar mode) or zero−padded (Unipolar mode) for the 16−bit result in registers DAh and D9h. E1h SSCON Figure 7. MSC1201/02 ADC Structure 21 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ADC INPUT MULTIPLEXER BURNOUT DETECT The input multiplexer provides for any combination of differential inputs to be selected as the input channel, as shown in Figure 8. If AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to six fully differential input channels. It is also possible to switch the polarity of the differential input pair to negate any offset voltages. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the pins. When the Burnout Detect (BOD) bit is set in the ADC control configuration register (ADCON0, SFR DCh), two current sources are enabled. The current source on the positive input channel sources approximately 2µA of current. The current source on the negative input channel sinks approximately 2µA. This allows for the detection of an open circuit (full-scale reading) or short circuit (small differential reading) on the selected input differential pair. The buffer should be on for sensor burnout detection. ADC INPUT BUFFER The analog input impedance is always high, regardless of PGA setting (when the buffer is enabled). With the buffer enabled, the input voltage range is reduced and the analog power-supply current is higher. If the limitation of input voltage range is acceptable, then the buffer is always preferred. AIN0 AIN1 AVDD The input impedance of the MSC1201/02 without the buffer is 7MΩ/PGA. The buffer is controlled by the state of the BUF bit in the ADC control register (ADCON0, SFR DCh). Burnout Detect (2µA) AIN2 ADC ANALOG INPUT AIN3 When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK, SFR F6h) and gain (PGA). The relationship is: In+ Buffer AIN4 In− A IN Impedance (W) + Ǔ ǒACLK1MHz Ǔ @ ǒ7MW Frequency PGA AIN5 AGND where ACLK frequency (f ACLK) + Burnout Detect (2µA) Temperature Sensor AVDD AVDD 80• I and f MOD + I AINCOM f CLK ACLK ) 1 f ACLK . 64 NOTE: The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Figure 9 shows the basic input structure of the MSC1201/02. RSWITCH (3kΩ typical) Figure 8. Input Multiplexer Configuration TEMPERATURE SENSOR On-chip diodes provide temperature sensing capability. When the configuration register for the input mux is set to all 1s, the diodes are connected to the inputs of the ADC. All other channels are open. The internal device power dissipation affects the temperature sensor reading. High Impedance > 1GΩ AIN CS Sampling Frequency = fSAMP PGA f SAMP 1, 2, 4 8 16 32 64, 128 fMOD 2 × fMOD 4 × fMOD 8 × fMOD 16 × f MOD AGND PGA CS 1 2 4 to 128 9pF 18pF 36pF Figure 9. Analog Input Structure (without Buffer) 22 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ADC PGA The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For instance, with a PGA of 1 on a ±2.5V full-scale range (FSR), the ADC can resolve to 1.5µV. With a PGA of 128 on a ±19mV FSR, the ADC can resolve to 75nV. With a PGA of 1 on a ±2.5V FSR, it would require a 26-bit ADC to resolve 75nV, as shown in Table 1. Table 1. ENOB versus PGA (Bipolar Mode) RMS MEASUREMENT RESOLUTION PGA SETTING FULL-SCALE RANGE (V) MSC1201 ENOB AT 10HZ (BITS) MSC1202 ENOB UP TO 200HZ (BITS) MSC1201 (nV) MSC1202 (mV) 1 ±2.5 21.7 16 1468 76.3 2 ±1.25 21.5 15.6 843 38.1 4 ±0.625 21.4 15.5 452 19.1 8 ±0.313 21.2 15.4 259 9.5 16 ±0.156 20.8 15.4 171 4.8 32 ±0.078 20.4 15.3 113 2.4 64 ±0.039 20 15.2 74.5 12 128 ±0.019 19 14.2 74.5 0.6 For system calibration, the appropriate signal must be applied to the inputs. It then computes an offset that will nullify offset in the system. The system gain calibration requires a positive full-scale differential input signal. It then computes a gain value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. Calibration should be performed after power on, a change in temperature, power supply, voltage reference, decimation ratio, buffer, or a change of the PGA. At the completion of calibration, the ADC Interrupt bit goes high, which indicates the calibration is finished and valid data is available. ADC DIGITAL FILTER The Digital Filter can use either the Fast Settling, Sinc2, or Sinc3 filter, as shown in Figure 10. In addition, the Auto mode changes the Sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the Fast Settling filter for the next two conversions, the first of which should be discarded. It will then use the Sinc2 followed by the Sinc3 filter to improve noise performance. This combines the low-noise advantage of the Sinc3 filter with the quick response of the Fast Settling Time filter. The frequency response of each filter is shown in Figure 11. ADC OFFSET DAC The analog output from the PGA can be offset by up to half the full-scale input range of the PGA by using the ODAC register (SFR E6h). The ODAC (Offset DAC) register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Since the ODAC introduces an analog (instead of digital) offset to the PGA, using the ODAC does not reduce the range of the ADC. Adjustable Digital Filter Sinc3 Sinc2 Modulator ADC MODULATOR Fast Settling The modulator is a single-loop 2nd-order system. The modulator runs at a clock speed (fMOD) that is derived from CLK using the value in the Analog Clock register (ACLK, SFR F6h). The data output rate is: Data Rate + f DATA + where f MOD + Data Out f MOD Decimation Ratio f CLK f + ACLK . 64 (ACLK ) 1) @ 64 FILTER SETTLING TIME FILTER Sinc3 Sinc2 Fast SETTLING TIME (Conversion Cycles)(1) 3 2 1 (1) With synchronized channel changes. AUTO MODE FILTER SELECTION ADC CALIBRATION The offset and gain errors in the MSC1201/02, or the complete system, can be reduced with calibration. Calibration is controlled through the ADCON1 register (SFR DDh), bits CAL2:CAL0. Each calibration process takes seven tDATA periods (data conversion time) to complete. Therefore, it takes 14 tDATA periods to complete both an offset and gain calibration. CONVERSION CYCLE 2 3 4+ Discard Fast Sinc2 Sinc3 1 Figure 10. Filter Step Responses 23 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 SINC3 FILTER RESPONSE 0 (−3dB = 0.262 • fDATA) −20 Gain (dB) −40 −60 −80 −100 −120 0 1 2 3 4 5 fDATA SINC2 FILTER RESPONSE 0 (−3dB = 0.318 • fDATA) −20 Gain (dB) −40 The internal voltage reference can be selected as either 1.25V or 2.5V. The analog power supply (AVDD) must be within the specified range for the selected internal voltage reference. The valid ranges are: VREF = 2.5 internal (AVDD = 3.3V to 5.25V) and VREF = 1.25 internal (AVDD = 2.7V to 5.25V). If the internal VREF is selected, then AGND must be connected to REFIN−. The REFOUT/REFIN+ pin should also have a 0.1µF capacitor connected to AGND as close as possible to the pin. If the internal VREF is not used, then VREF should be disabled in ADCON0. If the external voltage reference is selected, it can be used as either a single-ended input or differential input, for ratiometric measures. When using an external reference, it is important to note that the input current will increase for VREF with higher PGA settings and with a higher modulator frequency. The external voltage reference can be used over the input range specified in the electrical characteristics section. IDAC −60 −80 −100 −120 0 1 2 3 4 5 fDATA The 8-bit IDAC in the MSC1201/02 can be used to provide a current source that can be used for ratiometric measurements. The IDAC operates from its own voltage reference and is not dependent on the ADC voltage reference. The full-scale output current of the IDAC is approximately 1mA. The equation for the IDAC output current is: IDAC OUT + IDAC @ 3.6mA FAST SETTLING FILTER RESPONSE 0 (−3dB = 0.469 • fDATA) −20 RESET Gain (dB) −40 Taking the RST pin high stops the operation of the device, and taking the RST pin low initiates a reset. The device can also be reset by the Power On Reset circuitry, Digital Brownout Reset, or Software Reset. The timing of the reset operation is shown in the Electrical Characteristic section. −60 −80 −100 −120 0 1 2 3 4 5 fDATA NOTE: fDATA = Data Output Rate = 1/tDATA Figure 11. Filter Frequency Responses VOLTAGE REFERENCE The MSC1201/02 can use either an internal or external voltage reference. The voltage reference selection is controlled via ADC Control Register 0 (ADCON0, SFR DCh). The default power-up configuration for the voltage reference is 2.5V internal. 24 If pin P1.0/PROG is unconnected or tied high, the device will enter User Application mode (UAM) on reset. If P1.0/PROG is tied low during reset, the device will enter Serial Programming mode. POWER ON RESET The on-chip Power On Reset (POR) circuitry releases the device from reset at approximately DVDD = 2.0V. The POR accommodates power-supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically. Note that, as the device is released from reset and program execution begins, the "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 device current consumption may increase, which may result in a power-supply voltage drop. If the power supply ramps at a slower rate, is not monotonic, or a brownout condition occurs (where the supply does not drop below the 2.0V threshold), then improper device operation may occur. The on-chip Brownout Reset may provide benefit in these conditions. A POR circuit is shown in Figure 12. DVDD 0.1µF 4 ANALOG LOW-VOLTAGE DETECT The MSC1201/02 contain an analog low-voltage detect. When the analog supply drops below the value programmed in LVDCON (SFR E7h), an interrupt is generated. MSC1201/02 10kΩ The DBOR level should be chosen to match closely with the application. That is, with a high external clock frequency, the DBOR level should match the minimum operating voltage range for the device or improper operation may still occur. RST CLOCKS 1MΩ The MSC1201/02 can operate in three separate clock modes: Internal Oscillator mode (IOM), External Clock mode (ECM), and Phase Lock Loop (PLL) mode. A block diagram is shown in Figure 13. The clock mode for the MSC1201/02 is selected via the CLKSEL bits in HCR2. IOM is the default mode for the device. Figure 12. Typical Reset Circuit DIGITAL BROWNOUT RESET The Digital Brownout Reset (DBOR) is enabled through Hardware Configuration Register 1 (HCR1). If the conditions for proper POR are not met or the device encounters a brownout condition that does not generate a POR, the DBOR can be used to ensure proper device operation. The DBOR will hold the state of the device when the power supply drops below the threshold level programmed in HCR1, and then generate a reset when the supply rises above the threshold level. Note that, as the device is released from reset and program execution begins, the device current consumption may increase, which can result in a power supply voltage drop, which may initiate another brownout condition. Also, the DBOR comparison is done against an analog reference; therefore, AVDD must be within its valid operating range for DBOR to function. Serial Flash Programming mode (SFPM) uses IO low-frequency (LF) mode (the HCR2 and CLKSEL bits have no effect). Table 2 shows the active clock mode for the various startup conditions during UAM. Internal Oscillator In IOM, the CPU executes either in LF mode (if HCR2, CLKSEL = 111) or high-frequency (HF) mode (if HCR2, CLKSEL = 110). In this mode, XIN must be grounded or tied to supply. External Clock In ECM (HCR2, CLKSEL = 011), the CPU can execute from an external crystal, external ceramic resonator, external clock, or external oscillator. If an external clock is detected at startup, then the CPU will begin execution in ECM after startup. If an external clock is not detected at startup, then the device will revert to the mode shown in Table 2. tOSC STOP XIN (1) XOUT Phase Detector Charge Pump LF/HF Internal Mode Oscillator 100kΩ tPLL/tIOM tSYS VCO tCLK SYSCLK PLL DAC PLLDIV NOTE: (1) Disabled in PLL mode; therefore, an external resistor between XIN and XOUT is required. Figure 13. Clock Block Diagram 25 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Table 2. Active Clock Modes STARTUP CONDITION(1) ACTIVE CLOCK MODE (fSYS) Active clock present at XIN External Clock Mode No clock present at XIN IO LF Mode IO LF Mode N/A IO LF Mode IO HF Mode N/A IO HF Mode Active 32.768kHz clock at XIN PLL LF Mode No clock present at XIN Nominal 50% of IO LF Mode Active 32.768kHz clock at XIN PLL HF Mode No clock present at XIN Nominal 50% of IO HF Mode SELECTED CLOCK MODE (HCR2, CLKCON2:0) External Clock Mode (ECM) Internal Oscillator Mode (IOM)(2) PLL LF Mode PLL(3) PLL HF Mode (1) Clock detection is only done at startup; refer to Electrical Characteristics parameter tRFD in Figure 2. (2) XIN must not be left floating; it must be tied high or low. (3) PLL operation requires that both AVDD and DVDD are within their specified ranges. PLL XIN In PLL mode (HCR2, CLKSEL = 101 or HCR2, CLKSEL = 100), the CPU can execute from an external 32.768kHz crystal. This mode enables the use of a PLL circuit that synthesizes the selected clock frequencies (PLL LF mode or PLL HF mode). If an external clock is detected at startup, then the CPU will begin execution in PLL mode after startup. If an external clock is not detected at startup, then the device will revert to the mode shown in Table 2. The status of the PLL can be determined by first writing the PLLLOCK bit (enable) and then reading the PLLLOCK status bit in the PLLH SFR. C1 XOUT C2 NOTE: Refer to the crystal manufacturer’s specification for C1 and C2 values. Figure 14. External Crystal Connection The frequency of the PLL is preloaded with default trimmed values. However, the PLL frequency can be fine-tuned by writing to the PLLDIV1 and PLLDIV0 SFRs. The equation for the PLL frequency is: External Clock XIN PLL Frequency = ((PLLDIV9:PLLDIV0) + 1) • fOSC where fOSC = 32.768kHz. Figure 15. External Clock Connection The default value for PLL LF mode is automatically loaded into the PLLDIV SFR. For PLL HF mode, PLLDIV must be loaded with the appropriate value. For different connections to external clocks, see Figure 14, Figure 15, and Figure 16. XIN 32pF 32.768kHz 5MΩ XOUT 32pF NOTE: Typical configuration is shown. Figure 16. PLL Connection 26 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 D Toggle SCK by setting and clearing the port pin. D Memory Write Pulse (WR) that is idle high. SPI The MSC1201/02 implement a basic SPI interface that includes the hardware for simple serial data transfers. Figure 17 shows a block diagram of the SPI. The peripheral supports master and slave modes, full duplex data transfers, both clock polarities, both clock phases, bit order, and slave select. Whenever an external memory write command (MOVX) is executed, a pulse is seen on P3.6. This method can be used only if CPOL is set to ‘1’. D Memory Write Pulse toggle version. In this mode, SCK toggles whenever an external write command (MOVX) is executed. The timing diagram for supported SPI data transfers is shown in Figure 18. D T0_Out signal can be used as a clock. A pulse is The I/O pins needed for data transfer are Data In (DIN), Data Out (DOUT) and serial clock (SCK). The slave select (SS) pin can also be used to control the output of data on DOUT. generated on SCK whenever Timer 0 expires. The idle state of the signal is low, so this can be used only if CPOL is cleared to ‘0’. D T0_Out toggle. SCK toggles whenever Timer 0 The DIN pin is used for shifting data in for both master and slave modes. expires. D T1_Out signal can be used as a clock. A pulse is The DOUT pin is used for shifting data out for both master and slave modes. generated whenever Timer 1 expires. The idle state of the signal is low, so this can be used only if CPOL is cleared to ‘0’. The SCK pin is used to synchronize the transfer of data for both master and slave modes. SCK is always generated by the master. The generation of SCK in master mode can be done either in software by simply toggling the port pin, or by configuring the output on the SCK pin via PASEL (SFR F2h). A list of the most common methods of generating SCK follows, but the complete list of clock sources can be found by referring to the PASEL SFR. D T1_Out toggle. SCK toggles whenever Timer 1 expires. DOUT SPI /I 2C Data Write P1.2 DOUT TX_CLK SPICON I2CCON SS P1.4 CNT_CLK CNT INT Counter I2C INT Start/Stop Detect SS Logic SCK/SCL Pad Control P3.6 SCK I 2C Stretch Control P1.3 RX_CLK DIN SPI /I2C Data Read DIN CLKS (refer to PASEL, SFR F2h) Figure 17. SPI/I2C Block Diagram 27 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 SCK Cycle # 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) Sample Input MSB 6 5 4 3 2 1 LSB (CPHA = 0) Data Out Sample Input MSB 6 5 4 3 2 1 LSB (CPHA = 1) Data Out SS to Slave Slave CPHA = 1 Transfer in Progress 2 1) SS Asserted 1 2) First SCK Edge 3) CNTIF Set (dependent on CPHA bit) 4) SS Negated Slave CPHA = 0 Transfer in Progress 3 4 Figure 18. SPI Timing Diagram The SS pin can be used to control the output of data on DOUT when the MSC1201/02 is in slave mode. The SS function is enabled or disabled by the ESS bit of the SPICON SFR. When enabled, the SS input of a slave device must be externally asserted before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. When SS is high, data will not be shifted into the shift register nor will the counter increment. When SPI is enabled, SS also controls the drive of the line DOUT (P1.2). When SS is low in slave mode, the DOUT pin will be driven and when SS is high, DOUT will be high impedance. The SPI generates interrupt ECNT (AIE.2) to indicate that the transfer/reception of the byte is complete. The interrupt goes high whenever the counter value is equal to 8 (indicating that eight SCKs have occurred). The interrupt is cleared on reading or writing to the SPIDATA register. During the data transfer, the actual counter value can be read from the SPICON SFR. Power Down The SPI is powered down by the PDSPI bit in the power control register (PDCON). This bit needs to be cleared to enable the SPI function. When the SPI is powered down, pins P1.2, P1.3, P1.4, and P3.6 revert to general-purpose I/O pins. 28 Application Flow This section explains the typical application usage flow of SPI in master and slave modes. Master Mode Application Flow 1. Configure the port pins. 2. Configure the SPI. 3. Assert SS to enable slave communication (if applicable). 4. Write data to SPIDATA. 5. Generate eight SCKs. 6. Read the received data from SPIDATA. Slave Mode Application Flow 1. Configure the ports pins. 2. Enable SS (if applicable). 3. Configure the SPI. 4. Write data to SPIDATA. 5. Wait for the Count Interrupt (eight SCKs). 6. Read the data from SPIDATA. CAUTION: If SPIDATA is not read before the next SPI transaction, the ECNT interrupt will be removed and the previous data will be lost. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 I2C The I/O pins needed for I2C transfer are serial clock (SCL) and serial data (SDA—implemented by connecting DIN and DOUT externally). The I2C transfer timing is shown in Figure 19. The MSC1201/02 I2C supports: 1. Master or slave I2C operation (control in software) 2. Standard or fast modes of transfer 3. Clock stretching 4. General call When used in I2C mode, pins DIN (P1.3) and DOUT (P1.2) should be tied together externally. The DIN pin should be configured as an input pin and the DOUT pin should be configured as open drain or standard 8051 by setting the P1DDR (DOUT should be set high so that the bus is not pulled low). The MSC1201/02 I2 C can generate two interrupts: 1. I2C interrupt for START/STOP interrupt (AIE.3) 2. CNT interrupt for bit counter interrupt (AIE.2) The START/STOP interrupt is generated when a START condition or STOP condition is detected on the bus. The bit counter generates an interrupt on a complete (8-bit) data transfer and also after the transfer of the ACK/NACK. The bit counter for serial transfer is always incremented on the falling edge of SCL and can be reset by reading or writing to I2CDATA (SFR 9Bh) or when a START/STOP condition is detected. The bit counter can be polled or used as an interrupt. The bit counter interrupt occurs when the bit counter value is equal to 8, indicating that eight bits of data have been transferred. I2C mode also allows for interrupt generation on one bit of data transfer (I2CCON.CNTSEL). This can be used for ACK/NACK interrupt generation. For instance, the I2C interrupt can be configured for 8-bit interrupt detection; on the eighth bit, the interrupt is generated. Following this interrupt, the clock is stretched (SCL held low). The interrupt can then be configured for 1-bit detection, which will terminate clock stretching. The ACK/NACK can be written by the software, which will terminate clock stretching. The next interrupt will be generated after the ACK/NACK has been latched by the receiving device. The interrupt is cleared on reading or writing to the I2CDATA register. If I2CDATA is not read before the next data transfer, the interrupt will be removed and the previous data will be lost. Master Operation The source for the SCL is controlled in the PASEL register or can be generated in software. Transmit The serial data must be stable on the bus while SCL is high. Therefore, the writing of serial data to I2CDATA must be coordinated with the generation of the SCL, since SDA transitions on the bus may be interpreted as a START or STOP while SCL is high. The START and STOP conditions on the bus must be generated in software. After the serial data has been transmitted, the generation of the ACK/NACK clock must be enabled by writing 0xFFh to I2CDATA. This allows the master to read the state of ACK/NACK. Receive The serial data is latched into the receive buffer on the rising edge of SCL. After the serial data has been received, ACK/NACK is generated by writing 0x7Fh (for ACK) or 0xFFh (for NACK) to I2CDATA. SDA 1−7 SCL 8 9 1−7 8 9 1−7 8 9 S P START ADDRESS(2) Condition(1) R/W(2) ACK(3) DATA(2) ACK(3) DATA(2) ACK(3) STOP Condition(4) NOTES: (1) Generate in software; write 0x7F to I2CDATA. (2) I2CDATA register. (3) Generate in software. Can enable bit count = 1 interrupt prior to ACK/NACK for interrupt use. Generate ACK by writing 0x7F to I2CDATA; generate NACK by writing 0xFF to I2CDATA. (4) Generate in software; write 0xFF to I2CDATA. Figure 19. Timing Diagram for I2C Transmission and Reception 29 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Slave Operation Slave operation is supported, but address recognition, R/W determination, and ACK/NACK must be done under software control. The Disable Clock Stretch (DCS) bit can be set to disable clock stretching. When the DCS bit is set, the device will no longer stretch the clock and will not generate interrupts. This bit can be used to disable clock stretch interrupts when there is no address match. This bit is automatically cleared when a start or repeated start condition occurs. Transmit Once address recognition, R/W determination, and ACK/NACK are complete, the serial data to be transferred can be written to I2CDATA. The data is automatically shifted out based on the master SCL. After data transmission, CNTIF is generated and SCL is stretched by the MSC1201/02 until the I2CDATA register is written with a 0xFFh. The ACK/NACK from the master can then be read. Receive Once address recognition, R/W determination, and ACK/NACK are complete, I2CDATA must be written with 0xFFh to enable data reception. Upon completion of the data shift, the MSC1201/02 generates the CNT interrupt and stretches SCL. Received data can then be read from I2CDATA. After the serial data has been received, ACK/NACK is generated by writing 0x7Fh (for ACK) or 0xFFh (for NACK) to I2CDATA. The write to I2CDATA clears the CNT interrupt and clock stretch. MEMORY MAP The MSC1201/02 contain on-chip SFR, Flash Memory, Scratchpad SRAM Memory, and Boot ROM. The SFR registers are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1201/02 are controlled through the SFR. Reading from an undefined SFR will return zero. Writing to undefined SFR registers is not recommended and will have indeterminate effects. Flash Memory is used for both Program Memory and Data Memory. Program/Data Memory partition size is selectable. The partition size is set through hardware configuration bits, which are programmed serially. Both Program and Data Flash Memories are erasable and writable (programmable) in User Application mode. However, program execution can only occur from Program Memory. As an added precaution, a lock feature can be 30 activated through the hardware configuration bits, which disables erase/write operation to 4kB of Program Flash Memory or the entire Program Flash Memory in User Application mode. FLASH MEMORY The MSC1201/02 use a memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). The program and data segments can overlap since they are accessed by different instructions. Program Memory is fetched by the microcontroller automatically. MOVC is the one instruction that is used to explicitly read the program area, and is commonly used to read lookup tables. The MSC1201/02 have three Hardware (HW) Configuration registers (HCR0, HCR1, and HCR2) that are programmable only during Flash Memory Programming mode. The MSC1201/02 allow the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1201Y3/MSC1202Y3 contain 8kB of Flash Memory on-chip. Through the HW configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Table 3, Table 4, and Figure 20. The MSC1201/02 families offer two memory configurations. Table 3. Flash Memory Partitioning HCR0 MSC1201/02Y2 MSC1201/02Y3 DFSEL PM DM PM DM 00 2kB 2kB 4kB 4kB 01 2kB 2kB 6kB 2kB 10 3kB 1kB 7kB 1kB 11 (default) 4kB 0kB 8kB 0kB Table 4. Flash Memory Partitioning Addresses HCR0 MSC1201/02Y2 MSC1201/02Y3 DFSEL PM DM PM DM 00 0000−07FF 0400−0BFF 0000−0FFF 0400−13FF 01 0000−07FF 0400−0BFF 0000−17FF 0400−0BFF 10 0000−0BFF 0400−07FF 0000−1BFF 0400−07FF 11 (default) 0000−0FFF 0000 0000−1FFF 0000 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Program Memory Data Memory FFFFh FFFFh Select in HCR0 Unused FC00h 1K Internal Boot ROM System Memory F800h Unused 7Fh Unused UAM: Read Only SFPM: Read Only 40h 2000h, 8k (Y3) On−Chip Flash 1400h, 5k (Y3) 1000h, 4k (Y2) 0000h, 0k On−Chip Flash 0C00h, 3k (Y2) 0400h, 1k UAM: Read Only SFPM: ReadWrite 00h Figure 20. Memory Map It is important to note that the Flash Memory is readable and writable (depending on the MXWS bit in the MWS SFR) by the user through the MOVX instruction when configured as either Program or Data Memory. This means that the user may partition the device for maximum Flash Program Memory size (no Flash Data Memory) and use Flash Program Memory as Flash Data Memory. This may lead to undesirable behavior if the PC points to an area of Flash Program Memory that is being used for data storage. Therefore, it is recommended to use Flash partitioning when Flash Memory is used for data storage. Flash partitioning prohibits execution of code from Data Flash Memory. Additionally, the Program Memory erase/write can be disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) to Data Flash Memory. The effect of memory mapping on Program and Data Memory is straightforward. The Program Memory is decreased in size from the top of Flash Memory. To maintain compatibility with the MSC121x, the Flash Data Memory maps to addresses 0400h. Therefore, access to Data Memory (through MOVX) will access Flash Memory for the addresses shown in Table 4. Data Memory The MSC1201/02 has on-chip Flash Data Memory, which is readable and writable (depending on Memory Write Select register) during normal operation (full VDD range). This memory is mapped into the external Data Memory space, which requires the use of the MOVX instruction to program. Note that the page size is 64 bytes for both Program and Data Memory and the page must be erased before it can be written. System Memory The System Memory is nonvolatile memory that can be read in User Application mode through the faddr_data_read Boot ROM routine. In Serial Flash Programming mode, the lower 64 bytes can be written. The lower 64 bytes include the Hardware Configuration registers. 31 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 The Register Map is illustrated in Figure 21. It is entirely separate from the Program and Data Memory areas mentioned before. A separate class of instructions is used to access the registers. There are 256 potential register locations. In practice, the MSC1201/02 have 256 bytes of Scratchpad RAM and up to 128 SFRs. This is possible, since the upper 128 Scratchpad RAM locations can only be accessed indirectly. Thus, a direct reference to one of the upper 128 locations must be an SFR access. Direct RAM is reached at locations 0 to 7Fh (0 to 127). 255 FFh 255 Indirect RAM 128 127 80h 128 7Fh Direct RAM 0 FFh Direct Special Function Registers 80h SFR Registers 00h Scratchpad RAM Figure 21. Register Map SFRs are accessed directly between 80h and FFh (128 to 255). The RAM locations between 128 and 255 can be reached through an indirect reference to those locations. Scratchpad RAM is available for general-purpose data storage. Within the 128 bytes of RAM, there are several special-purpose areas. Word register (PSW; 0D0h) in the SFR area described below. The 16 bytes immediately above the R0−R7 registers are bit-addressable, so any of the 128 bits in this area can be directly accessed using bit-addressable instructions. 7Fh Direct RAM 2Fh 7F 7E 7D 7C 7B 7A 79 78 2Eh 77 76 75 74 73 72 71 70 2Dh 6F 6E 6D 6C 6B 6A 69 68 2Ch 67 66 65 64 63 62 61 60 2Bh 5F 5E 5D 5C 5B 5A 59 58 2Ah 57 56 55 54 53 52 51 50 29h 4F 4E 4D 4C 4B 4A 49 48 28h 47 46 45 44 43 42 41 40 27h 3F 3E 3D 3C 3B 3A 39 38 26h 37 36 35 34 33 32 31 30 25h 2F 2E 2D 2C 2B 2A 29 28 24h 27 26 25 24 23 22 21 20 23h 1F 1E 1D 1C 1B 1A 19 18 22h 17 16 15 14 13 12 11 10 21h 0F 0E 0D 0C 0B 0A 09 08 20h 07 06 05 04 03 02 01 00 Bit Addressable REGISTER MAP 1Fh Bit Addressable Locations In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM and SFR area. In the Scratchpad RAM area, registers 20h to 2Fh are bit-addressable. This provides 128 (16 • 8) individual bits available to software. A bit access is distinguished from a full-register access by the type of instruction. In the SFR area, any register location ending in a 0h or 8h is bit-addressable. Figure 22 shows details of the on-chip RAM addressing including the locations of individual RAM bits. Bank 3 18h 17h Bank 2 10h 0Fh Bank 1 08h 07h Bank 0 00h MSB LSB Working Registers As part of the lower 128 bytes of RAM, there are four banks of Working Registers, as shown in Figure 20. The Working Registers are general-purpose RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently selected bank will be used by any instruction using R0−R7. This allows software to change context by simply switching banks. This is controlled via the Program Status 32 Figure 22. Scratchpad Register Addressing Thus, an instruction can designate the value stored in R0 (for example) to address the upper RAM. The 16 bytes immediately above the these registers are bit-addressable, so any of the 128 bits in this area can be directly accessed using bit-addressable instructions. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Stack Another use of the Scratchpad area is for the programmer’s stack. This area is selected using the Stack Pointer (SP, SFR 81h). Whenever a call or interrupt is invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the Stack can be moved and there is no fixed location within the RAM designated as Stack. The Stack Pointer defaults to 07h on reset and the user can then move it as needed. The SP will point to the last used value. Therefore, the next value placed on the Stack is put at SP + 1. Each PUSH or CALL increments the SP by the appropriate value and each POP or RET decrements it. Program Memory After reset, the CPU begins execution from Program Memory location 0000h. The standard internal Program Memory size for MSC1201/02 family members is shown in Table 5. If enabled, the Boot ROM will appear from address F800h to FFFFh. Table 5. MSC1201/02 Maximum Internal Program Memory Sizes MODEL NUMBER STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES) MSC1201Y2/MSC1202Y2 8k MSC1201Y3/MSC1202Y3 4k Boot ROM There is a 1kB Boot ROM that controls operation during serial programming. Additionally, the Boot ROM routines shown in Table 6 can be accessed during the user mode, if it is enabled. When enabled, the Boot ROM routines will be located at memory addresses F800h−FBFFh during user mode. Table 6. MSC1201/02 Boot ROM Routines HEX ADDRESS ROUTINE C DECLARATIONS DESCRIPTION F802 sfr_rd char sfr_rd(void); Return SFR value pointed to by CADDR(1) F805 sfr_wr void sfr_wr(char d); Write to SFR pointed to by CADDR(1) FBD8 monitor_isr void monitor_isr() interrupt 6; Push registers and call cmd_parser FBDA cmd_parser void cmd_parser(void); See application note SBAA076, Programming the MSC1210, available at www.ti.com. FBDC put_string void put_string(char code *string); Output string FBDE page_erase char page_erase(int faddr, char fdata, char fdm); Erase flash page FBE0 write_flash Assembly only; DPTR = address, ACC = data Flash write(2) FBE2 write_flash_chk char write_flash_chk(int faddr, char fdata, char fdm); Write flash byte, verify FBE4 write_flash_byte void write_flash_byte(int faddr, char fdata); Write flash byte(2) FBE6 faddr_data_read char faddr_data_read(char faddr); Read System Memory byte from faddr FBE8 data_x_c_read char data_x_c_read(int faddr, char fdm); Read xdata or code byte FBEA tx_byte void tx_byte(char); Send byte to USART0 FBEC tx_hex void tx_hex(char); send hex value to USART0 FBEE putx void putx(void); send “x” to USART0 on R7 = 1 FBF0 rx_byte char rx_byte(void); Read byte from USART0 FBF2 rx_byte_echo char rx_byte_echo(void); Read and echo byte on USART0 FBF4 rx_hex_echo char rx_hex_echo(void); Read and echo hex on USART0 FBF6 rx_hex_dbl_echo int_rx_hex_dbl_echo(void); Read int as hex and echo: USART0 FBF8 rx_hex_word_echo int_rx_hex_word_echo(void); Read int reversed as hex and echo: USART0 FBFA autobaud void autobaud(void); Set baud with received CR(3) FBFC putspace1 void putspace1(void); Output 1 space to USART0 FBFE putcr void putcr(void); Output CR, LF to USART0 (1) CADDR must be set using the faddr_data_read routine. (2) MWS register (SFR 8Fh) defines Data Memory or Program Memory write. (3) SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00. 33 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Serial Flash Programming Mode INTERRUPTS Serial Flash Programming mode is initiated by holding the P1.0/PROG pin low during reset, as shown in Figure 23. User Application mode also allows for Flash programming. Code execution from Flash Memory cannot occur in this mode while programming, but code execution can occur from Boot ROM while programming. The MSC1201/02 use a three-priority interrupt system. As shown in Table 7, each interrupt source has an independent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxiliary Interrupt, AI, at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the original 8051 family. All of the standard interrupts are available. MSC1201/02 P3.0/RxD0 P3.1/TxD0 HARDWARE CONFIGURATION MEMORY Programmer The 64 configuration bytes can only be written during the program mode. The bytes are accessed through SFR registers CADDR (SFR 93h) and CDATA (SFR 94h) by using the faddr_data_read Boot-ROM routine. Three of the configuration bytes control Flash partitioning and system control. If the security bit is set, these bits cannot be changed except with a Mass Erase command that erases all of the Flash Memory, including the 64 configuration bytes. RST P1.0/PROG NOTE: For User Application mode, avoid heavy loading on P1.0/PROG, which can result in erroneously entering Serial Flash Programming mode on power− up. Figure 23. Serial Flash Programming Mode Table 7. Interrupt Summary INTERRUPT ADDR NUM PRIORITY FLAG ENABLE PRIORITY CONTROL AVDD Low Voltage Detect 33h 6 HIGH 0 ALVDIP (AIPOL.1)(1) EALV (AIE.1)(1) N/A Count (SPI/I2C) 33h 6 0 CNTIP (AIPOL.2)(1) ECNT (AIE.2)(1) N/A (AIPOL.3)(1) EI2C (AIE.3)(1) N/A EMSEC (AIE.4)(1) N/A INTERRUPT/EVENT I2C Start/Stop 33h 6 0 Milliseconds Timer 33h 6 0 I2CIP MSECIP (AIPOL.4)(1) (AIPOL.5)(1) N/A ADC 33h 6 0 ADCIP Summation Register 33h 6 0 SUMIP (AIPOL.6)(1) ESUM (AIE.6)(1) N/A Seconds Timer 33h 6 0 SECIP (AIPOL.7)(1) ESEC (AIE.7)(1) N/A (TCON.1)(2) EADC (AIE.5)(1) EX0 (IE.0)(4) PX0 (IP.0) External Interrupt 0 03h 0 1 IE0 Timer 0 Overflow 0Bh 1 2 TF0 (TCON.5)(3) ET1 (IE.1)(4) PT0 (IP.1) (TCON.3)(2) (IE.2)(4) PX1 (IP.2) External Interrupt 1 13h 2 3 IE1 Timer 1 Overflow 1Bh 3 4 TF1 (TCON.7)(3) EX1 ET1 (IE.3)(4) PT1 (IP.3) ES0 (IE.4)(4) PS0 (IP.4) Serial Port 0 23h 4 5 RI_0 (SCON0.0) TI_0 (SCON0.1) External Interrupt 2 43h 8 6 IE2 (EXIF.4) EX2 (EIE.0)(4) PX2 (EIP.0) (EIE.1)(4) PX3 (EIP.1) External Interrupt 3 4Bh 9 7 IE3 (EXIF.5) EX3 External Interrupt 4 53h 10 8 IE4 (EXIF.6) EX4 (EIE.2)(4) PX4 (EIP.2) External Interrupt 5 5Bh 11 9 IE5 (EXIF.7) EX5 (EIE.3)(4) PX5 (EIP.3) Watchdog 63h 12 10 LOW WDTI (EICON.3) EWDI (EIE.4)(4) PWDI (EIP.4) (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge-triggered, cleared automatically by hardware when the service routine is vectored to. If level-triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs. (4) Globally enabled by EA (IE.7). 34 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. CADDR 3Fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR 1 DFSEL1 DFSEL0 EPMA bit 7 Enable Programming Memory Access (Security Bit). 0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done. 1: Fully Accessible (default) PML bit 6 Program Memory Lock (PML has Priority Over RSL). 0: Enable read and write for Program Memory in UAM. 1: Enable Read-Only mode for Program Memory in UAM (default). RSL bit 5 Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming. This will allow Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. 0: Enable Reset Sector Writing 1: Enable Read-Only mode for reset sector (4kB) (default). Same effect as PML for the MSC1201Y2/MSC1202Y2. EBR bit 4 Enable Boot ROM. Boot ROM is 1kB of code located in ROM, not to be confused with the 4kB Boot Sector located in Flash Memory. 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR bit 3 Enable Watchdog Reset. 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL1−0 Data Flash Memory Size (See Table 3). bits 1−0 00: 4kB Data Flash Memory (MSC1201Y3/MSC1202Y3 Only) 01: 2kB Data Flash Memory 10: 1kB Data Flash Memory 11: No Data Flash Memory (default) 35 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Hardware Configuration Register 1 (HCR1) CADDR 3Eh DDB bit 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 1 1 1 DDB 1 1 Disable Digital Brownout Detection. 0: Enable Digital Brownout Detection (2.7V) 1: Disable Digital Brownout Detection (default) Hardware Configuration Register 2 (HCR2) CADDR 3Dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 CLKSEL2 CLKSEL1 CLKSEL0 CLKSEL2−1 Clock Select. bits 2−0 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode 101: PLL Low-Frequency (LF) Mode 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode 36 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 SFR DEFINITIONS ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE 80h 81h SP 07h 82h DPL0 00h 83h DPH0 00h 84h DPL1 00h 85h DPH1 86h DPS 0 0 0 0 0 0 0 SEL 00h 87h PCON SMOD 0 1 1 GF1 GF0 STOP IDLE 30h 88h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h 00h TMOD 89h −−−−−−−−−−−−−−− Timer 1 −−−−−−−−−−−−−−− GATE C/T M1 M0 −−−−−−−−−−−−−−− Timer 0 −−−−−−−−−−−−−−− GATE C/T M1 M0 00h 8Ah TL0 00h 8Bh TL1 00h 8Ch TH0 00h 8Dh TH1 00h 8Eh CKCON 0 0 0 T1M T0M MD2 MD1 MD0 01h 8Fh MWS 0 0 0 0 0 0 0 MXWS 00h P1 P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 DIN P1.2 DOUT P1.1 P1.0 PROG FFh 91h EXIF IE5 IE4 IE3 IE2 1 0 0 0 08h 92h MPAGE 93h CADDR 00h 94h CDATA 00h 90h 95h 96h 97h 98h SCON0 99h SBUF0 9Ah SPICON I2CCON 9Bh SPIDATA I2CDATA SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h 00h SBIT3 SBIT3 SBIT2 SBIT2 SBIT1 SBIT1 SBIT0 SBIT0 ORDER STOP CPHA START ESS DCS CPOL CNTSEL 00h 00h 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h AIPOL SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP 0 00h A5h PAI 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h A6h AIE ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00h A7h AISTAT SEC SUM ADC MSEC I2C CNT ALVD 0 00h A8h IE EA 0 0 ES0 ET1 EX1 ET0 EX0 00h A9h 37 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 SFR DEFINITIONS (continued) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE AEh P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00h AFh P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00h P3 P3.7 P3.6 SCK/SCL/CLKS P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh AAh ABh ACh ADh B0h B1h B2h B3h P3DDRL P33H P33L P32H P32L P31H P31L P30H P30L 00h B4h P3DDRH P37H P37L P36H P36L P35H P35L P34H P34L 00h B5h IDAC 00h B6h B7h B8h IP 1 0 0 PS0 PT1 PX1 PT0 PX0 80h EWUWDT EWUEX1 EWUEX0 00h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h EWU C7h SYSCLK 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h D0h PSW CY AC F0 RS1 RS0 OV F1 P 00h D1h OCL LSB 00h D2h OCM D3h OCH D4h GCL D5h GCM D6h GCH C8h C9h CAh CBh CCh CDh CEh CFh 38 00h MSB 00h LSB 5Ah ECh MSB 5Fh "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 SFR DEFINITIONS (continued) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE D7h ADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h D8h EICON 0 1 EAI AI WDTI 0 0 0 40h D9h ADRESL(1) LSB(1) 00h DAh ADRESM(1) MSB(1) 00h DBh ADRESH(1) MSB(1) 00h DCh ADCON0 BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 DDh ADCON1 OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 00h DEh ADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DFh ADCON3 0 0 0 0 0 DR10 DR9 DR8 06h E0h ACC ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h E1h SSCON SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h E2h SUMR0 LSB 00h E3h SUMR1 E4h SUMR2 E5h SUMR3 E6h ODAC E7h LVDCON ALVDIS 0 0 0 1 1 1 1 8Fh E8h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h E9h HWPC0 0 0 0 0 0 0 DEVICE MEMORY EAh HWPC1 0 0 1 0 0 0 0 0 EBh HWVER ECh Reserved EDh Reserved EEh FMCON 0 PGERA 0 FRCM 0 BUSY 1 0 02h EFh FTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h F0h B F1h PDCON PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDST PDSPI 6Fh F2h PASEL PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00h F3h Reserved F4h PLLL PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 xxh(2) F5h PLLH CKSTAT2 CKSTAT1 CKSTAT0 PLLLOCK 0 0 PLL9 PLL8 xxh(2) F6h ACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h F7h SRST 0 0 0 0 0 0 0 RSTREQ 00h F8h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h F9h SECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh FAh MSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh FBh USEC 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FCh MSECL MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9Fh FDh MSECH MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh FEh HMSEC HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h FFh WDTCON EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h 30h 00h 00h MSB 00h 00h 0000_00xxb 20h 00h (1) For the MSC1201, the ADC result is contained in ADRESH, ADRESM, and ADRESL. For the MSC1202, the ADC result is contained in ADRESM and ADRESL (that is, shifted right one byte) and the MSB is sign-extended (Bipolar mode) or zero-padded (Unipolar mode) in ADRESH. Therefore, when migrating between the MSC1201 and MSC1202, the ADC result calculation must be adjusted accordingly. For both the MSC1201 and MSC1202, the ADC interrupt is cleared by reading ADRESL. (2) Dependent on HCR2 value. 39 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Stack Pointer (SP) SFR 81h SP.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 07h Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h after reset. Data Pointer Low 0 (DPL0) SFR 82h DPL0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 00h Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer High 0 (DPH0) SFR 83h DPH0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 00h Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer Low 1 (DPL1) SFR 84h DPL1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 00h Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer High 1 (DPH1) SFR 85h DPH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 00h Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer Select (DPS) SFR 86h SEL bit 0 40 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 SEL 00h Data Pointer Select. This bit selects the active data pointer. 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Power Control (PCON) SFR 87h 7 6 5 4 3 2 1 0 Reset Value SMOD 0 1 1 GF1 GF0 STOP IDLE 30h SMOD bit 7 Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. GF1 bit 3 General-Purpose User Flag 1. This is a general-purpose flag for software control. GF0 bit 2 General-Purpose User Flag 0. This is a general-purpose flag for software control. STOP bit 1 Stop Mode Select. Setting this bit will halt the internal oscillator and block external clocks. This bit will always read as 0. Exit with RESET. In this mode, internal peripherals are frozen and I/O pins are held in their current state. The ADC is frozen, but IDAC and VREF remain active. IDLE bit 0 Idle Mode Select. Setting this bit will freeze the CPU, Timer 0 and 1, and the USART; other peripherals remain active. This bit will always be read as a 0. Exit with AIE (A6h) and EWU (C6h) interrupts (refer to Figure 6 for clocks affected during IDLE). Timer/Counter Control (TCON) SFR 88h 7 6 5 4 3 2 1 0 Reset Value TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TF1 bit 7 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 bit 6 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current bit 6 count in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 bit 5 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 bit 4 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the current count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 bit 3 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 bit 2 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge- or level-triggered interrupts. 0: INT1 is level triggered. 1: INT1 is edge triggered. IE0 bit 1 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 bit 0 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge- or level-triggered interrupts. 0: INT0 is level triggered. 1: INT0 is edge triggered. 41 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Timer Mode Control (TMOD) 7 SFR 89h 6 5 4 3 2 TIMER 1 GATE C/T 1 0 M1 M0 TIMER 0 M1 M0 GATE C/T GATE bit 7 Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T bit 6 Timer 1 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1. M1, M0 bits 5−4 Timer 1 Mode Select. These bits select the operating mode of Timer 1. M1 M0 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Timer 1 is halted, but holds its count. Reset Value 00h MODE GATE bit 3 Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T bit 2 Timer 0 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1. M1, M0 bits 1−0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. M1 M0 0 0 MODE Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. Timer 0 LSB (TL0) SFR 8Ah TL0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 00h Timer 0 LSB. This register contains the least significant byte of Timer 0. Timer 1 LSB (TL1) SFR 8Bh TL1.7−0 bits 7−0 42 7 6 5 4 3 2 1 0 Reset Value TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 00h Timer 1 LSB. This register contains the least significant byte of Timer 1. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Timer 0 MSB (TH0) SFR 8Ch TH0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h Timer 0 MSB. This register contains the most significant byte of Timer 0. Timer 1 MSB (TH1) SFR 8Dh TH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h Timer 1 MSB. This register contains the most significant byte of Timer 1. Clock Control (CKCON) SFR 8Eh 7 6 5 4 3 2 1 0 Reset Value 0 0 0 T1M T0M MD2 MD1 MD0 01h T1M bit 4 Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide-by-12 of the crystal frequency. 1: Timer 1 uses a divide-by-4 of the crystal frequency. T0M bit 3 Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide-by-12 of the crystal frequency. 1: Timer 0 uses a divide-by-4 of the crystal frequency. MD2, MD1, MD0 bits 2−0 Stretch MOVX Select. These bits select the time by which external MOVX cycles are to be stretched. Since the MSC1201/02 does not allow external memory access, these bits should be set to 000B to allow for the fastest Flash Data Memory access. Memory Write Select (MWS) SFR 8Fh MXWS bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 MXWS 00h MOVX Write Select. This allows writing to the internal Flash Program Memory. 0: No writes are allowed to the internal Flash Program Memory. 1: Writing is allowed to the internal Flash Program Memory, unless PML or RSL (HCR0, CADDR 3Fh) are on. 43 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Port 1 (P1) SFR 90h 7 6 5 4 3 2 1 0 Reset Value P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 DIN P1.2 DOUT P1.1 P1.0 PROG FFh P1.7−0 bits 7−0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEh), P1DDRH (SFR AFh). INT5 bit 7 External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled. INT4 bit 6 External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. INT3 bit 5 External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled. INT2/SS bit 4 External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. This pin can be used as slave select (SS) in SPI slave mode. DIN bit 3 Serial Data In. This pin receives serial data in SPI and I2C modes (in I2C mode, this pin should be configured as an input) or standard 8051. DOUT bit 2 Serial Data Out. This pin transmits serial data in SPI and I2C modes (in I2C mode, this pin should be configured as an open drain) or standard 8051. PROG bit 0 Program Mode. When this pin is pulled low at power-up, the device enters Serial Programming mode (refer to Figure 2). External Interrupt Flag (EXIF) SFR 91h 7 6 5 4 3 2 1 0 Reset Value IE5 IE4 IE3 IE2 1 0 0 0 08h IE5 bit 7 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 bit 6 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE3 bit 5 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE2 bit 4 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. 44 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Configuration Address Register (CADDR) (write-only) 7 6 5 4 3 2 1 0 SFR 93h CADDR bits 7−0 Reset Value 00h Configuration Address Register. This register supplies the address for reading bytes in the 64 bytes of Flash Configuration Memory. Always use the Boot ROM CADDR access routine (faddr_data_read). This register is also used for SFR read and write routines. CAUTION: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect. Configuration Data Register (CDATA) (read-only) 7 6 5 4 3 2 1 0 SFR 94h CDATA bits 7−0 Reset Value 00h Configuration Data Register. This register will contain the data in the 64 bytes of Flash Configuration Memory that is located at the last written address in the CADDR register. This is a read-only register. Serial Port 0 Control (SCON0) SFR 98h SM0−2 bits 7−5 7 6 5 4 3 2 1 0 Reset Value SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 0 0 0 0 FUNCTION Synchronous LENGTH 8 bits PERIOD 0 0 0 1 Synchronous 8 bits 1 0 1 0 Asynchronous 10 bits 1 0 1 1 Asynchronous−Valid Stop Required(2) 10 bits 2 1 0 0 Asynchronous 11 bits 2 1 0 1 Asynchronous with Multiprocessor Communication 11 bits 3 1 1 0 Asynchronous 11 bits Timer 1 Baud Rate Equation 3 1 1 1 Asynchronous with Multiprocessor Communication(3) 11 bits Timer 1 Baud Rate Equation 12 pCLK(1) 4 pCLK(1) Timer 1 Baud Rate Equation Timer 1 Baud Rate Equation 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) RI_0 will only be activated when a valid STOP is received. (3) RI_0 will not be activated if bit 9 = 0. REN_0 bit 4 Receive Enable. This bit enables/disables the serial Port 0 received shift register. 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_0 bit 3 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. RB8_0 bit 2 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. TI_0 bit 1 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 bit 0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software. 45 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Serial Data Buffer 0 (SBUF0) 7 6 5 4 3 2 1 0 SFR 99h SBUF0 bits 7−0 Reset Value 00h Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive buffers are separate registers, but both are addressed at this location. SPI Control (SPICON) SFR 9Ah SBIT3−0 bits 7−4 7 6 5 4 3 2 1 0 Reset Value SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00h Serial Bit Count. Number of bits transferred (read-only). SBIT3:0 COUNT 0x00 0 0x01 1 0x03 2 0x02 3 0x06 4 0x07 5 0x05 6 0x04 7 0x0C 8 ORDER bit 3 Set Bit Order for Transmit and Receive. 0: Most Significant Bits First 1: Least Significant Bits First CPHA bit 2 Serial Clock Phase Control. 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK ESS bit 1 Enable Slave Select. 0: SS (P1.4) is configured as a general-purpose I/O (default). 1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is high-impedance when SS is high. CPOL bit 0 Serial Clock Polarity. 0: SCK idle at logic LOW 1: SCK idle at logic HIGH 46 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 I2C Control (I2CCON) SFR 9Ah SBIT3−0 bits 7−4 7 6 5 4 3 2 1 0 Reset Value SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 00h Serial Bit Count. Number of bits transferred (read-only). SBIT3:0 COUNT 0x00 0 0x01 1 0x03 2 0x02 3 0x06 4 0x07 5 0x05 6 0x04 7 0x0C 8 STOP bit 3 Stop-Bit Status. 0: No Stop 1: Stop Condition Received and I2CCNT set (cleared on write to I2CDATA) START bit 2 Start-Bit Status. 0: No Stop 1: Start or Repeated Start Condition Received and I2CCNT set (cleared on write to I2CDATA) DCS bit 1 Disable Serial Clock Stretch. 0: Enable SCL Stretch (cleared by firmware or START condition) 1: Disable SCL Stretch CNTSEL bit 0 Counter Select. 0: Counter IRQ Set for Bit Counter = 8 (default) 1: Counter IRQ Set for Bit Counter = 1 (default) SPI Data Register (SPIDATA) / I2C Data Register (I2CDATA) 7 SFR 9Bh 6 5 4 3 2 1 0 Reset Value 00h SPIDATA bits 7−0 SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the transmit interrupt. I2CDATA bits 7−0 I2C Data Register. Data for I2C is read from or written to this location. The I2C transmit and receive buffers are separate registers, but both are addressed at this location. 47 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Auxiliary Interrupt Poll (AIPOL) SFR A4h 7 6 5 4 3 2 1 0 Reset Value SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP 0 00h Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers. SECIP bit 7 Second System Timer Interrupt Poll (before IRQ masking). 0 = Second System Timer Interrupt Poll Inactive 1 = Second System Timer Interrupt Poll Active SUMIP bit 6 Accumulator Interrupt Poll (before IRQ masking). 0 = Accumulator Interrupt Poll Inactive 1 = Accumulator Interrupt Poll Active ADCIP bit 5 ADC Interrupt Poll (before IRQ masking). 0 = ADC Interrupt Poll Inactive 1 = ADC Interrupt Poll Active MSECIP bit 4 Millisecond System Timer Interrupt Poll (before IRQ masking). 0 = Millisecond System Timer Interrupt Poll Inactive 1 = Millisecond System Timer Interrupt Poll Active I2CIP bit 3 I2C Interrupt Poll (before IRQ masking). 0 = I2C Interrupt Poll Inactive 1 = I2C Interrupt Poll Active CNTIP bit 2 Serial Bit Count Interrupt Poll (before IRQ masking). 0 = Serial Bit Count Interrupt Poll Inactive 1 = Serial Bit Count Interrupt Poll Active ALVDIP bit 1 Analog Low Voltage Detect Interrupt Poll (before IRQ masking). 0 = Analog Low Voltage Detect Interrupt Poll Inactive 0 = Analog Low Voltage Detect Interrupt Poll Active Pending Auxiliary Interrupt (PAI) SFR A5h PAI bits 3−0 48 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the appropriate interrupt routine. All of these interrupts vector through address 0033h. PAI3 PAI2 PAI1 PAI0 0 0 0 0 AUXILIARY INTERRUPT STATUS No Pending Auxiliary IRQ. 0 0 0 1 Reserved. 0 0 1 0 0 0 1 1 Analog Low Voltage Detect IRQ and Possible Lower Priority Pending. I2C IRQ and Possible Lower Priority Pending. 0 1 0 0 Serial Bit Count Interrupt and Possible Lower Priority Pending. 0 1 0 1 Millisecond System Timer IRQ and Possible Lower Priority Pending. 0 1 1 0 ADC IRQ and Possible Lower Priority Pending. 0 1 1 1 Accumulator IRQ and Possible Lower Priority Pending. 1 0 0 0 Second System Timer IRQ and Possible Lower Priority Pending. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Auxiliary Interrupt Enable (AIE) SFR A6h 7 6 5 4 3 2 1 0 Reset Value ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00h Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers. ESEC bit 7 Enable Second System Timer Interrupt (lowest priority auxiliary interrupt). Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Second Timer Interrupt mask. ESUM bit 6 Enable Summation Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Summation Interrupt mask. EADC bit 5 Enable ADC Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: ADC Interrupt mask. EMSEC bit 4 Enable Millisecond System Timer Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Millisecond System Timer Interrupt mask. ESPIT bit 3 Enable I2C Start/Stop Bit. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: I2C Start/Stop Bit mask. ECNT bit 2 Enable Serial Bit Count Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Serial Bit Count Interrupt mask. EALV bit 1 Enable Analog Low Voltage Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Analog Low Voltage Detect Interrupt mask. 49 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Auxiliary Interrupt Status Register (AISTAT) SFR A6h 7 6 5 4 3 2 1 0 Reset Value SEC SUM ADC MSEC I2C CNT ALVD 0 00h SEC bit 7 Second System Timer Interrupt Status Flag (lowest priority AI). 0: SEC interrupt cleared or masked. 1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9h). SUM bit 6 Summation Register Interrupt Status Flag. 0: SUM interrupt cleared or masked. 1: SUM interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2h). ADC bit 5 ADC Interrupt Status Flag. 0: ADC interrupt cleared or masked. 1: ADC interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9h; if active, no new data will be written to the ADC Results registers). MSEC bit 4 Millisecond System Timer Interrupt Status Flag. 0: MSEC interrupt cleared or masked. 1: MSEC interrupt active (it is cleared by reading MSINT, SFR FAh). I2C bit 3 I2C Start/Stop Interrupt Status Flag. 0: I2C Start/stop interrupt cleared or masked. 1: I2C Start/stop interrupt active (it is cleared by writing to I2CDATA, SFR 9Bh). CNT bit 2 CNT Interrupt Status Flag. 0: CNT Interrupt cleared or masked. 1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9Bh). ALVD bit 1 Analog Low Voltage Detect Interrupt Status Flag. 0: ALVD Interrupt cleared or masked. 1: ALVD Interrupt active (cleared in HW if AVDD exceeds ALVD threshold). NOTE: If an interrupt is masked, the status can be read in AIPOL (SFR A4h). 50 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Interrupt Enable (IE) SFR A8h 7 6 5 4 3 2 1 0 Reset Value EA 0 0 ES0 ET1 EX1 ET0 EX0 00h EA bit 7 Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES0 bit 4 Enable Serial port 0 Interrupt. This bit controls the masking of the serial Port 0 interrupt. 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags. ET1 bit 3 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h). EX1 bit 2 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 bit 1 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h). EX0 bit 0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin. 51 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Port 1 Data Direction Low Register (P1DDRL) SFR AEh P1.3 bits 7−6 P1.2 bits 5−4 P1.1 bits 3−2 P1.0 bits 1−0 52 7 6 5 4 3 2 1 0 Reset Value P13H P13L P12H P12L P11H P11L P10H P10L 00h Port 1 bit 3 control. P13H P13L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 2 control. P12H P12L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 1 control. P11H P11L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 0 control. P10H P10L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Port 1 Data Direction High Register (P1DDRH) SFR AFh P1.7 bits 7−6 P1.6 bits 5−4 P1.5 bits 3−2 P1.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P17H P17L P16H P16L P15H P15L P14H P14L 00h Port 1 bit 7 control. P17H P17L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 6 control. P16H P16L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 5 control. P15H P15L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 4 control. P14H P14L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 53 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Port 3 (P3) SFR B0h P3.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value P3.7 P3.6 SCK/SCL/CLKS P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. SCK/SCL/CLKS Clock Source Select. Refer to PASEL (SFR F2h). bit 6 T1 bit 5 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. T0 bit 4 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. INT1 bit 3 External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. INT0 bit 2 External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. TXD0 bit 1 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the synchronizing clock in serial port mode 0. RXD0 bit 0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data transfer pin in serial port mode 0. 54 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Port 3 Data Direction Low Register (P3DDRL) SFR B3h P3.3 bits 7−6 P3.2 bits 5−4 P3.1 bits 3−2 P3.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P33H P33L P32H P32L P31H P31L P30H P30L 00h Port 3 bit 3 control. P33H P33L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 bit 2 control. P32H P32L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 bit 1 control. P31H P31L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 bit 0 control. P30H P30L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 55 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Port 3 Data Direction High Register (P3DDRH) SFR B4h P3.7 bits 7−6 7 6 5 4 3 2 1 0 Reset Value P37H P37L P36H P36L P35H P35L P34H P34L 00h Port 3 bit 7 control. P37H P37L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 bits 5−4 Port 3 bit 6 control. P36H P36L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1. P3.5 bits 3−2 P3.4 bits 1−0 56 Port 3 bit 5 control. P35H P35L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 bit 4 control. P34H P34L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 IDAC Register 7 6 5 4 3 2 1 0 SFR B5h IDAC bits 7−0 Reset Value 00h IDAC Register. IDACOUT = IDAC • 3.8µA (∼1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC and float the IDAC pin. Interrupt Priority (IP) SFR B8h 7 6 5 4 3 2 1 0 Reset Value 1 0 0 PS0 PT1 PX1 PT0 PX0 80h PS0 bit 4 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high priority interrupt. PT1 bit 3 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high priority interrupt. PX1 bit 2 External Interrupt 1. This bit controls the priority of external interrupt 1. 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high priority interrupt. PT0 bit 1 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high priority interrupt. PX0 bit 0 External Interrupt 0. This bit controls the priority of external interrupt 0. 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high priority interrupt. Enable Wake Up (EWU) Waking Up from IDLE Mode SFR C6h 7 6 5 4 3 2 1 0 Reset Value — — — — — EWUWDT EWUEX1 EWUEX0 00h Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5). EWUWDT bit 2 Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt. 0 = Do not wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 bit 1 Enable Wake Up External 1. Wake using external interrupt source 1. 0 = Do not wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 bit 0 Enable Wake Up External 0. Wake using external interrupt source 0. 0 = Do not wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0. 57 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 System Clock Divider Register (SYSCLK) SFR C7h 7 6 5 4 3 2 1 0 Reset Value 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h DIVMOD1−0 Clock Divide Mode bits 5−4 Write: DIVMOD DIVIDE MODE 00 Normal mode (default, no divide). 01 Immediate mode: start divide immediately; return to Normal mode on IDLE wakeup condition or Normal mode write. 10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Can exit on Normal mode write. 11 Manual mode: start divide immediately; exit mode only on write to DIVMOD. Read: DIVMOD DIV2−0 bit 2−0 58 DIVISION MODE STATUS 00 No divide 01 Divider is in Immediate mode 10 Divider is in Delay mode 11 Medium mode Divide Mode DIV DIVISOR 000 Divide by 2 (default) 001 Divide by 4 010 Divide by 8 011 Divide by 16 100 Divide by 32 101 Divide by 1024 110 Divide by 2048 111 Divide by 4096 fCLK = fSYS/2 fCLK = fSYS/4 fCLK = fSYS/8 fCLK = fSYS/16 fCLK = fSYS/32 fCLK = fSYS/1024 fCLK = fSYS/2048 fCLK = fSYS/4096 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Program Status Word (PSW) SFR D0h 7 6 5 4 3 2 1 0 Reset Value CY AC F0 RS1 RS0 OV F1 P 00h CY bit 7 Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during subtraction). Otherwise it is cleared to 0 by all arithmetic operations. AC bit 6 Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition), or a borrow (during subtraction) from the high order nibble. Otherwise it is cleared to 0 by all arithmetic operations. F0 bit 5 User Flag 0. This is a bit-addressable, general-purpose flag for software control. RS1, RS0 bits 4−3 Register Bank Select 1−0. These bits select which register bank is addressed during register accesses. RS1 RS0 REGISTER BANK 0 0 0 ADDRESS 00h − 07h 0 1 1 08h − 0Fh 1 0 2 10h − 17h 1 1 3 18h − 1Fh OV bit 2 Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations. F1 bit 1 User Flag 1. This is a bit-addressable, general-purpose flag for software control. P bit 0 Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and cleared to 0 on even parity. 59 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ADC Offset Calibration Register Low Byte (OCL) 7 6 5 4 3 2 1 SFR D1h 0 Reset Value LSB 00h Both the MSC1201 and MSC1202 support 24-bit calibration values. OCL bits 7−0 ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register Middle Byte (OCM) 7 6 5 4 3 2 1 0 SFR D2h Reset Value 00h Both the MSC1201 and MSC1202 support 24-bit calibration values. OCM bits 7−0 ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register High Byte (OCH) 7 SFR D3h 6 5 4 3 2 1 0 MSB Reset Value 00h Both the MSC1201 and MSC1202 support 24-bit calibration values. OCH bits 7−0 ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value. ADC Gain Calibration Register Low Byte (GCL) 7 6 5 4 3 2 1 SFR D4h 0 Reset Value LSB 5Ah Both the MSC1201 and MSC1202 support 24-bit calibration values. GCL bits 7−0 ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC gain calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register Middle Byte (GCM) 7 6 5 4 3 2 1 0 SFR D5h Reset Value ECh Both the MSC1201 and MSC1202 support 24-bit calibration values. GCM bits 7−0 ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register High Byte (GCH) 7 SFR D6h 6 5 4 3 MSB 2 1 0 Reset Value 5Fh Both the MSC1201 and MSC1202 support 24-bit calibration values. GCH bits 7−0 60 ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC gain calibration. A value that is written to this location will set the ADC gain calibration value. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ADC Input Multiplexer Register (ADMUX) SFR D7h INP3−0 bits 7−4 INN3−0 bits 3−0 7 6 5 4 3 2 1 0 Reset Value INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h Input Multiplexer Positive Input. This selects the positive signal input. INP3 INP2 INP1 INP0 0 0 0 0 POSITIVE INPUT AIN0 (default) 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 REFIN− 0 1 1 1 REFIN− 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) Input Multiplexer Negative Input. This selects the negative signal input. INN3 INN2 INN1 INN0 0 0 0 0 NEGATIVE INPUT AIN0 0 0 0 1 AIN1 (default) 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 REFIN− 0 1 1 1 REFIN− 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) 61 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Enable Interrupt Control (EICON) SFR D8h 7 6 5 4 3 2 1 0 Reset Value 0 1 EAI AI WDTI 0 0 0 40h EAI bit 5 Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI bit 4 Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. WDTI bit 3 Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in HCR0. 0 = No Watchdog Timer Interrupt Detected (default). 1 = Watchdog Timer Interrupt Detected. ADC Results Register Low Byte (ADRESL) 7 6 5 4 3 2 1 SFR D9h ADRESL bits 7−0 0 Reset Value LSB 00h The ADC Results Low Byte. This is the low byte of the ADC results. Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared. ADC Results Register Middle Byte (ADRESM) 7 6 5 4 3 2 1 0 SFR DAh ADRESM Reset Value 00h The ADC Results Middle Byte. This is the middle byte of the ADC results for the MSC1201 and the most significant byte for the MSC1202. bits 7−0 ADC Results Register High Byte (ADRESH) 7 SFR DBh ADRESH bits 7−0 62 MSB 6 5 4 3 2 1 0 Reset Value 00h The ADC Results High Byte. This is the high byte and most significant byte of the ADC results for the MSC1201. This is a sign-extended (Bipolar mode) or zero-padded (Unipolar mode) byte for the MSC1202 (that is, all 0s for positive ADC or unipolar results and all 1s for negative ADC results). "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ADC Control Register 0 (ADCON0) SFR DCh 7 6 5 4 3 2 1 0 Reset Value — BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h BOD bit 6 Burnout Detect. When enabled, this connects a positive current source to the positive channel and a negative current source to the negative channel. If the channel is open circuit, then the ADC results will be full-scale (buffer must be enabled). 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. EVREF bit 5 Enable Internal Voltage Reference. If an external voltage is used, the internal voltage reference should be disabled. 0 = Internal Voltage Reference Off for external reference. 1 = Internal Voltage Reference On (default). Note that REFIN− must be connected to AGND. VREFH bit 4 Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. 0 = REFOUT/REF IN+ is 1.25V. 1 = REFOUT/REF IN+ is 2.5V (default). EBUF bit 3 Enable Buffer. Enables the input buffer to provide higher input impedance but limits the input voltage range and dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. Input signal limited to AVDD − 1.5V. PGA2−0 bits 2−0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128. PGA2 PGA1 PGA0 GAIN 0 0 0 1 (default) 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 63 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ADC Control Register 1 (ADCON1) SFR DDh 7 6 5 4 3 2 1 0 Reset Value OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 00h OF_UF bit 6 Overflow/Underflow. If this bit is set, the data in the Summation register is invalid; either an overflow or underflow occurred. This bit is cleared by writing a ‘0’ to it. POL bit 6 Polarity. Polarity of the ADC result and Summation register. 0 = Bipolar. 1 = Unipolar. DIGITAL OUTPUT POL MSC1201 MSC1202(1) ANALOG INPUT +FSR 0x7FFFFF 0x7FFF ZERO 0x000000 0x0000 0 1 −FSR 0x800000 0x8000 +FSR 0xFFFFFF 0xFFFF ZERO 0x000000 0x0000 −FSR 0x000000 0x0000 (1) The MSC1202 ADC result is sign-extended into ADRESH. SM1−0 bits 5−4 CAL2−0 bits 2−0 Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics. SM1 SM0 0 0 SETTLING MODE Auto 0 1 1 0 Fast Settling Filter Sinc2 Filter 1 1 Sinc3 Filter Calibration Mode Control Bits. Writing to this register initiates calibration. CAL2 CAL1 CAL0 CALIBRATION MODE 0 0 0 No Calibration (default) 0 0 1 Self-Calibration, Offset and Gain 0 1 0 Self-Calibration, Offset only 0 1 1 Self-Calibration, Gain only 1 0 0 System Calibration, Offset only (requires external connection) 1 0 1 System Calibration, Gain only (requires external connection) 1 1 0 Reserved 1 1 1 Reserved NOTE: Read value—000B. 64 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 ADC Control Register 2 (ADCON2) SFR DEh DR7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh Decimation Ratio LSB (refer to ADCON3, SFR DFh). ADC Control Register 3 (ADCON3) SFR DFh 7 6 5 4 3 2 1 0 Reset Value — — — — — DR10 DR9 DR8 06h DR10−8 Decimation Ratio Most Significant 3 Bits. bits 2−0 The ADC output data rate is: fMOD Decimation Ratio where fMOD + fCLK (ACLK)1) @ 64 . Accumulator (A or ACC) SFR E0h ACC.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h Accumulator. This register serves as the accumulator for arithmetic and logic operations. 65 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Summation/Shifter Control (SSCON) SFR E1h 7 6 5 4 3 2 1 0 Reset Value SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit SUMR3−0 registers will be cleared. The Summation registers will do sign extend if Bipolar Mode is selected in ADCON1. SSCON1−0 Summation/Shift Count. bits 7−6 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 0 0 0 0 0 0 0 0 DESCRIPTION Clear Summation Register 0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0 (sum count/shift ignored) 0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0 (sum count/shift ignored) 1 0 x x x Note (1) Note (1) Note (1) 0 1 Note (1) Note (1) Note (1) x x x 1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) CPU Shift only ADC Summation only ADC Summation completes then shift completes (1) Refer to register bit definition. SCNT2−0 bits 5−3 SHF2−0 bits 2−0 66 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the SUMR0 register clears the interrupt. SCNT2 SCNT1 SCNT0 SUMMATION COUNT 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 Shift Count. SHF2 SHF1 SHF0 SHIFT DIVIDE 0 0 0 1 2 0 0 1 2 4 0 1 0 3 8 0 1 1 4 16 1 0 0 5 32 1 0 1 6 64 1 1 0 7 128 1 1 1 8 256 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Summation Register 0 (SUMR0) 7 6 5 4 3 2 1 SFR E2h SUMR0 bits 7−0 0 Reset Value LSB 00h Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. Write: Will cause values in SUMR3−0 to be added to the summation register. Read: Will clear the Summation Interrupt. Summation Register 1 (SUMR1) 7 6 5 4 3 2 1 0 Reset Value SFR E3h SUMR1 bits 7−0 00h Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8−15. Summation Register 2 (SUMR2) 7 6 5 4 3 2 1 0 Reset Value SFR E4h SUMR2 bits 7−0 00h Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16−23. Summation Register 3 (SUMR3) 7 SFR E5h SUMR3 bits 7−0 6 5 4 3 2 1 0 Reset Value MSB 00h Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24−31. Offset DAC Register (ODAC) 7 6 5 4 SFR E6h 3 2 1 0 Reset Value 00h ODAC bits 7−0 Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC. bit 7 Offset DAC Sign Bit. 0 = Positive 1 = Negative bit 6−0 Offset + ǒ Ǔ *VREF ODAC [6 : 0] bit7 @ @ (*1) 127 2 @ PGA 67 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Low Voltage Detect Control (LVDCON) SFR E7h ALVDIS bit 7 7 6 5 4 3 2 1 0 Reset Value ALVDIS 0 0 0 1 1 1 1 8Fh Analog Low Voltage Detect Disable. 0 = Enable Detection of Low Analog Supply Voltage (ALVD flag and interrupt are set when AVDD < 2.8V). 1 = Disable Detection of Low Analog Supply Voltage. Extended Interrupt Enable (EIE) SFR E8h 7 6 5 4 3 2 1 0 Reset Value 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h EWDI bit 4 Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by the WDTCON (SFR FFh) and PDCON (SFR F1h) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 bit 3 External Interrupt 5 Enable. This bit enables/disables external interrupt 5. 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 EX4 bit 2 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 EX3 bit 1 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 EX2 bit 0 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2 Hardware Product Code Register 0 (HWPC0) (read-only) SFR E9h 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 DEVICE MEMORY 0000_00xxb HWPC0.7−0 Hardware Product Code LSB. Read-only. bits 7−0 DEVICE MEMORY MODEL FLASH MEMORY 0 0 MSC1201Y2 4kB 0 1 1 1 0 1 MSC1201Y3 MSC1202Y2 MSC1202Y3 8kB 4kB 8kB Hardware Product Code Register 1 (HWPC1) (read-only) SFR EAh 7 6 5 4 3 2 1 0 Reset Value 0 0 1 0 0 0 0 0 20h HWPC1.7−0 Hardware Product Code MSB. Read-only. bits 7−0 68 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Hardware Version Register (HWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBh Flash Memory Control (FMCON) SFR EEh 7 6 5 4 3 2 1 0 Reset Value 0 PGERA 0 FRCM 0 BUSY 1 0 02h PGERA bit 6 Page Erase. Available in both user and program modes. 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode FRCM bit 4 Frequency Control Mode. The bypass is only used for slow clocks to save power. 0 = Bypass (default) 1 = Use Delay Line. Saves power (recommended). BUSY bit 2 Write/Erase BUSY Signal. 0 = Idle or Available 1 = Busy Flash Memory Timing Control Register (FTCON) SFR EFh 7 6 5 4 3 2 1 0 Reset Value FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h 1 0 Reset Value Refer to Flash Timing Characteristics FER3−0 bits 7−4 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK. 11ms industrial temperature range. 5ms commercial temperature range. FWR3−0 bits 3−0 Set Write. Set Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK. 30µs to 40µs. B Register (B) 7 6 5 4 3 2 SFR F0h B.7−0 bits 7−0 00h B Register. This register serves as a second accumulator for certain arithmetic operations. 69 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Power-Down Control Register (PDCON) SFR F1h 7 6 5 4 3 2 1 0 Reset Value PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDST PDSPI 6Fh Turning peripheral modules off puts the MSC1201/02 in the lowest power mode. PDICLK bit 6 Internal Clock Control. 0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode) 1 = Internal Oscillator and PLL Power Down (External Clock mode) PDIDAC bit 6 IDAC Control. 0 = IDAC On 1 = IDAC Power Down (default) PDI2C bit 5 I2C Control. 0 = I2C On (only when PDSPI = 1) 1 = I2C Power Down (default) PDADC bit 3 ADC Control. 0 = ADC On 1 = ADC, VREF, and Summation registers are powered down (default). PDWDT bit 2 Watchdog Timer Control. 0 = Watchdog Timer On 1 = Watchdog Timer Power Down (default) PDST bit 1 System Timer Control. 0 = System Timer On 1 = System Timer Power Down (default) PDSPI bit 0 SPI System Control. 0 = SPI System On 1 = SPI System Power Down (default) 70 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 PSEN/ALE Select (PASEL) SFR F2h PSEN2−0 bits 7−3 7 6 5 4 3 2 1 0 Reset Value PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00h PSEN Mode Select. Defines the output on P3.6 in User Application mode or Serial Flash Programming mode. 00000: General-purpose I/O (default) 00001: SYSCLK 00011: Internal PSEN (refer to Figure 5 for timing) 00101: Internal ALE (refer to Figure 5 for timing) 00111: fOSC (buffered XIN oscillator clock) 01001: Memory WR (MOVX write) 01011: T0 Out (overflow)(1) 01101: T1 Out (overflow)(1) 01111: fMOD(2) 10001: SYSCLK/2 (toggles on rising edge)(2) 10011: Internal PSEN/2(2) 10101: Internal ALE/2(2) 10111: fOSC(2) 11001: Memory WR/2 (MOVX write)(2) 11011: T0 Out/2 (overflow)(2) 11101: T1 Out/2 (overflow)(2) 11111: fMOD/2(2) (1) One period of these signals equal to tCLK. (2) Duty cycle is 50%. Phase Lock Loop Low Register (PLLL) SFR F4h PLL7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 xxh PLL Counter Value Least Significant Bit. PLL Frequency = External Crystal Frequency • PLL9:0. 71 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Phase Lock Loop High Register (PLLH) SFR F5h 7 6 5 4 3 2 1 0 Reset Value CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 xxh CLKSTAT2−0 Active Clock Status (read-only). Derived from HCR2 setting; refer to Table 3. bits 7−5 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status) 101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status) 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode PLLLOCK bit 4 PLL Lock Status and Status Enable. For Write (PLL Lock Status Enable): 0 = No Effect 1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid). For Read (PLL Lock Status): 0 = PLL Not Locked (PLL may be inactive; refer to Table 3 for active clock mode) 1 = PLL Locked (PLL is active clock). PLL9−8 bits 1−0 PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4h). Analog Clock (ACLK) SFR F6h FREQ6−0 bits 6−0 7 6 5 4 3 2 1 0 Reset Value 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock. . f CLK fOSC fACLK + fMOD ACLK ) 1 f ACLK + 64 , where fCLK + ADC Data Rate + fDATA + SYSCLK divider f MOD Decimation Ratio System Reset Register (SRST) SFR F7h RSTREQ bit 0 72 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 RSTREQ 00h Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset. "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Extended Interrupt Priority (EIP) SFR F8h 7 6 5 4 3 2 1 0 Reset Value 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h PWDI bit 4 Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 bit 3 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. PX4 bit 2 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. PX3 bit 1 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. PX2 bit 0 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority. Seconds Timer Interrupt (SECINT) SFR F9h 7 6 5 4 3 2 1 0 Reset Value WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored in the AIE register. WRT bit 7 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation. SECINT6−0 Seconds Count. Normal operation would use 100ms as the clock interval. bits 6−0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • tCLK. 73 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Milliseconds Interrupt (MSINT) SFR FAh 7 6 5 4 3 2 1 0 Reset Value WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also be cleared. WRT bit 7 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. MSINT6−0 bits 6−0 Milliseconds Count. Normal operation would use 1ms as the clock interval. MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • tCLK One Microsecond Register (USEC) SFR FBh FREQ5−0 bits 5−0 7 6 5 4 3 2 1 0 Reset Value 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs Clock. USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh). One Millisecond Low Register (MSECL) SFR FCh 7 6 5 4 3 2 1 0 Reset Value MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9Fh MSECL7−0 One Millisecond Low. This value in combination with the next register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFh). One Millisecond High Register (MSECH) SFR FDh 7 6 5 4 3 2 1 0 Reset Value MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh MSECH7−0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK. One Hundred Millisecond Register (HMSEC) SFR FEh WRT 7 6 5 4 3 2 1 0 Reset Value HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. HMSEC7−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 7−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK. 74 "#$%&$ "#$%&% www.ti.com SBAS317B − APRIL 2004 − REVISED JANUARY 2005 Watchdog Timer Register (WDTCON) SFR FFh 7 6 5 4 3 2 1 0 Reset Value EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h EWDT bit 7 Enable Watchdog (R/W). Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT bit 6 Disable Watchdog (R/W). Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT bit 5 Reset Watchdog (R/W). Write 1/Write 0 sequence restarts the Watchdog Counter. WDCNT4−0 Watchdog Count (R/W). bits 4−0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count. NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is cleared and the watchdog timer expires, an interrupt is generated (see Table 7). 75 PACKAGE OPTION ADDENDUM www.ti.com 19-May-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MSC1201Y2RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM MSC1201Y2RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM MSC1201Y3RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM MSC1201Y3RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM MSC1202Y2RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM Lead/Ball Finish MSL Peak Temp (3) MSC1202Y2RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM MSC1202Y3RHHR ACTIVE QFN RHH 36 2500 TBD CU SNPB Level-1-235C-UNLIM MSC1202Y3RHHT ACTIVE QFN RHH 36 250 TBD CU SNPB Level-1-235C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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