25AA640A/25LC640A
64K SPI Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
Page Size
Temp. Ranges
Packages
25LC640A
2.5-5.5V
32 Byte
I,E
P, SN, ST, MS, MF, MNY
25AA640A
1.8-5.5V
32 Byte
I, E
P, SN, ST, MS, MF, MNY
Features:
Description:
• Max. Clock 10 MHz
• Low-Power CMOS Technology:
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 1 A at 5.5V
• 8192 x 8-bit Organization
• 32 Byte Page
• Self-Timed Erase and Write Cycles (5 ms max.)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential Read
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
- Automotive (E):
-40°C to +125°C
The Microchip Technology Inc. 25AA640A/25LC640A
(25XX640A*) are 64 kbit Serial Electrically Erasable
PROMs. The memory is accessed via a simple Serial
Peripheral Interface (SPI) compatible serial bus. The
bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX640A is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead MSOP, 8-lead TSSOP, DFN
and TDFN.
Package Types (not to scale)
PDIP/SOIC
TSSOP/MSOP
(P, SN)
(ST, MS)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
1
2
8
7
VCC
HOLD
WP
3
6
SCK
VSS
4
5
SI
X-Rotated TSSOP
DFN/TDFN
(MF/MNY)
(X/ST)
HOLD
VCC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
VSS
WP
CS
SO
WP
VSS
1
8
VCC
2
7
3
6
4
5
HOLD
SCK
SI
* 25XX640A is used in this document as a generic part number
for the 25AA640A, 25LC640A devices.
2003-2013 Microchip Technology Inc.
DS21830F-page 1
25AA640A/25LC640A
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-40°C to 125°C
ESD protection on all pins ..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Industrial (I):
TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Min.
Max.
Units
D001
VIH1
High-level input
voltage
0.7 VCC
VCC +1
V
D002
VIL1
-0.3
0.3 VCC
V
D003
VIL2
Low-level input
voltage
D004
VOL
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
Test Conditions
VCC2.7V
-0.3
0.2 VCC
V
VCC < 2.7V
Low-level output
voltage
—
0.4
V
IOL = 2.1 mA
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
VCC -0.5
—
V
IOH = -400 A
D005
VOL
D006
VOH
High-level output
voltage
D007
ILI
Input leakage current
—
±1
A
CS = VCC, VIN = VSS or VCC
D008
ILO
Output leakage
current
—
±1
A
CS = VCC, VOUT = VSS or VCC
D009
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
D010
ICC Read
—
—
5
mA
2.5
mA
VCC = 5.5V; FCLK = 10.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
—
—
5
A
1
A
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 125°C
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 85°C
Operating Current
D011
ICC Write
D012
ICCS
Standby Current
Note:
This parameter is periodically sampled and not 100% tested.
DS21830F-page 2
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Industrial (I):
TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
Min.
Max.
Units
Test Conditions
—
—
—
10
5
3
MHz
MHz
MHz
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
1
FCLK
Clock frequency
2
TCSS
CS setup time
50
100
150
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
3
TCSH
CS hold time
100
200
250
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4
TCSD
CS disable time
50
—
ns
—
5
Tsu
Data setup time
10
20
30
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
6
THD
Data hold time
20
40
50
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
7
TR
CLK rise time
—
100
ns
(Note 1)
8
TF
CLK fall time
—
100
ns
(Note 1)
9
THI
Clock high time
50
100
150
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
10
TLO
Clock low time
50
100
150
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
11
TCLD
Clock delay time
50
—
ns
—
12
TCLE
Clock enable time
50
—
ns
—
13
TV
Output valid from clock
low
—
—
—
50
100
160
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
14
THO
Output hold time
0
—
ns
(Note 1)
15
TDIS
Output disable time
—
—
—
40
80
160
ns
ns
ns
4.5V Vcc 5.5V (Note 1)
2.5V Vcc 4.5V (Note 1)
1.8V Vcc 2.5V (Note 1)
16
THS
HOLD setup time
20
40
80
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
2003-2013 Microchip Technology Inc.
DS21830F-page 3
25AA640A/25LC640A
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Industrial (I):
TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Min.
Max.
Units
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
Test Conditions
17
THH
HOLD hold time
20
40
80
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
18
THZ
HOLD low to output
High-Z
30
60
160
—
—
—
ns
ns
ns
4.5V Vcc 5.5V (Note 1)
2.5V Vcc 4.5V (Note 1)
1.8V Vcc 2.5V (Note 1)
19
THV
HOLD high to output valid
30
60
160
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
ms
(Note 3)
20
TWC
Internal write cycle time
—
5
21
—
Endurance
1M
—
E/W 25°C, VCC = 5.5V (Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
—
VHI = VCC - 0.2V
(Note 1)
VHI = 4.0V
(Note 2)
CL = 100 pF
—
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC 4.0V.
2: For VCC > 4.0V.
DS21830F-page 4
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
19
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
8
3
12
11
SCK Mode 0,0
5
SI
6
MSB in
LSB in
High-Impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
SO
14
MSB out
SI
2003-2013 Microchip Technology Inc.
15
ISB out
Don’t Care
DS21830F-page 5
25AA640A/25LC640A
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25XX640A is a 8192-byte serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25XX640A contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred Most Significant
Byte (MSB) first, Least Significant Byte (LSB) last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX640A in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX640A
followed by the 16-bit address, with the three MSBs of
the address being “don’t care” bits. After the correct
READ instruction and address are sent, the data stored
in the memory at the selected address is shifted out on
the SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to
provide clock pulses. The internal Address Pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached (1FFFh), the address counter rolls
over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS pin (Figure 2-1).
DS21830F-page 6
2.3
Write Sequence
Prior to any attempt to write data to the 25XX640A, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX640A. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the three
MSBs of the address being “don’t care” bits, and then
the data to be written. Up to 32 bytes of data can be
sent to the device before a write cycle is necessary.
The only restriction is that all of the bytes must reside
in the same page.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
BLOCK DIAGRAM
STATUS
Register
HV Generator
Memory
Control
Logic
I/O Control
Logic
EEPROM
Array
X
Dec
Page Latches
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
TABLE 2-1:
INSTRUCTION SET
Instruction Name
Instruction Format
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
WRDI
0000 0100
Reset the write enable latch (disable write operations)
WREN
0000 0110
Set the write enable latch (enable write operations)
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
FIGURE 2-1:
Description
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
1
1 15 14 13 12
2
1
0
Data Out
High-Impedance
SO
2003-2013 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS21830F-page 7
25AA640A/25LC640A
FIGURE 2-2:
BYTE WRITE SEQUENCE
CS
Twc
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
2
0 15 14 13 12
1
Data Byte
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 2-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0 1
Data Byte 1
2
0 15 14 13 12
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
DS21830F-page 8
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (32 max.)
1
0
7
6
5
4
3
2
1
0
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
2.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
The 25XX640A contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI will reset the latch.
FIGURE 2-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 2-5:
0
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-Impedance
SO
2003-2013 Microchip Technology Inc.
DS21830F-page 9
25AA640A/25LC640A
2.5
Read Status Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
7
6 5 4
3
2
1
W/R
– – – W/R W/R
R
WPEN X X X BP1 BP0 WEL
W/R = writable/readable. R = read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
0
R
WIP
See Figure 2-6 for the RDSR timing sequence.
The STATUS register can be continually read until the
CS is de-asserted.
The Write-In-Process (WIP) bit indicates whether the
25XX640A is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
High-Impedance
SO
DS21830F-page 10
1
0
1
Data from STATUS Register
7
6
5
4
3
2
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
2.6
Write Status Register Instruction
(WRSR)
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
array is divided up into four segments. The user has the
ability to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
FIGURE 2-7:
ARRAY PROTECTION
BP1
BP0
Array Addresses
Write-Protected
0
0
none
0
1
upper 1/4
(1800h-1FFFh)
1
0
upper 1/2
(1000h-1FFFh)
1
1
all
(0000h-1FFFh)
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
2003-2013 Microchip Technology Inc.
DS21830F-page 11
25AA640A/25LC640A
2.7
Data Protection
2.8
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 2-4:
Power-On State
The 25XX640A powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks
Unprotected Blocks
STATUS Register
0
x
x
Protected
Protected
Protected
1
0
x
Protected
Writable
Writable
1
1
0 (low)
Protected
Writable
Protected
1
1
1 (high)
Protected
Writable
Writable
x = don’t care
DS21830F-page 12
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Name
Pin
Number
X-Rotated
Pin Number
CS
1
3
Chip Select Input
SO
2
4
Serial Data Output
WP
3
5
Write-Protect Pin
VSS
4
6
Ground
SI
5
7
Serial Data Input
SCK
6
8
Serial Clock Input
HOLD
7
1
Hold Input
VCC
8
2
Supply Voltage
3.1
Function
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence
being initiated.
3.2
Serial Output (SO)
The SO pin is used to transfer data out of the
25XX640A. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
3.3
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX640A in a system with WP pin
grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the
WPEN bit is set high.
3.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX640A. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX640A while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX640A must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function
normally. When WP is high, all functions, including
writes to the nonvolatile bits in the STATUS register
operate normally. If the WPEN bit is set, WP low during
a STATUS register write sequence will disable writing
to the STATUS register. If an internal write cycle has
already begun, WP going low will have no effect on the
write.
2003-2013 Microchip Technology Inc.
DS21830F-page 13
25AA640A/25LC640A
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
8-Lead DFN-S (5x6x1 mm)
XXXXXXX
XXXXXXX
XXYYWW
NNN
8-Lead MSOP (150 mil)
XXXXXT
YWWNNN
Example:
5LC640A
E/MF e3
0728
IL7
Example:
5LCAI
7281L7
8-Lead PDIP
Example:
XXXXXXXX
T/XXXNNN
YYWW
25LC640A
I/P e3 1L7
0728
8-Lead SOIC
Example:
XXXXXXXT
XX/XXYYWW
NNN
25L640AI
SN e3 0728
1L7
8-Lead TSSOP
XXXX
TYWW
NNN
8-Lead 2x3 TDFN
XXX
YWW
NN
DS21830F-page 14
Example:
5LCA
I728
1L7
Example:
C81
828
17
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
1st Line Marking Codes
Part Number TSSOP
25AA640A
25LC640A
Note:
Rotated
TSSOP
MSOP
TDFN
I Temp.
E Temp.
5ACA
ACAX
5ACAT
C81
EG2
5LCA
LCAX
5LCAT
C84
C85
T = Temperature grade (I, E).
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2003-2013 Microchip Technology Inc.
DS21830F-page 15
25AA640A/25LC640A
!"#
$%& "'($)*+
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E2
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EXPOSED
PAD
NOTE 1
2
2
1
1
NOTE 1
D2
TOP VIEW
BOTTOM VIEW
φ
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A
A1
A3
NOTE 2
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DS21830F-page 16
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc.
DS21830F-page 17
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21830F-page 18
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc.
DS21830F-page 19
25AA640A/25LC640A
'--.//
!'#
,
2
&'
!&"&+#*!(!!&
+%&
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&&133***'
'3+
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
4&!
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5'&!
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9
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;
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5
*5#=#&
7 *@
/0
,
!"#$%&"' ()"&'"!&)
&#*&&&#
@%&0&!&
'!
!#,#
&"#'
#%!
&"!
!
#%!
&"!
!!
&$#A!#
'!
#&
,-.
/01/!'!
&$& "!
**&
"&&
!
* 09/
DS21830F-page 20
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc.
DS21830F-page 21
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21830F-page 22
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
"
0
-"112.34/ !"0'%#
,
2
&'
!&"&+#*!(!!&
+%&
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&&133***'
'3+
2003-2013 Microchip Technology Inc.
DS21830F-page 23
25AA640A/25LC640A
*5-"51-"
0
-"*636 !*""0#
,
2
&'
!&"&+#*!(!!&
+%&
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&&133***'
'3+
D
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E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
4&!
'!
5'&!
6"')
%!
55,,
6
6
67
8
9
&
7 :&
;
<./0
;
##++!!
9
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%%
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;
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7 =#&
,
##+=#&
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##+5&
2
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5
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,2
2
&
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;
9?
5#+!!
;
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'!
!#,#
&"#'
#%!
&"!
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&"!
!!
&$#.''!#
'!
#&
,-.
/01 /!'!
&$& "!
**&
"&&
!
,21 %'!
("!"*&
"&&
(%
%
'&
"
!!
* 09</
DS21830F-page 24
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc.
DS21830F-page 25
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21830F-page 26
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc.
DS21830F-page 27
25AA640A/25LC640A
7./38 !*#
,
2
&'
!&"&+#*!(!!&
+%&
&#&
&&133***'
'3+
DS21830F-page 28
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
APPENDIX A:
REVISION HISTORY
Revision A (9/2003)
Initial Release.
Revision B (12/2003)
Corrections to Section 1.0, Electrical Characteristics.
Revision C (9/2007)
Features and Description, removed reference to Pbfree packages; Revise Table 1-2: AC Characteristics,
parameters 7 and 8; Updated Packing Information/
Package Drawings; Add DFN Package; Removed
trademark from SPI.
Revision D (10/2008)
Added TDFN Package; Updated Package Drawings.
Revision E (02/2012)
Add text to Section 2.5.
Revision F (01/2013)
Revise Automotive E-temp; Revise Table 1-2, Param.
No. 21; Update Package Info.
2003-2013 Microchip Technology Inc.
DS21830F-page 29
25AA640A/25LC640A
NOTES:
DS21830F-page 30
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2003-2013 Microchip Technology Inc.
DS21830F-page 31
25AA640A/25LC640A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 25AA640A/25LC640A
Literature Number: DS21830F
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21830F-page 32
2003-2013 Microchip Technology Inc.
25AA640A/25LC640A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
Device
Tape & Reel
X
/XX
Temp Range
Package
–
Examples:
a)
b)
Device:
25AA640A =
25LC640A =
25AA640AX =
25LC640AX =
64k-bit, 1.8V, SPI Serial EEPROM
64k-bit, 2.5V, SPI Serial EEPROM
64k-bit, 1.8V, SPI Serial EEPROM in alternate
pinout (ST only)
64k-bit, 2.5V, SPI Serial EEPROM
in alternate pinout (ST only)
Tape & Reel:
Blank
T
=
=
Standard packaging
Tape & Reel
Temperature
Range:
I
E
=
=
-40C to+85C
-40C to+125C
Package:
MS
P
SN
ST
MF
MNY(1)
=
=
=
=
=
=
Plastic MSOP (Micro Small Outline), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (3.90 mm body), 8-lead
TSSOP (4.4 mm body), 8-lead
DFN (5x6), 8-lead
TDFN (2x3), 8-lead
Note
1:
c)
d)
e)
f)
25AA640A-I/MS = 64 kbit, 1.8V Serial
EEPROM, Industrial temp., MSOP
package
25AA640AT-I/SN = 64 kbit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, SOIC
package
25LC640AT-E/SN = 64 kbit, 2.5V Serial
EEPROM, Extended temp., Tape & Reel, SOIC
package
25LC640AT-I/ST = 64 kbit, 2.5V Serial
EEPROM, Industrial temp., Tape & Reel,
TSSOP package
25LC640AXT-I/ST = 64 kbit, 2.5V Serial
EEPROM, Industrial temp., Tape & Reel,
Rotated pinout, TSSOP package
25AA640AT-E/SN = 64 kbit, 1.8V Serial
EEPROM, Extended temp., Tape & Reel, SOIC
package
“Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
2003-2013 Microchip Technology Inc.
DS21830F-page 33
25AA640A/25LC640A
NOTES:
DS21830F-page 34
2003-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620768549
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2003-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21830F-page 35
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
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Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS21830F-page 36
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
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