CS3842B/3843B CS3842B/CS3843B Off-Line Current Mode PWM Control Circuit with Very Low Start Up Current Description Features possible. On board logic ensures that VREF is stabilized before the output stage is enabled. Ion-implant resistors provide tighter control of undervoltage lockout. The CS384XB provides all the necessary features to implement off-line fixed frequency current-mode control with a minimum number of external components. The family has been optimized for very low start up current (300µA, typ). Other features include pulse-by-pulse current limiting, and a high-current totem pole output for driving capacitive loads, such as the gate of a power MOSFET. The output is LOW in the off state, consistent with N-channel devices. The CS384XB family incorporates a precision temperature-controlled oscillator with an internally trimmed discharge current to minimize variations in frequency. A precision duty-cycle clamp eliminates the need for an external oscillator when a 50% duty-cycle is used. Duty-cycles of almost 100% are These ICs are available in 8 and 14 lead surface mount (SO) and 8 lead PDIP packages. Absolute Maximum Ratings Supply Voltage (ICC<30mA) ..........................................................Self Limiting Supply Voltage (Low Impedance Source)...................................................30V Output Current ...............................................................................................±1A Output Energy (Capacitive Load) .................................................................5µJ Analog Inputs (VFB, Sense) ............................................................-0.3V to 5.5V Error Amp Output Sink Current...............................................................10mA Lead Temperature Soldering Wave Solder (through hole styles only) ...................10 sec. max, 260°C peak Reflow (SMD styles only) ....................60 sec. max above 183°C, 230°C peak V CC V CC Pwr Undervoltage Lock-out Circuit 34V Set/ 5V Reset Reference V REF 16V/10V (8.4V/7.6V) Internal Bias REF 2.50V OSC – Error Amplifier 1 8 VREF VFB 2 7 VCC Sense 3 6 VOUT OSC 4 5 Gnd COMP 1 14 VREF NOR V OUT V FB COMP 14L SO Narrow Output Enable Oscillator S 2 R + Package Options 8 Lead PDIP & SO Narrow Block Diagram Gnd ■ Very low Start Up Current (300µA typ) ■ Optimized Off-line Control ■ Internally Trimmed, Temperature Compensated Oscillator ■ Maximum Duty-cycle Clamp ■ VREF stabilization before Output Enable ■ Pulse-by-pulse Current Limiting ■ Improved Undervoltage Lockout ■ Double Pulse Suppression ■ 1% Trimmed Bandgap Reference ■ High Current Totem Pole Output R VC R 1 V COMP PWM Latch Pwr Gnd Current Sense Comparator Sense NC 2 13 NC VFB 3 12 VCC NC 4 11 VCC Pwr Sense 5 10 VOUT NC 6 9 Pwr Gnd OSC 7 8 Gnd ( ) Indicates CS-3843B Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 6/23/99 1 A ® Company CS3842B/3843B Electrical Characteristics: 0≤TA≤70˚C, VCC=15V (Note 1); RT=680Ω, CT=.022µF for triangular mode, RT=10kΩ, CT=3.3nF for sawtooth mode (see Fig. 3), unless otherwise stated PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ■ Reference Section Output Voltage TJ=25˚C, IOUT=1mA 5.00 5.10 V Line Regulation 12≤VIN≤25V 6 20 mV Load Regulation 1≤IOUT≤20mA 6 25 mV Temperature Stability (Note 2) 0.2 0.4 mV/˚C Total Output Variation Line, Load, Temperature (Note 2) 5.18 V Output Noise Voltage 10Hz≤f≤10kHz, TJ=25˚C (Note 2) 4.90 4.82 50 µV Long Term Stability TA=125˚C, 1kHrs. (Note 2) 5 25 mV Output Short Circuit TA=25˚C -30 -100 -180 mA Initial Accuracy Sawtooth Mode (see Fig. 3), TJ=25˚C Triangular Mode (see Fig. 3), TJ=25˚C 47 44 52 52 57 60 kHz kHz Voltage Stability 12≤VCC≤25V 0.2 1.0 % Temp. Stability Sawtooth Mode TMIN≤TA≤TMAX (Note 2) Triangular Mode TMIN≤TA≤TMAX (Note 2) ■ Oscillator Section 5 % 8 % 1.7 V Amplitude Oscillator peak to peak Discharge Current TJ=25˚C TMIN≤TA≤TMAX 7.5 7.2 8.3 9.3 9.5 mA mA VCOMP=2.5V 2.42 2.50 2.58 V -0.3 -2.0 µA AVOL 2≤VOUT≤4V 65 90 dB Unity Gain Bandwidth (Note 2) 0.7 1.0 MHz ■ Error Amp Section Input Voltage Input Bias Current PSRR 12≤VCC≤25V 60 70 dB Output Sink Current VFB=2.7V, VOSC=1.1V 2 6 mA Output Source Current VFB=2.3V, VOSC=5V -0.5 -0.8 mA VOUT High VFB=2.3V, RL=15kΩ to ground 5 6 VOUT Low VFB=2.7V, RL=15kΩ to VREF V 0.7 1.1 V ■ Current Sense Section Gain (Notes 3 & 4) 2.85 3.00 3.15 V/V Maximum Input Signal VCOMP=5V (Note 3) 0.9 1.0 1.1 V PSRR 12≤VCC≤25V (Note 3) -2 -10 µA TJ=25˚C (Note 2) 150 300 ns Output Low Level ISINK=20mA ISINK=200mA 0.1 1.5 0.4 2.2 V V Output High Level ISOURCE=20mA ISOURCE=200mA 70 Input Bias Current Delay to Output dB ■ Output Section 13.0 12.0 2 13.5 13.5 V V PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ■ Output Section: continued Rise Time TJ=25˚C, CL=1nF (Note 2) 50 150 ns Fall Time TJ=25˚C, CL=1nF (Note 2) 50 150 ns Output Leakage UVLO Active, VOUT=0 -0.01 -10.00 µA 0.3 0.5 mA 17 mA ■ Total Standby Current Start-Up Current Operating Supply Current VFB=VSense=0V RT=10kΩ, CT=3.3nF 11 VCC Zener Voltage ICC=25mA 34 V CS-3842B PARAMETER TEST CONDITIONS MIN TYP CS-3843B MAX MIN TYP MAX UNITS ■ Under-Voltage Lockout Section Start Threshold Min. Operating Voltage After Turn On Notes: 1. Adjust VCC above the start threshold before setting at 15V. 14.5 16.0 17.5 7.8 8.4 9.0 V 8.5 10.0 11.5 7.0 7.6 8.2 V 3. Parameter measured at trip point of latch with VFB=0. 2. These parameters, although guaranteed, are not 100% tested in production. 4. Gain defined as: A= ∆VCOMP ∆VSense ; 0 ≤ VSense ≤ 0.8V. Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION 8L PDIP/SO 14L SO Narrow 1 1 COMP 2 3 VFB 3 5 Sense Noninverting input to Current Sense Comparator 4 7 OSC Oscillator Timing Network with Capacitor to Ground, resistor to VREF 5 8 Gnd Ground 9 Pwr Gnd 10 VOUT 11 VCCPwr 7 12 VCC Positive power supply 8 14 VREF Output of 5V internal reference 2,4,6,13 NC No Connection 6 Error amp output, used to compensate error amplifier Error amp inverting input Output driver Ground Output drive pin Output driver positive supply 3 CS3842B/3843B Electrical Characteristics: continued CS3842B/3843B Typical Performance Characteristics: Oscillator Duty Cycle vs RT Oscillator Frequency vs CT 100 900 90 800 80 RT =680Ω DUTY CYCLE (%) FREQ. (kHz) 700 600 500 RT =1.5kΩ 400 70 60 50 40 30 300 20 200 RT =10kΩ 10 100 100 .0005 .001 .002 .003 .005 .01 .02 200 300 400 500 700 1k 2k 3k 4k 5k 7k 10k .03 .04 .05 RT (Ω) CT (µF) Test Circuit V REF RT 2N2222 V CC A 100kΩ COMP 4.7kΩ 0.1µF CS-3842B 1kΩ ERROR AMP ADJUST 4.7kΩ V REF V FB CS-3843B V CC 0.1µF 5kΩ V OUT V OUT Sense Sense ADJUST 1kΩ 1W OSC Gnd Gnd CT Circuit Description Undervoltage Lockout V CC During Undervoltage Lockout (Figure 1), the output driver is biased to a high impedance state. VOUT should be shunted to ground with a resistor to prevent output leakage current from activating the power switch. ON/OFF Command to reset of IC CS3842B CS3843B V ON V OFF 16V 10V 8.4V 7.6V PWM Waveform To generate the PWM waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (Figure 2). An increase in VCC causes the inductor current slope to increase, thus reducing the duty cycle. This is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage. When the power supply sees a sudden large output current increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty I CC <15mA <0.5mA V CC V ON V OFF Figure 1: Typical Undervoltage Characteristics 4 cycle tends to exceed the maximum allowed, to prevent transformer saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator timing components. VOSC OSC RESET Setting the Oscillator EA Output The oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source (Figure 3). During the discharge time, the internal clock signal blanks out the output to the Low state, thus providing a user selected maximum duty cycle clamp. Switch Current VCC Charge and discharge times are determined by the general formulas: IOUT VOUT tc = RTCT ln ( VREF – Vlower VREF – Vupper ) Figure 2: Timing Diagram for key CS-384XB parameters td = RTCT ln V REF ( VREF – Id RT –Vlower VREF – Id RT – Vupper ) Substituting in typical values for the parameters in the above formulas: RT OSC CT then Gnd VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA, tc ≈ 0.5534RTCT td = RTCT ln Vupper ( 2.3 – 0.0083 RT 4.0 – 0.0083 RT ) The frequency and maximum duty cycle can be determined from the Typical Performance Characteristics graphs. Vlower tc td Grounding High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to ground in a single point ground. Sawtooth Mode LARGE RT (≈10kΩ) VOSC The transistor and 5kΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense. Internal Clock Triangular Mode SMALL RT (≈700kΩ) VREF Internal Clock Figure 3: Oscillator Timing Network and parameters 5 CS3842B/3843B Figure 3: Oscillator CS3842B/3843B Package Specification PACKAGE THERMAL DATA PACKAGE DIMENSIONS IN mm (INCHES) Thermal Data D Lead Count Metric Max Min 10.16 9.02 5.00 4.80 8.75 8.55 8 L PDIP 8 L SOIC Narrow 14L SOIC Narrow English Max Min .400 .355 .197 .189 .344 .337 RΘJC RΘJA typ typ Surface Mount Narrow Body (D); 150 mil wide Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 8L 8L 14 L PDIP SO Narrow SO Narrow 52 45 30 ˚C/W 100 165 125 ˚C/W 8.26 (.325) 7.62 (.300) 1.77 (.070) 1.14 (.045) 2.54 (.100) BSC 3.68 (.145) 2.92 (.115) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 1.75 (.069) MAX .356 (.014) .203 (.008) 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.39 (.015) MIN. .558 (.022) .356 (.014) 0.25 (.010) 0.19 (.008) D REF: JEDEC MS-001 0.25 (0.10) 0.10 (.004) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. REF: JEDEC MS-012 Ordering Information Part Number CS3842BGN8 CS3842BGD8 CS3842BGDR8 CS3842BGD14 CS3842BGDR14 CS3843BGN8 CS3843BGD8 CS3843BGDR8 CS3843BGD14 CS3843BGDR14 Rev. 6/23/99 Description 8L PDIP 8L SO Narrow 8L SO Narrow (tape & reel) 14L SO Narrow 14L SO Narrow (tape & reel) 8L PDIP 8L SO Narrow 8L SO Narrow (tape & reel) 14L SO Narrow 14L SO Narrow (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 6 © 1999 Cherry Semiconductor Corporation