TI BQ24090DGQT

bq24090, bq24091
bq24092, bq24093
www.ti.com
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
1A, Single-Input, Single Cell Li-Ion Battery Charger
Check for Samples: bq24090, bq24091, bq24092, bq24093
FEATURES
APPLICATIONS
•
•
•
•
•
1
•
•
CHARGING
– 1% Charge Voltage Accuracy
– 10% Charge Current Accuracy
– Pin Selectable USB 100mA and 500mA
Maximum Input Current Limit
– Programmable Termination and Precharge
Threshold
PROTECTION
– 6.6V Over-Voltage Protection
– Input Voltage Dynamic Power Management
– 125°C Thermal Regulation; 150°C Thermal
Shutdown Protection
– OUT Short-Circuit Protection and ISET
Short Detection
– Operation Over JEITA Range via Battery
NTC – ½ Fast-Charge-Current at Cold,
4.06V at Hot, bq24092/3
– Fixed 10 Hour Safety Timer
SYSTEM
– Automatic Termination and Timer Disable
Mode (TTDM) for Absent Battery Pack With
Thermistor
– Status Indication – Charging/Done
– Available in Small 10-Pin MSOP Package
Smart Phones
PDAs
MP3 Players
Low-Power Handheld Devices
DESCRIPTION
The bq2409x series of devices are highly integrated
Li-ion linear chargers devices targeted at
space-limited portable applications. The devices
operate from either a USB port or AC adapter. The
high input voltage range with input overvoltage
protection supports low-cost unregulated adapters.
The bq2409x has a single power output that charges
the battery. A system load can be placed in parallel
with the battery as long as the average system load
does not keep the battery from charging fully during
the 10 hour safety timer.
The battery is charged in three phases: conditioning,
constant current and constant voltage. In all charge
phases, an internal control loop monitors the IC
junction temperature and reduces the charge current
if an internal temperature threshold is exceeded.
1.5kW
bq2409x
Adaptor
1 IN
DC+
OUT 10
1.5kW
GND
1mF
1kW
2 ISET
TS 9
3 VSS
CHG 8
System Load
Battery Pack
++
1mF
4 PRETERM ISET2 7
OR
5 PG
NC 6
VDD
2kW
TTDM
USB Port
ISET/100/500mA
VBUS
GND
GND
D+
D+
D-
Disconnect after Detection
D-
Host
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq24090, bq24091
bq24092, bq24093
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
The charger power stage and charge current sense functions are fully integrated. The charger function has high
accuracy current and voltage regulation loops, charge status display, and charge termination. The pre-charge
current and termination current threshold are programmed via an external resistor. The fast charge current value
is also programmable via an external resistor.
ORDERING INFORMATION
PART #
VO(REG)
VOVP
JEITA
TS/CE
PG
PACKAGE
Marking
2
bq24090
4.20 V
6.6 V
No
10kΩ NTC
Yes
10 PIN 5x3mm
bq24090
bq24091
4.20 V
6.6 V
No
100kΩ NTC
Yes
10 PIN 5x3mm2
bq24091
bq24092
4.20 V
6.6 V
Yes
10kΩ NTC
Yes
10 PIN 5x3mm2
bq24092
Yes
2
bq24093
bq24093
4.20 V
6.6 V
Yes
100kΩ NTC
10 PIN 5x3mm
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Input Voltage
VALUE
UNIT
IN (with respect to VSS)
–0.3 to 7
V
OUT (with respect to VSS)
–0.3 to 7
V
PRE-TERM, ISET, ISET2, TS, CHG, PG, ASI, ASO (with respect to
VSS)
–0.3 to 7
V
A
Input Current
IN
1.25
Output Current (Continuous)
OUT
1.25
A
Output Sink Current
CHG
15
mA
TJ
Junction temperature
–40 to 150
°C
TSTG
Storage temperature
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
PACKAGE DISSIPATION RATINGS (1)
(1)
(2)
2
(2)
PACKAGE
RqJA
RqJC
TA ≤ 25°C
POWER RATING
DERATING FACTOR
TA > 25°C
5x3mm MSOP
52°C/W
48°C/W
1.92 W
19.2 mW/°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2×3 via matrix
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24090 bq24091 bq24092 bq24093
bq24090, bq24091
bq24092, bq24093
www.ti.com
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
RECOMMENDED OPERATING CONDITIONS (1)
IN voltage range
VIN
IN operating voltage range, Restricted by VDPM and VOVP
MIN
MAX
3.5
7
UNIT
V
4.45
6.45
V
A
IIN
Input current, IN pin
1.0
IOUT
Current, OUT pin
1.0
A
TJ
Junction temperature
125
°C
RPRE-TERM
Programs precharge and termination current thresholds
RISET
Fast-charge current programming resistor
RTS
10k NTC thermistor range without entering BAT_EN or TTDM
(1)
0
1
10
kΩ
0.675
49.9
kΩ
1.66
258
kΩ
Operation with VIN less than 4.5V or in drop-out may result in reduced performance.
ELECTRICAL CHARACTERISTICS
Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Undervoltage lock-out Exit
VIN: 0V → 4V Update based on sim/char
3.15
3.3
3.45
V
VHYS_UVLO
Hysteresis on VUVLO_RISE falling
VIN: 4V→0V,
VUVLO_FALL = VUVLO_RISE –VHYS-UVLO
175
227
280
mV
VIN-DT
Input power good detection threshold
is VOUT + VIN-DT
(Input power good if VIN > VOUT + VIN-DT);
VOUT = 3.6V, VIN: 3.5V → 4V
30
80
145
mV
VHYS-INDT
Hysteresis on VIN-DT falling
VOUT = 3.6V, VIN: 4V → 3.5V
31
mV
tDGL(PG_PWR)
Deglitch time on exiting sleep.
Time measured from VIN: 0V → 5V 1ms rise-time to
PG = low, VOUT = 3.6V
45
ms
tDGL(PG_NO-
Deglitch time on VHYS-INDT power
down. Same as entering sleep.
Time measured from VIN: 5V → 3.2V 1ms fall-time to
PG = OC, VOUT = 3.6V
29
ms
PWR)
VOVP
Input over-voltage protection threshold
VIN: 5V → 7V
tDGL(OVP-SET)
Input over-voltage blanking time
VIN: 5V → 7V
113
ms
VHYS-OVP
Hysteresis on OVP
VIN: 7V → 5V
95
mV
tDGL(OVP-REC)
Deglitch time exiting OVP
Time measured from VIN: 7V → 5V 1ms fall-time to
PG = LO
30
ms
VIN-DPM
USB/Adaptor low input voltage
protection. Restricts lout at VIN-DPM
UVLO
IIN-USB-CL
6.5
6.65
6.8
Feature active in USB mode; Limit Input Source
Current to 50mA; VOUT = 3.5V; RISET = 825Ω
4.34
4.4
4.46
Feature active in Adaptor mode; Limit Input Source
Current to 50mA; VOUT = 3.5V; RISET = 825Ω
4.24
4.3
4.36
V
V
USB input I-Limit 100mA
ISET2 = Float; RISET = 825Ω
85
92
100
USB input I-Limit 500mA
ISET2 = High; RISET = 825Ω
430
462
500
280
mA
ISET SHORT CIRCUIT TEST
RISET_SHORT
Highest Resistor value considered a
fault (short). Monitored for Iout>90mA
Riset: 600Ω → 250Ω, IOUT latches off. Cycle power to
Reset.
tDGL_SHORT
Deglitch time transition from ISET
short to Iout disable
Clear fault by cycling IN or TS/BAT_EN
IOUT_CL
Maximum OUT current limit Regulation VIN = 5V, VOUT = 3.6V, VISET2 = Low, RISET:
(Clamp)
600Ω → 250Ω, Iout latches off after tDGL-SHORT
500
1
1.05
Ω
ms
1.4
A
0.85
V
BATTERY SHORT PROTECTION
VOUT(SC)
OUT pin short-circuit detection
threshold/ precharge threshold
VOUT:3V → 0.5V, no deglitch
VOUT(SC-HYS)
OUT pin Short hysteresis
Recovery ≥ VOUT(SC) + VOUT(SC-HYS); Rising, no
Deglitch
IOUT(SC)
Source current to OUT pin during
short-circuit detection
Copyright © 2010, Texas Instruments Incorporated
0.75
0.8
77
10
15
mV
20
Submit Documentation Feedback
Product Folder Link(s): bq24090 bq24091 bq24092 bq24093
mA
3
bq24090, bq24091
bq24092, bq24093
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENT
IOUT(PDWN)
Battery current into OUT pin
VIN = 0V
1
IOUT(DONE)
OUT pin current, charging terminated
VIN = 6V, VOUT > VOUT(REG)
6
IIN(STDBY)
Standby current into IN pin
TS = LO, VIN ≤ 6V
ICC
Active supply current, IN pin
TS = open, VIN = 6V, TTDM – no load on OUT pin,
VOUT > VOUT(REG), IC enabled
mA
125
mA
0.8
1.0
mA
BATTERY CHARGER FAST-CHARGE
VOUT(REG)
Battery regulation voltage
VIN = 5.5V, IOUT = 25mA, (VTS-45°C≤ VTS ≤ VTS-0°C)
4.16
4.2
4.23
V
VO_HT(REG)
Battery hot regulation Voltage,
bq24092/3
VIN = 5.5V, IOUT = 25mA, VTS-60°C≤ VTS ≤ VTS-45°C
4.02
4.06
4.1
V
IOUT(RANGE)
Programmed Output “fast charge”
current range
VOUT(REG) > VOUT > VLOWV; VIN = 5V, ISET2=Lo,
RISET = 675 to 10.8kΩ
VDO(IN-OUT)
Drop-Out, VIN – VOUT
Adjust VIN down until IOUT = 0.5A, VOUT = 4.15V,
RISET = 675 , ISET2=Lo (adaptor mode); TJ ≤ 100°C
IOUT
Output “fast charge” formula
VOUT(REG) > VOUT > VLOWV; VIN = 5V, ISET2 = Lo
KISET
Fast charge current factor
10
325
1000
mA
520
mV
KISET/RISET
A
RISET = KISET /IOUT; 50 < IOUT < 800 mA
510
540
565
RISET = KISET /IOUT; 25 < IOUT < 50 mA
480
527
580
RISET = KISET /IOUT; 10 < IOUT < 25 mA
350
520
680
2.4
2.5
2.6
AΩ
PRECHARGE – SET BY PRETERM PIN
VLOWV
Pre-charge to fast-charge transition
threshold
tDGL1(LOWV)
Deglitch time on pre-charge to
fast-charge transition
70
ms
tDGL2(LOWV)
Deglitch time on fast-charge to
pre-charge transition
32
ms
IPRE-TERM
Refer to the Termination Section
%PRECHG
KPRE-CHG
Pre-charge current, default setting
VOUT < VLOWV; RISET = 1080Ω;
RPRE-TERM= High Z
Pre-charge current formula
RPRE-TERM = KPRE-CHG (Ω/%) × %PRE-CHG (%)
% Pre-charge Factor
18
20
22
V
%IOUTCC
RPRE-TERM/KPRE-CHG%
VOUT < VLOWV, VIN = 5V, RPRE-TERM = 2k to 10kΩ;
RISET = 1080Ω , RPRE-TERM = KPRE-CHG × %IFAST-CHG,
where %IFAST-CHG is 20 to 100%
90
100
110
Ω/%
VOUT < VLOWV, VIN = 5V, RPRE-TERM = 1k to 2kΩ;
RISET = 1080Ω, RPRE-TERM = KPRE-CHG × %IFAST-CHG,
where %IFAST-CHG is 10% to 20%
84
100
117
Ω/%
9
10
11
%IOUT-
TERMINATION – SET BY PRE-TERM PIN
Termination Threshold Current, default VOUT > VRCH; RISET = 1k;
setting
RPRE-TERM= High Z
%TERM
KTERM
RPRE-TERM = KTERM (Ω/%) × %TERM (%)
182
% Term Factor
VOUT > VRCH, VIN = 5V, RPRE-TERM = 2k to 10kΩ ;
RISET = 750Ω KTERM × %IFAST-CHG, where %IFAST-CHG
is 10 to 50%
VOUT > VRCH, VIN = 5V, RPRE-TERM = 1k to 2kΩ ; RISET
= 750Ω KTERM × %Iset, where %Iset is 5 to 10%
174
199
224
71
75
81
IPRE-TERM
Current for programming the term. and
pre-chg with resistor. ITerm-Start is the
RPRE-TERM = 2k, VOUT = 4.15V
initial PRE-TERM current.
%TERM
Termination current formula
tDGL(TERM)
Deglitch time, termination detected
ITerm-Start
Elevated PRE-TERM current for,
tTerm-Start, during start of charge to
prevent recharge of full battery,
tTerm-Start
Elevated termination threshold initially
active for tTerm-Start
4
CC
Termination Current Threshold
Formula
RPRE-TERM/ KTERM
200
216
Ω/%
RTERM/ KTERM
Submit Documentation Feedback
%
29
80
85
1.25
mA
ms
92
mA
min
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24090 bq24091 bq24092 bq24093
bq24090, bq24091
bq24092, bq24093
www.ti.com
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
ELECTRICAL CHARACTERISTICS (continued)
Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RECHARGE OR REFRESH
Recharge detection threshold –
Normal Temp
VIN = 5V, VTS = 0.5V, VOUT: 4.25V → VRCH
VO(REG)
-0.120
VO(REG)-0.095
VO(REG)0.070
V
Recharge detection threshold – Hot
Temp
VIN = 5V, VTS = 0.2V, VOUT: 4.15V → VRCH
VO(REG)
-0.130
VO(REG)-0.105
VO(REG)0.080
V
tDGL1(RCH)
Deglitch time, recharge threshold
detected
VIN = 5V, VTS = 0.5V, VOUT: 4.25V → 3.5V in 1ms;
tDGL(RCH) is time to ISET ramp
29
ms
tDGL2(RCH)
Deglitch time, recharge threshold
detected in OUT-Detect Mode
VIN = 5V, VTS = 0.5V, VOUT = 3.5V inserted; tDGL(RCH)
is time to ISET ramp
3.6
ms
VRCH
BATTERY DETECT ROUTINE
VREG-BD
VOUT Reduced regulation during
battery detect
IBD-SINK
Sink current during VREG-BD
tDGL(HI/LOW
REG)
VO(REG)
-0.450
VIN = 5V, VTS = 0.5V, Battery Absent
VO(REG)-0.400
7
Regulation time at VREG or VREG-BD
VO(REG)350
10
25
V
mA
ms
VBD-HI
High battery detection threshold
VIN = 5V, VTS = 0.5V, Battery Absent
VO(REG)
-0.150
VO(REG)-0.100
VO(REG)0.050
V
VBD-LO
Low battery detection threshold
VIN = 5V, VTS = 0.5V, Battery Absent
VREG-BD
+0.50
VREG-BD +0.1
VREG-BD
+0.15
V
BATTERY CHARGING TIMERS AND FAULT TIMERS
tPRECHG
Pre-charge safety timer value
Restarts when entering Pre-charge; Always enabled
when in pre-charge.
1700
1940
2250
s
tMAXCH
Charge safety timer value
Clears fault or resets at UVLO, TS/BAT_EN disable,
OUT Short, exiting LOWV and Refresh
34000
38800
45000
s
BATTERY-PACK NTC MONITOR (Note 1); TS pin: 10k and 100k NTC
INTC-10k
NTC bias current, bq24090/2
VTS = 0.3V
48
50
52
mA
INTC-100k
NTC bias current, bq24091/3
VTS = 0.3V
4.8
5.0
5.2
mA
INTC-DIS-10k
10k NTC bias current when Charging
is disabled, bq24090/2
VTS = 0V
27
30
34
mA
INTC-DIS-100k
10k NTC bias current when Charging
is disabled, bq24091/3
VTS = 0V
4.4
5.0
5.8
mA
INTC-FLDBK-10k
INTC is reduced prior to entering
TTDM to keep cold thermistor from
entering TTDM, bq24090/2
VTS: Set to 1.525V
4
5
6.5
mA
INTC-FLDBK-100k
INTC is reduced prior to entering
TTDM to keep cold thermistor from
entering TTDM, bq24091/3
VTS: Set to 1.525V
1.1
1.5
1.9
mA
VTTDM(TS)
Termination and timer disable mode
Threshold – Enter
VTS: 0.5V → 1.7V; Timer Held in Reset
1550
1600
1650
mV
VHYS-TTDM(TS)
Hysteresis exiting TTDM
VTS: 1.7V → 0.5V; Timer Enabled
VCLAMP(TS)
TS maximum voltage clamp
VTS = Open (Float)
1800
1950
tDGL(TTDM)
100
Deglitch exit TTDM between states
Deglitch enter TTDM between states
VTS_I-FLDBK
TS voltage where INTC is reduce to
keep thermistor from entering TTDM
CTS
Optional Capacitance – ESD
INTC adjustment (90 to 10%; 45 to 6.6uS) takes
place near this spec threshold. VTS: 1.425V →
1.525V
VTS-0°C
Low temperature CHG Pending
Low Temp Charging to Pending;
VTS: 1.0V → 1.5V
VHYS-0°C
Hysteresis at 0°C
Charge pending to low temp charging;
VTS: 1.5V → 1V
VTS-10°C
Low temperature, half charge,
bq24092/3
Normal charging to low temp charging;
VTS: 0.5V → 1V
VHYS-10°C
Hysteresis at 10°C, bq24092/3
Low temp charging to normal CHG;
VTS: 1.0V → 0.5V
VTS-45°C
High temperature at 4.1V
Normal charging to high temp CHG;
VTS: 0.5V → 0.2V
VHYS-45°C
Hysteresis at 45°C
High temp charging to normal CHG;
VTS: 0.2V → 0.5V
Copyright © 2010, Texas Instruments Incorporated
1205
mV
2000
57
ms
8
ms
1475
mV
0.22
mF
1230
1255
86
765
790
278
815
mV
mV
293
10.7
Submit Documentation Feedback
Product Folder Link(s): bq24090 bq24091 bq24092 bq24093
mV
mV
35
263
mV
mV
mV
5
bq24090, bq24091
bq24092, bq24093
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
170
178
186
mV
VTS-60°C
High temperature Disable, bq24092/3
High temp charge to pending;
VTS: 0.2V → 0.1V
VHYS-60°C
Hysteresis at 60°C, bq24092/3
Charge pending to high temp CHG;
VTS: 0.1V → 0.2V
tDGL(TS_10C)
Deglitch for TS thresholds: 10C,
bq24092/3
Normal to Cold Operation; VTS: 0.6V → 1V
50
Cold to Normal Operation; VTS: 1V → 0.6V
12
tDGL(TS)
Deglitch for TS thresholds: 0/45/60C.
Battery charging
VTS-EN-10k
Charge Enable Threshold, (10k NTC)
VTS: 0V → 0.175V;
VTS-DIS_HYS-10k
HYS below VTS-EN-10k to Disable, (10k
NTC)
VTS: 0.125V → 0V;
VTS-EN-100k
Charge Enable Threshold, bq24090/2
VTS: 0V → 0.175V;
VTS-DIS_HYS-
HYS below VTS-EN-100k to Disable,
bq24091/3
VTS: 0.125V → 0V;
100k
11.5
mV
ms
30
80
88
ms
96
12
140
150
mV
mV
160
mV
50
mV
THERMAL REGULATION
TJ(REG)
Temperature regulation limit
125
°C
TJ(OFF)
Thermal shutdown temperature
155
°C
TJ(OFF-HYS)
Thermal shutdown hysteresis
20
°C
LOGIC LEVELS ON ISET2
VIL
Logic LOW input voltage
Sink 8 mA
VIH
Logic HIGH input voltage
Source 8 mA
1.4
IIL
Sink current required for LO
VISET2= 0.4V
2
IIH
Source current required for HI
VISET2= 1.4V
VFLT
ISET2 Float Voltage
V
9
mA
V
1.1
575
0.4
900
8
mA
1225
mV
LOGIC LEVELS ON CHG AND PG
VOL
Output LOW voltage
ISINK = 5 mA
ILEAK
Leakage current into IC
V CHG = 5V, V PG = 5V
6
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0.4
V
1
mA
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24090 bq24091 bq24092 bq24093
bq24090, bq24091
bq24092, bq24093
www.ti.com
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
PIN CONFIGURATION
bq2409x
1 IN
OUT 10
2 ISET
TS 9
3 VSS
CHG 8
4 PRETERM ISET2 7
5 PG
NC 6
PIN FUNCTIONS
NAME
PIN
I/O
DESCRIPTION
IN
1
I
Input power, connected to external DC supply (AC adapter or USB port). Expected range of bypass
capacitors 1mF to 10mF, connect from IN to VSS.
OUT
10
O
Battery Connection. System Load may be connected. Average load should not be excessive, allowing
battery to charge within the 10 hour safety timer window. Expected range of bypass capacitors 1mF to
10mF.
PRE-TERM
4
I
Programs the Current Termination Threshold (5 to 50% of Iout which is set by ISET) and Sets the
Pre-Charge Current to twice the Termination Current Level.
Expected range of programming resistor is 1k to 10kΩ (2k: Ipgm/10 for term; Ipgm/5 for precharge)
ISET
2
I
Programs the Fast-charge current setting. External resistor from ISET to VSS defines fast charge current
value. Range is 10.8k (50mA) to 675 Ω (800mA).
ISET2
7
I
Programming the Input/Output Current Limit for the USB or Adaptor source:
High = 500mAmax, Low = ISET, FLOAT = 100mAmax.
I
Temperature sense pin connected to bq24090/2 -10k at 25°C NTC thermistor & bq24091/3 -100k at
25°C NTC thermistor, in the battery pack. Floating TS Pin or pulling High puts part in TTDM “Charger”
Mode and disable TS monitoring, Timers and Termination. Pulling pin Low disables the IC. If NTC
sensing is not needed, connect this pin to VSS through an external 10 kΩ/100kΩ resistor. A 250kΩ from
TS to ground will prevent IC entering TTDM mode when battery with thermistor is removed.
TS
9
VSS
3
–
Ground terminal
CHG
8
O
Low (FET on) indicates charging and Open Drain (FET off) indicates no Charging or Charge complete.
PG
5
O
Low (FET on) indicates the input voltage is above UVLO and the OUT (battery) voltage.
NC
6
NA
Pad
5x3mm2
–
Thermal PAD
and Package
Do not make a connection to this pin (for internal use) – Do not route through this pin
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the
device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit
board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be
connected to ground at all times
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Typical Application Circuit: bq2409x
IOUT_FAST_CHG = 540mA; IOUT_PRE_CHG = 108mA; IOUT_TERM = 54mA
1.5kW
bq2409x
Adaptor
1 IN
DC+
OUT 10
1.5kW
GND
1mF
1kW
2 ISET
TS 9
3 VSS
CHG 8
System Load
Battery Pack
++
1mF
4 PRETERM ISET2 7
OR
5 PG
NC 6
VDD
2kW
TTDM
USB Port
ISET/100/500 mA
VBUS
GND
GND
D+
D+
D-
8
D-
Disconnect after Detection
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Host
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
Internal Charge
Current Sense
w/ Multiple Outputs
IN
OUT
80 mV
OUT
+
_
Input
Power
Detect
IN
OUT
+
_
+
_
+
-
IN-DPMREF
Charge
Pump
IOUT x 1.5 V
540 AW
OUTREGREF
TJ°C
+
_
FAST CHARGE
125°CREF
PRE-CHARGE
ISET
IN
+
_
1.5V
Pre-CHG Reference
+
_
USB100/500REF
USB Sense
Resistor
o
TJ C
+
_
Term Reference
+
_
150oCREF
Thermal Shutdown
75mA +
Charge
Pump
X2 Gain (1: 2)
Term:Pre-CHGX2
PRE-TERM
Increased from 75mA to 85mA for
1st minute of charge.
IN
+
_
+
OUT
VTERM_EN
CHG
OVPREF
+
_
+
_
ON:
OFF:
ISET2 (LO = ISET, HI = USB500,
0.9V Float
On During
1st Charge Only
CHARGE
CONTROL
FLOAT = USB100)
PG
VCOLD-10 C
o
+
_
o
+
_
VHOT-45 C
HI = Half CHG (JEITA)
HI = 4.06Vreg (JEITA)
VCOLD-FLT
+
_
+
_
VHOT-FLT
LO = TTDM MODE
HI = Suspend CHG
TS
VTTDM
TS - bq24090
VCE
+
_
+
_
HI=CHIP DISABLE
VDISABLE
+
_
Cold Temperature
Sink Current
= 45mA _ VCLAMP = 1.4V
Disable
Sink Current
= 20mA
+
5mA
+
_
45mA
Bq24090 is as shown
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TYPICAL OPERATIONAL CHARACTERISTICS
SETUP: bq2409x typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated)
POWER UP, DOWN, OVP, DISABLE AND ENABLE WAVEFORMS
Vin
Vin
5V/div
5V/div
Vchg
2V/div
2V/div
Vchg
Vpg
2V/div
Vpg
Viset
2V/div
Viset 2V/div
2V/div
t - time - 20ms/div
t - time - 100ms/div
Figure 1. OVP 8V Adaptor - Hot Plug
Figure 2. OVP from Normal Power-up
Operation – VIN 0V → 5V → 6.8V →5V
10kΩ resistor from TS to GND. 10kΩ is shorted to disable the IC.
Fixed 10kΩ resistor, between TS and GND.
Vpg
Vpg
2V/div
5V/div
Vchg
Vchg
2V/div
2V/div
Vout
2V/div
500mV/div
Vts
Battery Detect Mode
Viset
2V/div
Vin
5V/div
t - time - 50ms/div
t - time - 20ms/div
Figure 3. TS Enable and Disable
Figure 4. Hot Plug Source w/No Battery – Battery
Detection
Vout
Vin
1 Battery Detect Cycle
2V/div
Vchg
Vout
500mV/div
Viset
1V/div
5V/div
1V/div
Viset
1V/div
Vts
1V/div
Vts
2V/div
Entered TTDM
t - time - 5ms/div
t - time - 10ms/div
Figure 5. Battery Removal – GND Removed 1st, 42 Ω Load
Figure 6. Battery Removal with OUT and
TS Disconnect 1st, With 100 Ω Load
Continuous battery detection when not in TTDM.
10
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
TYPICAL OPERATIONAL CHARACTERISTICS (continued)
SETUP: bq2409x typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated)
Vout
1V/div
Vchg
Battery Declared Absent
5V/div
Viset
1V/div
V_0.1 W_OUT
100mV/div
t - time - 20ms/div
Figure 7. Battery Removal with fixed TS = 0.5V
PROTECTION CIRCUITS WAVEFORMS
CH4: Iout (1A/Div)
Battery voltage swept from 0V to 4.25V to 3.9V.
CH4: Iout (1A/Div)
1V/div
Vout
Vout
1V/div
Vchg
5V/div
Viset
Battery
Threshold
Reached
1V/div
Vchg 2V/div
500mV/div
IOUT Clamped Current
Viset
V_0.1 W_OUT
V_0.1 W_OUT
100mV/div
100mV/div
ISET Short Detected
and Latched Off
t - time - 500ms/div
Figure 8. Battery Charge Profile
t - time - 200ms/div
Figure 9. ISET Shorted During Normal Operation
CH4: Iout (0.2A/Div)
CH4: Iout (0.2A/Div)
Vchg
Vin
Vin
2V/div
2V/div
Vchg
2V/div
2V/div
500mV/div
Short Detected in 100mA
mode and Latched Off
Viset
Viset
V_0.1W_OUT
20mV/div
500mV/div
V_0.1 W_OUT
20mV/div
t - time - 5ms/div
Figure 10. ISET Shorted Prior to USB Power-up
t - time - 1ms/div
Figure 11. DPM – Adaptor Current Limits – Vin Regulated
The IC temperature rises to 125°C and enters thermal regulation. Charge current is reduced to regulate the IC at
125°C. VIN is reduced, the IC temperature drops, the charge current returns to the programmed value.
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TYPICAL OPERATIONAL CHARACTERISTICS (continued)
SETUP: bq2409x typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated)
Vin
2V/div
Vchg
Vin
Vout
2V/div
1V/div
2V/div
Enters
Thermal
Regulation
Exits
Thermal
Regulation
Viset
1V/div
500mV/div
V_0.1W_OUT
Viset
20mV/div
50mV/div
V_0.1W_OUT
t - time - 500ms/div
t - time - 1s/div
Figure 12. DPM – USB Current Limits – Vin Regulated to
4.4V
Figure 13. Thermal Reg. – Vin increases PWR/Iout
Reduced
VIN swept from 5V to 3.9V to 5V, VBAT = 4V
546
Kiset
544
Vin
1V/div
542
Low to High Currents
(may occur in recharge to fast charge transion)
Kiset - W
540
Viset
1V/div
Vchg
5V/div
Vpg
538
High to Low Currents
(may occur in Voltage Regulation - Taper Current)
536
5V/div
534
t - time - 20ms/div
532
530
528
.15
0
Figure 14. Entering and Exiting Sleep Mode
0.2
0.4
IO - Output Current - A
0.6
0.8
Figure 15. KISET for Low and High Currents
4.212
4.2
VO @ 0°C
ROUT = 100 Ω
4.21
4.199
4.208
4.198
4.206
VOUT - Output Voltage - V
VOUT - Output Voltage DC - V
Vreg @ 25°C
VO @ 25°C
4.204
4.202
VO @ 85°C
4.2
4.195
Vreg @ 0°C
4.194
4.192
5
5.5
VI - Input Voltage DC - V
6
Figure 16. Line Regulation
12
4.196
4.193
4.198
4.196
4.5
Vreg @ 85°C
4.197
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6.5
0
0.2
0.4
0.6
IO - Output current - A
0.8
1
Figure 17. Load Regulation Over Temperature
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
TYPICAL OPERATIONAL CHARACTERISTICS (continued)
SETUP: bq2409x typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated)
363.4
363.2
IO - Output Current - mA
IO @ 25°C
363
362.8
IO @ 85°C
362.6
362.4
362.2
IO @ 0°C
362
361.8
2.5
3
3.5
VO - Output Voltage - V
4
4.5
Figure 18. Current Regulation Over Temperature
FUNCTIONAL GENERAL DESCRIPTION
The bq2409x is a highly integrated family of 5x3mm2 single cell Li-Ion chargers. The charger can be used to
charge a battery, power a system or both. The charger has three phases of charging: Pre-charge to recover a
fully discharged battery, fast-charge constant current to supply the buck charge safely and voltage regulation to
safely reach full capacity. The charger is very flexible, allowing programming of the fast-charge current and
Pre-charge/Termination Current. This charger is designed to work with a USB connection or Adaptor (DC out).
The charger also checks to see if a battery is present.
The charger also comes with a full set of safety features: JEITA Temperature Standard, Over-Voltage Protection,
DPM-IN, Safety Timers, and ISET short protection. All of these features and more are described in detail below.
The charger is designed for a single power path from the input to the output to charge a single cell Li-Ion battery
pack. Upon application of a 5VDC power source the ISET and OUT short checks are performed to assure a
proper charge cycle.
If the battery voltage is below the LOWV threshold, the battery is considered discharged and a preconditioning
cycle begins. The amount of precharge current can be programmed using the PRE-TERM pin which programs a
percent of fast charge current (10 to 100%) as the precharge current. This feature is useful when the system load
is connected across the battery “stealing” the battery current. The precharge current can be set higher to account
for the system loading while allowing the battery to be properly conditioned. The PRE-TERM pin is a dual
function pin which sets the precharge current level and the termination threshold level. The termination "current
threshold" is always half of the precharge programmed current level.
Once the battery voltage has charged to the VLOWV threshold, fast charge is initiated and the fast charge current
is applied. The fast charge constant current is programmed using the ISET pin. The constant current provides the
bulk of the charge. Power dissipation in the IC is greatest in fast charge with a lower battery voltage. If the IC
reaches 125°C the IC enters thermal regulation, slows the timer clock by half and reduce the charge current as
needed to keep the temperature from rising any further. Figure 19 shows the charging profile with thermal
regulation. Typically under normal operating conditions, the IC’s junction temperature is less than 125°C and
thermal regulation is not entered.
Once the cell has charged to the regulation voltage the voltage loop takes control and holds the battery at the
regulation voltage until the current tapers to the termination threshold. The termination can be disabled if desired.
The CHG pin is low (LED on) during the first charge cycle only and turns off once the termination threshold is
reached, regardless if termination, for charge current, is enabled or disabled.
Further details are mentioned in the Operating Modes section.
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FUNCTIONAL GENERAL DESCRIPTION (continued)
VO(REG)
PreConditioning
Phase
Thermal
Regulation
Phase
Current
Regulation
Phase
Voltage Regulation and
Charge Termination
Phase
DONE
IO(OUT)
FAST-CHARGE
CURRENT
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
Battery
Voltage,
V(OUT)
Battery Current,
I(OUT)
Charge
Complete
Status,
Charger
Off
VO(LOWV)
I(TERM)
IO(PRECHG)
T(THREG)
0A
Temperature, Tj
T(PRECHG)
T(CHG)
DONE
Figure 19. Charging Profile With Thermal Regulation
14
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
DETAILED FUNCTIONAL DESCRIPTION
Power-Down or Undervoltage Lockout (UVLO)
The bq2409x family is in power down mode if the IN pin voltage is less than UVLO. The part is considered
“dead” and all the pins are high impedance. Once the IN voltage rises above the UVLO threshold the IC will
enter Sleep Mode or Active mode depending on the OUT pin (battery) voltage.
Under Voltage Lockout (UVLO):
The bq2409x family is in power down mode if the IN pin voltage is less than VUVLO. The part is considered “dead”
and all the pins are high impedance.
Power-up
The IC is alive after the IN voltage ramps above UVLO (see sleep mode), resets all logic and timers, and starts
to perform many of the continuous monitoring routines. Typically the input voltage quickly rises through the
UVLO and sleep states where the IC declares power good, starts the qualification charge at 100mA, sets the
input current limit threshold base on the ISET2 pin, starts the safety timer and enables the CHG pin. See
Figure 20.
Sleep Mode
If the IN pin voltage is between than VOUT+VDT and UVLO, the charge current is disabled, the safety timer
counting stops (not reset) and the PG and CHG pins are high impedance. As the input voltage rises and the
charger exits sleep mode, the PG pin goes low, the safety timer continues to count, charge is enabled and the
CHG pin returns to its previous state. See Figure 21
New Charge Cycle
A new charge cycle is started when a good power source is applied, performing a chip disable/enable (TS pin),
exiting Termination and Timer Disable Mode (TTDM), detecting a battery insertion or the OUT voltage dropping
below the VRCH threshold. The CHG pin is active low only during the first charge cycle, therefore exiting TTDM or
a dropping below VRCH will not turn on the CHG pin FET, if the CHG pin is already high impedance.
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0V
DISHYS
EN
60°C
60°CHYS
45°C
45°CHYS
10°CHYS
10°C
0°CHYS
0°C
LDOHYS
LDO
1.8V
VSS
tDGL(TS)
Disabled
4.06 V
HOT
Operation
tDGL(TS)
Normal
Operation
tDGL(TS)
4.06 V
HOT
Operation
tDGL(TS)
HOT
Fault
tDGL(TS)
Cold
Fault
LDO
Mode
t < tDGL(IS)
Normal
Operation
Cold
Operation
tDGL(TS_IOC)
Falling
tDGL(TS)
tDGL(TTDM)
Exit
Cold
Fault
Drawing Not to Scale
Dots Show Threshold Trip Points
fllowed by a deglitch time before
transitioning into a new mode.
tDGL(TTDM)
Enter
Cold
Operation
tDGL(TS)
Normal
Operation
tDGL(TS_IOC)
Rising
Disabled
Normal
Operation
t
tDGL(TS1_IOC)
Cold to Normal
t < tDGL(TTDM)
Exit
tDGL(TTDM)
Enter
LDO
Mode
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Figure 20. TS Battery Temperature Bias Threshold and Deglitch Timers
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
Apply Input
Power
Is power good?
VBAT +VDT < VIN < VOVP
& VUVLO < VIN
No
Turn on PG FET
PG pin LOW
Yes
Is chip enabled?
VTS > VEN
No
Yes
Set Input Current Limit to 100 mA
and Start Charge
Perform ISET & OUT short tests
Remember ISET2 State
Set charge current
based on ISET2 truth
table.
Return to
Charge
Figure 21. bq2409x Power-Up Flow Diagram
Overvoltage-Protection (OVP) – Continuously Monitored
If the input source applies an overvoltage, the pass FET, if previously on, turns off after a deglitch, tBLK(OVP). The
timer ends and the CHG and PG pin goes to a high impedance state. Once the overvoltage returns to a normal
voltage, the PG pin goes low, timer continues, charge continues and the CHG pin goes low after a 25ms
deglitch. PG pin is optional on some packages
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Power Good Indication (PG)
After application of a 5V source, the input voltage rises above the UVLO and sleep thresholds (VIN>VBAT+VDT),
but is less than OVP (VIN<VOVP,), then the PG FET turns on and provides a low impedance path to ground. See
Figure 1, Figure 2, and Figure 14.
CHG Pin Indication
The charge pin has an internal open drain FET which is on (pulls down to VSS) during the first charge only
(independent of TTDM) and is turned off once the battery reaches voltage regulation and the charge current
tapers to the termination threshold set by the PRE-TERM resistor.
The charge pin is high impedance in sleep mode and OVP (if PG is high impedance) and return to its previous
state once the condition is removed.
Cycling input power, pulling the TS pin low and releasing or entering pre-charge mode causes the CHG pin to go
reset (go low if power is good and a discharged battery is attached) and is considered the start of a first charge.
CHG and PG LED Pull-up Source
For host monitoring, a pull-up resistor is used between the "STATUS" pin and the VCC of the host and for a visual
indication a resistor in series with an LED is connected between the "STATUS" pin and a power source. If the
CHG or PG source is capable of exceeding 7V, a 6.2V Zener should be used to clamp the voltage. If the source
is the OUT pin, note that as the battery changes voltage, the brightness of the LEDs vary.
Charging State
CHG FET/LED
1st Charge
ON
Refresh Charge
OVP
OFF
SLEEP
TEMP FAULT
ON for 1st Charge
VIN Power Good State
PG FET/LED
UVLO
SLEEP Mode
OFF
OVP Mode
Normal Input (VOUT + VDT < VIN <
VOUP)
ON
PG is independent of chip disable
IN-DPM (VIN-DPM or IN–DPM)
The IN-DPM feature is used to detect an input source voltage that is folding back (voltage dropping), reaching its
current limit due to excessive load. When the input voltage drops to the VIN-DPM threshold the internal pass FET
starts to reduce the current until there is no further drop in voltage at the input. This would prevent a source with
voltage less than VIN-DPM to power the out pin. This works well with current limited adaptors and USB ports as
long as the nominal voltage is above 4.3V and 4.4V respectively. This is an added safety feature that helps
protect the source from excessive loads.
OUT
The Charger’s OUT pin provides current to the battery and to the system, if present. This IC can be used to
charge the battery plus power the system, charge just the battery or just power the system (TTDM) assuming the
loads do not exceed the available current. The OUT pin is a current limited source and is inherently protected
against shorts. If the system load ever exceeds the output programmed current threshold, the output will be
discharged unless there is sufficient capacitance or a charged battery present to supplement the excessive load.
18
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ISET
An external resistor is used to Program the Output Current (50 to 800mA) and can be used as a current monitor.
RISET = KISET ÷ IOUT
(1)
(1)
Where:
IOUT is the desired fast charge current;
KISET is a gain factor found in the electrical specification
For greater accuracy at lower currents, part of the sense FET is disabled to give better resolution. Figure 15
shows the transition from low current to higher current. Going from higher currents to low currents, there is
hysteresis and the transition occurs around 0.15A.
The ISET resistor is short protected and will detect a resistance lower than ≉340Ω. The detection requires at
least 80mA of output current. If a “short” is detected, then the IC will latch off and can only be reset by cycling the
power. The OUT current is internally clamped to a maximum current between 1.1A and 1.35A and is independent
of the ISET short detection circuitry, as shown in Figure 23. Also, see Figure 9 and Figure 10.
4.5
o
For < 45 C, 4.2V Regulation
No Operation
During Cold
Fault
3.5
3
60oC to 45oC
HOT TEMP
4.06V
Regulation
VOUT
2.5
< 48oC
1.5
1
0.5
0
0
o
10oC
60oC
Termination
Disable
2
0C
100% of Programmed
Current
} IC Disable
} Hot Fault
Normalized OUT Current and VREG - V
4
50%
Cold
Fault
IOUT
0.2
0.4
0.6
0.8
1
1.2
1.6
1.4
1.8
VTS - Voltage - V
Figure 22. Operation Over TS Bias Voltage
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1.6
1.4
IOUT Clamp min - max
1.8
IO - Output Current - A
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IOUT Fault min - max
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
1.2
IOUT Internal Clamp Range
1
0.8
IOUT Programmed
max
0.6
ISET Short
Fault
Range
min
0.4
0.2
Non Restricted
Operating Area
0
1000
100
10000
ISET - W
Figure 23. Programmed/Clamped Out Current
PRE_TERM – Pre-Charge and Termination Programmable Threshold
Pre-Term is used to program both the pre-charge current and the termination current threshold. The pre-charge
current level is a factor of two higher than the termination current level. The termination can be set between 5%
and 50% of the programmed output current level set by ISET. If left floating the termination and pre-charge are
set internally at 10/20% respectively. The pre-charge-to-fast-charge, Vlowv threshold is set to 2.5V.
RPRE-TERM = %Term × KTERM = %Pre-CHG × KPRE-CHG
(2)
(2)
Where:
%Term is the percent of fast charge current where termination occurs;
%Pre-CHG is the percent of fast charge current that is desired during precharge;
KTERM and KPRE-CHG are gain factors found in the electrical specifications.
ISET2
Is a 3-state input and programs the Input Current Limit/Regulation Threshold. A low will program a regulated fast
charge current via the ISET resistor and is the maximum allowed input/output current for any ISET2 setting, Float
will program a 100mA Current limit and High will program a 500mA Current limit.
Below are two configurations for driving the 3-state ISET2 pin:
VCC
VCC
To
ISET2
R1
To ISET2
Drive
Logic
Q1
OR
Drive
Logic
R1 Divider
set to 0.9 V
Which is the
Float Voltage
R2
Q2
20
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Product Folder Link(s): bq24090 bq24091 bq24092 bq24093
bq24090, bq24091
bq24092, bq24093
www.ti.com
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
TS
The TS pin is designed to follow the new JEITA temperature standard for Li-Ion batteries. There are now four
thresholds, 60°C, 45°C, 10°C, and 0°C. Normal operation occurs between 10°C and 45°C. If between 0°C and
10°C the charge current level is cut in half and if between 45°C and 60°C the regulation voltage is reduced to
4.1Vmax, see Figure 22. The TS feature is implemented using an internal 50mA current source to bias the
thermistor (designed for use with a 10k NTC b = 3370 (SEMITEC 103AT-2 or Mitsubishi TH05-3H103F)
connected from the TS pin to VSS. If this feature is not needed, a fixed 10k can be placed between TS and VSS to
allow normal operation. This may be done if the host is monitoring the thermistor and then the host would
determine when to pull the TS pin low to disable charge.
The TS pin has two additional features, when the TS pin is pulled low or floated/driven high. A low disables
charge (similar to a high on the BAT_EN feature) and a high puts the charger in TTDM.
Above 60°C or below 0°C the charge is disabled. Once the thermistor reaches ≈–10°C the TS current folds back
to keep a cold thermistor (between –10°C and –50°C) from placing the IC in the TTDM mode. If the TS pin is
pulled low into disable mode, the current is reduced to ≈30mA, see Figure 20. Since the ITS current is fixed along
with the temperature thresholds, it is not possible to use thermistor values other than the 10k NTC (at 25°C).
For non-JEITA spins, the operating range is between 0°C and 45°C.
Termination and Timer Disable Mode (TTDM) -TS pin high
The battery charger is in TTDM when the TS pin goes high from removing the thermistor (removing battery
pack/floating the TS pin) or by pulling the TS pin up to the TTDM threshold.
When entering TTDM, the 10 hour safety timer is held in reset and termination is disabled. A battery detect
routine is run to see if the battery was removed or not. If the battery was removed then the CHG pin will go to its
high impedance state if not already there. If a battery is detected the CHG pin does not change states until the
current tapers to the termination threshold, where the CHG pin goes to its high impedance state if not already
there (the regulated output will remain on).
The charging profile does not change (still has pre-charge, fast-charge constant current and constant voltage
modes). This implies the battery is still charged safely and the current is allowed to taper to zero.
When coming out of TTDM, the battery detect routine is run and if a battery is detected, then a new charge cycle
begins and the CHG LED turns on.
If TTDM is not desired upon removing the battery with the thermistor, one can add a 237k resistor between TS
and VSS to disable TTDM. This keeps the current source from driving the TS pin into TTDM. This creates ≈0.1°C
error at hot and a ≈3°C error at cold.
Timers
The pre-charge timer is set to 30 minutes. The pre-charge current, can be programmed to off-set any system
load, making sure that the 30 minutes is adequate.
The fast charge timer is fixed at 10 hours and can be increased real time by going into thermal regulation,
IN-DPM or if in USB current limit. The timer clock slows by a factor of 2, resulting in a clock than counts half as
fast when in these modes. If either the 30 minute or ten hour timer times out, the charging is terminated and the
CHG pin goes high impedance if not already in that state. The timer is reset by disabling the IC, cycling power or
going into and out of TTDM.
Termination
Once the OUT pin goes above VRCH, (reaches voltage regulation) and the current tapers down to the
termination threshold, the CHG pin goes high impedance and a battery detect route is run to determine if the
battery was removed or the battery is full. If the battery is present, the charge current will terminate. If the battery
was removed along with the thermistor, then the TS pin is driven high and the charge enters TTDM. If the battery
was removed and the TS pin is held in the active region, then the battery detect routine will continue until a
battery is inserted.
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
www.ti.com
Battery Detect Routine
The battery detect routine should check for a missing battery while keeping the OUT pin at a useable voltage.
Whenever the battery is missing the CHG pin should be high impedance.
The battery detect routine is run when entering and exiting TTDM to verify if battery is present, or run all the time
if battery is missing and not in TTDM. On power-up, if battery voltage is greater than VRCH threshold, a battery
detect routine is run to determine if a battery is present.
The battery detect routine is disabled while the IC is in TTDM, or has a TS fault. See Figure 24 for the Battery
Detect Flow Diagram.
Refresh Threshold
After termination, if the OUT pin voltage drops to VRCH (100mV below regulation) then a new charge is initiated,
but the CHG pin remains at a high impedance (off).
Starting a Charge on a Full Battery
The termination threshold is raised by ≉14%, for the first minute of a charge cycle so if a full battery is removed
and reinserted or a new charge cycle is initiated, that the new charge terminates (less than 1 minute). Batteries
that have relaxed many hours may take several minutes to taper to the termination threshold and terminate
charge.
22
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bq24092, bq24093
www.ti.com
SLUS968B – JANUARY 2010 – REVISED JUNE 2010
Start
BATT_DETECT
Start 25ms timer
Timer Expired?
No
Yes
Is VOUT<VREG-100mV?
Yes
Battery Present
Turn off Sink Current
Return to flow
No
Set OUT REG
to VREG-400mV
Enable sink current
Reset & Start 25ms timer
Timer Expired?
No
Yes
Yes
Is VOUT>VREG-300mV?
Battery Present
Turn off Sink Current
Return to flow
No
Battery Absent
Don’t Signal Charge
Turn off Sink Current
Return to Flow
Figure 24. Battery Detect Routine
Copyright © 2010, Texas Instruments Incorporated
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
www.ti.com
bq24090 CHARGER APPLICATION DESIGN EXAMPLE
1.5kW
bq24090
Adaptor
1 IN
DC+
OUT 10
1.5kW
GND
2 ISET
TS 9
3 VSS
CHG 8
System Load
Battery Pack
++
1mF
1kW
1mF
4 PRETERM ISET2 7
OR
5 PG
NC 6
VDD
2kW
TTDM
USB Port
ISET/100/500 mA
VBUS
GND
GND
D+
D+
D-
D-
Host
Requirements
• Supply voltage = 5 V
• Fast charge current: IOUT-FC = 540 mA; ISET-pin 2
• Termination Current Threshold: %IOUT-FC = 10% of Fast Charge or ~54mA
• Pre-Charge Current by default is twice the termination Current or ~108mA
• TS – Battery Temperature Sense = 10k NTC (103AT)
Calculations
Program the Fast Charge Current, ISET:
RISET = [K(ISET) / I(OUT)]
from electrical characteristics table. . . K(SET) = 540AΩ
RISET = [540AΩ/0.54A] = 1.0 kΩ
Selecting the closest standard value, use a 1 kΩ resistor between ISET (pin 16) and VSS.
Program the Termination Current Threshold, ITERM:
RPRE-TERM = K(TERM) × %IOUT-FC
RPRE-TERM = 200Ω/% × 10% = 2kΩ
Selecting the closest standard value, use a 2 kΩ resistor between ITERM (pin 15) and Vss.
One can arrive at the same value by using 20% for a pre-charge value (factor of 2 difference).
RPRE-TERM = K(PRE-CHG) × %IOUT-FC
RPRE-TERM = 100Ω/% × 20%= 2kΩ
TS Function
Use a 10k NTC thermistor in the battery pack (103AT).
To Disable the temp sense function, use a fixed 10k resistor between the TS (Pin 1) and Vss.
24
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
CHG and PG
LED Status: connect a 1.5k resistor in series with a LED between the OUT pin and the CHG pin.
Connect a 1.5k resistor in series with a LED between the OUT pin and the and PG pin.
Processor Monitoring: Connect a pull-up resistor between the processor’s power rail and the CHG pin.
Connect a pull-up resistor between the processor’s power rail and the PG pin.
SELECTING IN AND OUT PIN CAPACITORS
In most applications, all that is needed is a high-frequency decoupling capacitor (ceramic) on the power pin, input
and output pins. Using the values shown on the application diagram, is recommended. After evaluation of these
voltage signals with real system operational conditions, one can determine if capacitance values can be adjusted
toward the minimum recommended values (DC load application) or higher values for fast high amplitude pulsed
load applications. Note if designed for high input voltage sources (bad adaptors or wrong adaptors), the capacitor
needs to be rated appropriately. Ceramic capacitors are tested to 2x their rated values so a 16V capacitor may
be adequate for a 30V transient (verify tested rating with capacitor manufacturer).
THERMAL PACKAGE
The bq2409x family is packaged in a thermally enhanced MSOP package. The package includes a thermal pad
to provide an effective thermal contact between the IC and the printed circuit board (PCB). The power pad
should be directly connected to the VSS pin. Full PCB design guidelines for this package are provided in the
application note entitled: Power Pad Thermally Enhanced Package Note (SLMA002). The most common
measure of package thermal performance is thermal impedance (qJA ) measured (or modeled) from the chip
junction to the air surrounding the package surface (ambient). The mathematical expression for qJA is:
qJA = (TJ – T) / P
(3)
(3)
Where:
TJ = chip junction temperature
T = ambient temperature
P = device power dissipation
Factors that can influence the measurement and calculation of qJA include:
1. Whether or not the device is board mounted
2. Trace size, composition, thickness, and geometry
3. Orientation of the device (horizontal or vertical)
4. Volume of the ambient air surrounding the device under test and airflow
5. Whether other surfaces are in close proximity to the device being tested
Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. Typically after fast charge begins the pack voltage
increases to ≉3.4V within the first 2 minutes. The thermal time constant of the assembly typically takes a few
minutes to heat up so when doing maximum power dissipation calculations, 3.4V is a good minimum voltage to
use. This is verified, with the system and a fully discharged battery, by plotting temperature on the bottom of the
PCB under the IC (pad should have multiple vias), the charge current and the battery voltage as a function of
time. The fast charge current will start to taper off if the part goes into thermal regulation.
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged :
P = [V(IN) – V(OUT)] × I(OUT) + [V(OUT) – V(BAT)] × I(BAT)
(3)
The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is
recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage
and nominal ambient temperatures) and use the feature for non typical situations such as hot environments or
higher than normal input source voltage. With that said, the IC will still perform as described, if the thermal loop
is always active.
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SLUS968B – JANUARY 2010 – REVISED JUNE 2010
www.ti.com
Leakage Current Effects on Battery Capacity
To determine how fast a leakage current on the battery will discharge the battery is an easy calculation. The time
from full to discharge can be calculated by dividing the Amp-Hour Capacity of the battery by the leakage current.
For a 0.75AHr battery and a 10mA leakage current (750mAHr/0.010mA = 75000 Hours), it would take 75k hours
or 8.8 years to discharge. In reality the self discharge of the cell would be much faster so the 10mA leakage
would be considered negligible.
Layout Tips
To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2409x, with short
trace runs to both IN, OUT and GND (thermal pad).
• All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces
• The bq2409x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad
to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal pad is
also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. It is
best to use multiple 10mil vias in the power pad of the IC and in close proximity to conduct the heat to the
bottom ground plane. The bottom ground place should avoid traces that “cut off” the thermal path. The thinner
the PCB the less temperature rise. The EVM PCB has a thickness of 0.031 inches and uses 2 oz. (2.8mil
thick) copper on top and bottom, and is a good example of optimal thermal performance.
SPACER
REVISION HISTORY
Changes from Original (January 2010) to Revision A
Page
•
Changed VDO(IN-OUT), MAX value From: 500 mV To: 520 mV in the Elect Characteristics table .......................................... 4
•
Changed IPRE-TERM MAX value From: 79 µA to 81µA in the Elect Characteristics table ....................................................... 4
•
Changed VCLAMP(TS) MIN value From: 1900 mV to 1800 mV in the Elect Characteristics table ........................................... 5
Changes from Revision A (February 2010) to Revision B
Page
•
Changed the device number on the front page circuit From: bq24090 To: bq2409x ........................................................... 1
•
Changed the ORDERING INFORMATION table Marking column From: Product Preview To: bq24092 and bq24093 ...... 2
26
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
BQ24090DGQR
ACTIVE
MSOPPowerPAD
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
BQ24090DGQT
ACTIVE
MSOPPowerPAD
DGQ
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
BQ24091DGQR
ACTIVE
MSOPPowerPAD
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
BQ24091DGQT
ACTIVE
MSOPPowerPAD
DGQ
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
BQ24092DGQR
ACTIVE
MSOPPowerPAD
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
BQ24092DGQT
ACTIVE
MSOPPowerPAD
DGQ
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
BQ24093DGQR
ACTIVE
MSOPPowerPAD
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
BQ24093DGQT
ACTIVE
MSOPPowerPAD
DGQ
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2010
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24090DGQR
MSOPPower
PAD
DGQ
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
BQ24090DGQT
MSOPPower
PAD
DGQ
10
250
180.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
BQ24091DGQR
MSOPPower
PAD
DGQ
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
BQ24091DGQT
MSOPPower
PAD
DGQ
10
250
180.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
BQ24092DGQR
MSOPPower
PAD
DGQ
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24090DGQR
MSOP-PowerPAD
DGQ
10
2500
346.0
346.0
35.0
BQ24090DGQT
MSOP-PowerPAD
DGQ
10
250
203.0
203.0
35.0
BQ24091DGQR
MSOP-PowerPAD
DGQ
10
2500
346.0
346.0
35.0
BQ24091DGQT
MSOP-PowerPAD
DGQ
10
250
203.0
203.0
35.0
BQ24092DGQR
MSOP-PowerPAD
DGQ
10
2500
346.0
346.0
35.0
Pack Materials-Page 2
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