DS1232LP/LPS DS1232LP/LPS Low Power MicroMonitor Chip FEATURES PIN ASSIGNMENT • Super low-power version of DS1232 • 50 A quiescent current • Halts and restarts an out–of–control microprocessor • Automatically restarts microprocessor after power failure • Monitors pushbutton for external override • Accurate 5% or 10% microprocessor power supply PBRST 1 8 VCC TD 2 7 ST TOL 3 6 RST GND 4 5 RST DS1232LP 8–Pin DIP (300 Mil) See Mech. Drawings Section monitoring • 8–pin DIP, 8–pin SOIC or space saving µ–SOP package available • Optional 16–pin SOIC package available • Industrial temperature –40°C to +85°C available, designated N PBRST TD TOL GND NC 1 16 PBRST 2 15 NC 3 TD 4 5 14 13 NC TOL 12 6 NC 7 11 10 GND 8 9 NC VCC NC ST NC RST NC RST DS1232LPS 16–Pin SOIC (300 Mil) See Mech. Drawings Section 1 2 8 7 VCC ST PBRST 1 2 8 VCC TD 7 ST 3 4 6 5 RST RST TOL 3 6 RST GND 4 5 RST DS1232LPµ (118 MIL µ–SOP) See Mech. Drawings Section DS1232LPS–2 8–Pin SOIC (150 Mil) See Mech. Drawings Section PIN DESCRIPTION PBRST TD TOL GND RST RST ST VCC – – – – – – – – Pushbutton Reset Input Time Delay Set Selects 5% or 10% VCC Detect Ground Reset Output (Active High) Reset Output (Active Low, open drain) Strobe Input +5 Volt Power DESCRIPTION The DS1232LP/LPS Low Power MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply, software execution, and external override. First, a precision temperature–compensated reference and comparator circuit monitors the status of VCC. When an out–of–tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize. The second function the DS1232LP/LPS performs is pushbutton reset control. The DS1232LP/LPS debounces the pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a watchdog timer. The DS1232LP/LPS has an internal timer that forces the reset signals to the active state if 062698 1/7 DS1232LP/LPS the strobe input is not driven low prior to time–out. The watchdog timer function can be set to operate on timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds. signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level. OPERATION – WATCHDOG TIMER OPERATION – POWER MONITOR The DS1232LP/LPS detects out–of–tolerance power supply conditions and warns a processor–based system of impending power failure. When VCC falls below a preset level as defined by TOL, the VCC comparator outputs the signals RST and RST. When TOL is connected to ground, the RST and RST signals become active as VCC falls below 4.75 volts. When TOL is connected to VCC, the RST and RST signals become active as VCC falls below 4.5 volts. The RST and RST are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid VCC. On power–up, RST and RST are kept active for a minimum of 250 ms to allow the power supply and processor to stabilize. OPERATION – PUSHBUTTON RESET The DS1232LP/LPS provides an input pin for direct connection to a pushbutton (Figure 1). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that RST and RST The watchdog timer function forces RST and RST signals to the active state when the ST input is not stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to VCC. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive. If a high–to–low transition occurs on the ST input pin prior to time–out, the watchdog timer is reset and begins to time–out again. If the watchdog timer is allowed to time-out, then the RST and RST signals are driven to the active state for 250 ms minimum. The ST input can be derived from microprocessor address signals, data signals, and/or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to time–out. To guarantee that the watchdog timer does not time–out, a high–to– low transition must occur at or less than the minimum shown in Table 1. A typical circuit example is shown in Figure 2. MICROMONITOR BLOCK DIAGRAM ST RST VCC TOL VCC TOLERANCE BIAS + – DIGITAL SAMPLER DIGITAL DELAY RST T.C. REFERENCE PBRST LEVEL SENSE AND DEBOUNCE TD VOLTAGE SENSE 062698 2/7 TIME–OUT COMPARATOR DS1232LP/LPS PUSHBUTTON RESET Figure 1 +5 VDC PBRST VCC +5 VDC ST TD TOL ALE DS1232 LP/LPS RST GND RST RST 8051 P WATCHDOG TIMER Figure 2 +5 VDC PBRST VCC ST TD TOL DS1232 LP/LPS MREQ RST GND RST 10K Z80 RST ADDRESS BUS DECODER 062698 3/7 DS1232LP/LPS TIMING DIAGRAM: PUSHBUTTON RESET Figure 3 tPDLY PBRST tPB VIH VIL tRST RST VOH VOL RST TIMING DIAGRAM: STROBE INPUT Figure 4 INVALID STROBE INDETERMINATE STROBE VALID STROBE ST MIN. MAX. tTD RST WATCHDOG TIME–OUTS Table 1 TIME–OUT 062698 4/7 TD MIN TYP MAX GND 62.5 ms 150 ms 250 ms Float 250 ms 600 ms 1000 ms VCC 500 ms 1200 ms 2000 ms DS1232LP/LPS TIMING DIAGRAM: POWER DOWN Figure 5 tF VCC 4.75V VCCTP 4.25V RST tRPD VOH RST VOL TIMING DIAGRAM: POWER UP Figure 6 tR 4.75V 4.25V VCCTP VCC tRPU RST VOH RST VOL 062698 5/7 DS1232LP/LPS ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Pin Relative to Ground Voltage on I/O Relative to Ground Operating Temperature Operating Temperature (Industrial Version) Storage Temperature Soldering Temperature –0.5V to +7.0V –0.5V to VCC + 0.5V 0°C to 70°C –40°C to +85°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage VCC 4.5 5.0 5.5 V 1 ST and PBRST Input High Level VIH 2.0 VCC+0.3 V 1 ST and PBRST Input Low Level VIL –0.3 +0.8 V 1 DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V) PARAMETER SYMBOL MIN Input Leakage IIL –1.0 Output Current @ 2.4V IOH –8 Output Current @ 0.4V IOL 10 Low Level @ RST VOL Output Voltage @ –500 uA VOH Operating Current (CMOS) ICC1 Operating Current (TTL) ICC2 TYP MAX UNITS NOTES +1.0 µA 3 mA 5 –10 mA 0.4 VCC –0.5V V 1 V 1, 7 50 µA 2 200 500 µA 8 VCC –0.1V VCC Trip Point (TOL = GND) VCCTP 4.50 4.62 4.74 V 1 VCC Trip Point (TOL = VCC) VCCTP 4.25 4.37 4.49 V 1 CAPACITANCE PARAMETER Input Capacitance Output Capacitance 062698 6/7 (tA = 25°C) SYMBOL MAX UNITS CIN MIN TYP 5 pF COUT 7 pF NOTES DS1232LP/LPS AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5V + 10%) PARAMETER SYMBOL MIN PBRST = VIL tPB 20 RESET Active Time tRST 250 ST Pulse Width tST 20 VCC Fail Detect to RST and RST VCC Slew Rate 4.75V to 4.25V VCC Detect to RST and RST Inactive VCC Slew Rate 4.25V to 4.75V PBRST Stable Low to RST and RST TYP MAX 610 1000 tRPU 250 tR 0 ms ns 50 300 NOTES ms tRPD tF UNITS 175 6, 9 µs µs 610 1000 tPDLY ms 4 ns 20 ms NOTES: 1. All voltages referenced to ground. 2. Measured with outputs open and ST and PBRST within 0.5V of supply rails. 3. PBRST is internally pulled up to VCC with an internal impedance of 40K typical. 4. tR = 5 µs. 5. RST is an open drain output. 6. Must not exceed tTD minimum. See Table 1. 7. RST remains within 0.5V of VCC on power–down until VCC drops below 2.0V. RST remains within 0.5V of GND on power–down until VCC drops below 2.0V. 8. Measured with outputs open and ST and PBRST at TTL levels. 9. Watchdog can not be disabled. It must be strobed to avoid resets. MARKING INFORMATION: 8–pin DIP – “DS1232L” 16–pin SOIC – “DS1232L” 8–pin SOIC – “DS1232L” 8–pin µ–SOP – “1232” 062698 7/7