DALLAS DS21455

DS21455/DS21458
Quad T1/E1/J1 Transceivers
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS21455 and DS21458 are quad monolithic
devices featuring independent transceivers that
can be software configured for T1, E1, or J1
operation. Each is composed of a line interface
unit (LIU), framer, HDLC controllers, and a
TDM backplane interface, and is controlled via
an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21455* is a
direct replacement for the older DS21Q55 quad
MCM device. The DS21458, in a smaller
package (17mm CSBGA) and featuring an
improved controller interface, is software
compatible with the older DS21Q55.
Four Independent Transceivers, Each Having
the Following Features:
§ Complete T1 (DS1)/ISDN-PRI/J1
Transceiver Functionality
§ Complete E1 (CEPT) PCM-30/ISDNPRI Transceiver Functionality
§ Short- and Long-Haul Line Interface for
Clock/Data Recovery and Waveshaping
§ CMI Coder/Decoder
§ Crystal-Less Jitter Attenuator
§ Fully Independent Transmit and Receive
Functionality
§ Dual HDLC Controllers
§ On-Chip Programmable BERT Generator
and Detector
§ Internal Software-Selectable Receiveand Transmit-Side Termination Resistors
for 75Ω/100Ω/120Ω T1 and E1
Interfaces
§ Dual Two-Frame Elastic-Store Slip
Buffers that can Connect to
Asynchronous Backplanes Up to
16.384MHz
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
§ Programmable Output Clocks for
Fractional T1, E1, H0, and H12
Applications
§ Interleaving PCM Bus Operation
§ 8-Bit Parallel Control Port, Multiplexed
or Nonmultiplexed, Intel or Motorola
§ IEEE 1149.1 JTAG-Boundary Scan
§ 3.3V Supply with 5V Tolerant Inputs and
Outputs
§ DS21455 Directly Replaces DS21Q55
§ Signaling System 7 (SS7) Support
§ RAI-CI, AIS-CI Support
*The JTAG function on the DS21455/DS21458 is a single
controller for all four transceivers, unlike the DS21Q55, which has
a JTAG controller-per-transceiver architecture.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
ORDERING INFORMATION
PART
DS21455
DS21455N
DS21458
DS21458N
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
256 BGA
(27mm x 27mm)
256 BGA
(27mm x 27mm)
256 CSBGA
(17mm x 17mm)
256 CSBGA
(17mm x 17mm)
DALLAS is a registered trademark of Dallas Semiconductor Corp.
MAXIM is a registered trademark of Maxim Integrated Products, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 040804
DS21455/DS21458 Quad T1/E1/J1 Transceivers
DOCUMENT REVISION HISTORY
REVISION
040804
CHANGES
New Product Release.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
TABLE OF CONTENTS
1.
DESCRIPTION ................................................................................................................................................9
STANDARDS ...................................................................................................................... 10
2.
FEATURE HIGHLIGHTS...............................................................................................................................11
2.1
GENERAL .......................................................................................................................... 11
2.2
LINE INTERFACE ................................................................................................................ 11
2.3
CLOCK SYNTHESIZER ........................................................................................................ 11
2.4
JITTER ATTENUATOR ......................................................................................................... 12
2.5
FRAMER/FORMATTER ........................................................................................................ 12
2.6
SYSTEM INTERFACE........................................................................................................... 13
2.7
HDLC CONTROLLERS ....................................................................................................... 13
2.8
TEST AND DIAGNOSTICS .................................................................................................... 13
2.9
EXTENDED SYSTEM INFORMATION BUS .............................................................................. 14
2.10 CONTROL PORT ................................................................................................................ 14
3.
BLOCK DIAGRAM ........................................................................................................................................15
4.
DS21455/DS21458 DELTA ...........................................................................................................................17
4.1
PACKAGE .......................................................................................................................... 17
4.2
CONTROLLER INTERFACE................................................................................................... 17
4.3
ESIB FUNCTION ................................................................................................................ 17
4.4
FRAMER/LIU INTERIM SIGNALS .......................................................................................... 17
5.
PIN FUNCTION DESCRIPTION....................................................................................................................20
5.1
TRANSMIT SIDE PINS ......................................................................................................... 20
5.2
RECEIVE SIDE PINS ........................................................................................................... 22
5.3
PARALLEL CONTROL PORT PINS ........................................................................................ 24
5.4
EXTENDED SYSTEM INFORMATION BUS .............................................................................. 26
5.5
JTAG TEST ACCESS PORT PINS ........................................................................................ 26
5.6
LINE INTERFACE PINS ........................................................................................................ 27
5.7
SUPPLY PINS .................................................................................................................... 28
5.8
PIN DESCRIPTIONS ............................................................................................................ 29
5.9
PACKAGES ........................................................................................................................ 39
6.
PARALLEL PORT .........................................................................................................................................41
6.1
REGISTER MAP ................................................................................................................. 41
7.
SPECIAL PER-CHANNEL REGISTER OPERATION ..................................................................................46
8.
PROGRAMMING MODEL.............................................................................................................................48
8.1
POWER-UP SEQUENCE ...................................................................................................... 49
8.1.1
Master Mode Register........................................................................................................49
8.2
INTERRUPT HANDLING ....................................................................................................... 50
8.3
STATUS REGISTERS .......................................................................................................... 50
8.4
INFORMATION REGISTERS .................................................................................................. 51
8.5
INTERRUPT INFORMATION REGISTERS ................................................................................ 51
9.
CLOCK MAP .................................................................................................................................................52
10.
T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................53
10.1 T1 CONTROL REGISTERS .................................................................................................. 53
10.2 T1 TRANSMIT TRANSPARENCY ........................................................................................... 58
10.3 AIS-CI AND RAI-CI GENERATION AND DETECTION ............................................................. 59
10.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION ................................................. 60
10.5 T1 INFORMATION REGISTER............................................................................................... 62
11.
E1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................64
11.1 E1 CONTROL REGISTERS .................................................................................................. 64
11.2 AUTOMATIC ALARM GENERATION ....................................................................................... 68
11.2.1
Auto AIS ...........................................................................................................................68
11.2.2
Auto RAI ...........................................................................................................................68
11.2.3
Auto E-Bit .........................................................................................................................68
11.2.4
G.706 CRC-4 Interworking ............................................................................................68
11.3 E1 INFORMATION REGISTERS ............................................................................................ 69
12.
COMMON CONTROL AND STATUS REGISTERS.....................................................................................71
1.1
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
13.
I/O PIN CONFIGURATION OPTIONS ..........................................................................................................78
14.
LOOPBACK CONFIGURATIONS ................................................................................................................80
14.1 PER-CHANNEL PAYLOAD LOOPBACK .................................................................................. 83
15.
ERROR COUNT REGISTERS......................................................................................................................85
15.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) ............................................................ 86
15.1.1
T1 Operation....................................................................................................................86
15.1.2
E1 Operation....................................................................................................................86
15.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) .......................................................... 88
15.2.1
T1 Operation....................................................................................................................88
15.2.2
E1 Operation....................................................................................................................88
15.3 FRAMES OUT OF SYNC COUNT REGISTER (FOSCR) .......................................................... 89
15.3.1
T1 Operation....................................................................................................................89
15.3.2
E1 Operation....................................................................................................................89
15.4 E-BIT COUNTER REGISTER (EBCR)................................................................................... 90
16.
DS0 MONITORING FUNCTION ...................................................................................................................91
16.1 TRANSMIT DS0 MONITOR REGISTERS ................................................................................ 91
16.2 RECEIVE DS0 MONITOR REGISTERS .................................................................................. 92
17.
SIGNALING OPERATION ............................................................................................................................93
17.1 RECEIVE SIGNALING .......................................................................................................... 93
17.1.1
Processor-Based Receive Signaling............................................................................94
17.1.2
Hardware-Based Receive Signaling ............................................................................94
17.2 TRANSMIT SIGNALING ...................................................................................................... 100
17.2.1
Processor-Based Transmit Signaling ........................................................................100
17.2.2
Software Signaling Insertion Enable Registers, E1 CAS Mode.............................104
17.2.3
Software Signaling Insertion Enable Registers, T1 Mode ......................................106
18.
PER-CHANNEL IDLE CODE GENERATION ............................................................................................108
18.1 IDLE CODE PROGRAMMING EXAMPLES ............................................................................. 109
19.
CHANNEL BLOCKING REGISTERS.........................................................................................................113
20.
ELASTIC STORES OPERATION...............................................................................................................116
20.1 RECEIVE SIDE ................................................................................................................. 119
20.1.1
T1 Mode .........................................................................................................................119
20.1.2
E1 Mode .........................................................................................................................119
20.2 TRANSMIT SIDE ............................................................................................................... 120
20.2.1
T1 Mode .........................................................................................................................120
20.2.2
E1 Mode .........................................................................................................................120
20.3 ELASTIC STORES INITIALIZATION ...................................................................................... 120
20.4 MINIMUM-DELAY MODE ................................................................................................... 121
21.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................................122
22.
T1 BIT ORIENTED CODE (BOC) CONTROLLER.....................................................................................123
22.1 TRANSMIT BOC............................................................................................................... 123
22.2 RECEIVE BOC................................................................................................................. 123
23.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) ........................................127
23.1 HARDWARE SCHEME (METHOD 1) .................................................................................... 127
23.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (METHOD 2) ............................. 127
23.3 INTERNAL REGISTER SCHEME BASED ON CRC-4 MULTIFRAME (METHOD 3)...................... 130
24.
HDLC CONTROLLERS ..............................................................................................................................141
24.1 BASIC OPERATION DETAILS ............................................................................................. 141
24.2 HDLC CONFIGURATION ................................................................................................... 143
24.2.1
FIFO Control ..................................................................................................................145
24.3 HDLC MAPPING.............................................................................................................. 146
24.3.1
Receive...........................................................................................................................146
24.3.2
Transmit .........................................................................................................................148
24.3.3
FIFO Information ...........................................................................................................153
24.3.4
Receive Packet Bytes Available .................................................................................153
24.3.5
HDLC FIFOS .................................................................................................................154
24.4 RECEIVE HDLC CODE EXAMPLE...................................................................................... 155
24.5 LEGACY FDL SUPPORT (T1 MODE) ................................................................................. 155
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.5.1
Receive Section ............................................................................................................155
24.5.2
Transmit Section ...........................................................................................................157
24.6 D4/SLC–96 OPERATION ................................................................................................. 157
25.
LINE INTERFACE UNIT (LIU) ....................................................................................................................158
25.1 LIU OPERATION .............................................................................................................. 159
25.2 LIU RECEIVER ................................................................................................................ 159
25.2.1
Receive Level Indicator................................................................................................160
25.2.2
Receive G.703 Section 10 Synchronization Signal .................................................160
25.2.3
Monitor Mode.................................................................................................................160
25.3 LIU TRANSMITTER ........................................................................................................... 161
25.3.1
Transmit Short-Circuit Detector/Limiter .....................................................................161
25.3.2
Transmit Open-Circuit Detector ..................................................................................161
25.3.3
Transmit BPV Error Insertion ......................................................................................162
25.3.4
Transmit G.703 Section 10 Synchronization Signal (E1 Mode).............................162
25.4 MCLK PRESCALER ......................................................................................................... 162
25.5 JITTER ATTENUATOR ....................................................................................................... 162
25.6 CMI (CODE MARK INVERSION) OPTION ............................................................................ 163
25.7 LIU CONTROL REGISTERS ............................................................................................... 164
25.8 RECOMMENDED CIRCUITS................................................................................................ 173
25.9 COMPONENT SPECIFICATIONS.......................................................................................... 175
26.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................................179
27.
BERT FUNCTION .......................................................................................................................................186
27.1 BERT REGISTER DESCRIPTION ....................................................................................... 187
27.2 BERT REPETITIVE PATTERN SET..................................................................................... 192
27.3 BERT BIT COUNTER ....................................................................................................... 193
27.4 BERT ERROR COUNTER ................................................................................................. 194
28.
PAYLOAD ERROR INSERTION FUNCTION ............................................................................................195
28.1 NUMBER OF ERROR REGISTERS ...................................................................................... 197
28.1.1
Number Of Errors Left Register ..................................................................................198
29.
INTERLEAVED PCM BUS OPERATION ...................................................................................................199
29.1 CHANNEL INTERLEAVE MODE ........................................................................................... 199
29.2 FRAME INTERLEAVE MODE ............................................................................................... 199
30.
EXTENDED SYSTEM INFORMATION BUS (ESIB) ..................................................................................202
31.
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER .....................................................................208
32.
FRACTIONAL T1/E1 SUPPORT ................................................................................................................209
33.
USER-PROGRAMMABLE OUTPUT PINS ................................................................................................210
34.
TRANSMIT FLOW DIAGRAMS..................................................................................................................211
35.
JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT .............................................216
35.1 INSTRUCTION REGISTER .................................................................................................. 220
35.2 TEST REGISTERS............................................................................................................. 222
35.3 BOUNDARY SCAN REGISTER ............................................................................................ 222
35.4 BYPASS REGISTER .......................................................................................................... 222
35.5 IDENTIFICATION REGISTER ............................................................................................... 222
36.
FUNCTIONAL TIMING DIAGRAMS...........................................................................................................228
36.1 T1 MODE ........................................................................................................................ 228
36.2 E1 MODE ........................................................................................................................ 238
37.
OPERATING PARAMETERS.....................................................................................................................251
38.
AC TIMING PARAMETERS AND DIAGRAMS..........................................................................................253
38.1 MULTIPLEXED BUS AC CHARACTERISTICS ........................................................................ 253
38.2 NONMULTIPLEXED BUS AC CHARACTERISTICS ................................................................. 256
38.3 RECEIVE SIDE AC CHARACTERISTICS .............................................................................. 259
38.4 TRANSMIT AC CHARACTERISTICS .................................................................................... 265
39.
PACKAGE INFORMATION ........................................................................................................................269
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
LIST OF FIGURES
Figure 3-1. DS21458 Block Diagram ......................................................................................................................... 15
Figure 3-2. DS21455 Block Diagram ......................................................................................................................... 16
Figure 4-1. DS21455 Framer/LIU Interim Signals ..................................................................................................... 18
Figure 4-2. DS21458 Framer/LIU Interim Signals ..................................................................................................... 19
Figure 5-1. DS21455 Pin Diagram, 27mm BGA........................................................................................................ 39
Figure 5-2. DS21458 Pin Diagram, 17mm CSBGA................................................................................................... 40
Figure 8-1. Programming Sequence.......................................................................................................................... 48
Figure 9-1. Clock Map ............................................................................................................................................... 52
Figure 14-1. Normal Signal Flow Diagram ................................................................................................................ 80
Figure 17-1. Simplified Diagram of Receive Signaling Path...................................................................................... 93
Figure 17-2.Simplified Diagram of Transmit Signaling Path.................................................................................... 100
Figure 21-1. CRC-4 Recalculate Method ................................................................................................................ 122
Figure 25-1. Basic Balanced Network Connections ................................................................................................ 158
Figure 25-2. Basic Unbalanced Network Connections ............................................................................................ 159
Figure 25-3. Typical Monitor Application ................................................................................................................. 160
Figure 25-4. CMI Coding ......................................................................................................................................... 163
Figure 25-5. Basic Interface..................................................................................................................................... 173
Figure 25-6. Protected Interface Using Internal Receive Termination .................................................................... 174
Figure 25-7. E1 Transmit Pulse Template ............................................................................................................... 176
Figure 25-8. T1 Transmit Pulse Template ............................................................................................................... 176
Figure 25-9. Jitter Tolerance.................................................................................................................................... 177
Figure 25-10. Jitter Attenuation (T1 Mode).............................................................................................................. 177
Figure 25-11. Jitter Attenuation (E1 Mode) ............................................................................................................. 178
Figure 29-1. IBO Example ....................................................................................................................................... 201
Figure 30-1. DS21455 ESIB Group ......................................................................................................................... 203
Figure 30-2. DS21458 ESIB Group ......................................................................................................................... 204
Figure 34-1. T1 Transmit Data Flow ........................................................................................................................ 211
Figure 34-2. T1 Transmit Data Flow (continued) ..................................................................................................... 212
Figure 34-3. E1 Transmit Data Flow........................................................................................................................ 213
Figure 34-4. E1 Transmit Data Flow (continued)..................................................................................................... 214
Figure 34-5. E1 Transmit Data Flow (continued)..................................................................................................... 215
Figure 35-1. JTAG Functional Block Diagram ......................................................................................................... 216
Figure 35-2. TAP Controller State Diagram............................................................................................................. 219
Figure 36-1. Receive Side D4 Timing...................................................................................................................... 228
Figure 36-2. Receive Side ESF Timing ................................................................................................................... 229
Figure 36-3. Receive Side Boundary Timing (With Elastic Store Disabled)............................................................ 230
Figure 36-4. Receive Side 1.544MHz Boundary Timing (With Elastic Store Enabled) ........................................... 231
Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ........................................... 232
Figure 36-6. Transmit Side D4 Timing..................................................................................................................... 233
Figure 36-7. Transmit Side ESF Timing .................................................................................................................. 234
Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled)........................................................... 235
Figure 36-9. Transmit Side 1.544MHz Boundary Timing (With Elastic Store Enabled) .......................................... 236
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-10. Transmit Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ........................................ 237
Figure 36-11. Receive Side Timing ......................................................................................................................... 238
Figure 36-12. Receive Side Boundary Timing (With Elastic Store Disabled).......................................................... 239
Figure 36-13. Receive Side Boundary Timing, RSYSCLK = 1.544MHz (With Elastic Store Enabled) ................... 240
Figure 36-14. Receive Side Boundary Timing, RSYSCLK = 2.048MHz (With Elastic Store Enabled) .................. 241
Figure 36-15. Receive IBO Channel Interleave Mode Timing................................................................................. 242
Figure 36-16. Receive IBO Frame Interleave Mode Timing.................................................................................... 243
Figure 36-17. G.802 Timing, E1 Mode Only............................................................................................................ 244
Figure 36-18. Transmit Side Timing ........................................................................................................................ 245
Figure 36-19. Transmit Side Boundary Timing (With Elastic Store Disabled)......................................................... 246
Figure 36-20. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz (With Elastic Store Enabled) ................. 247
Figure 36-21. Transmit Side Boundary Timing, TSYSCLK = 2.048MHz (With Elastic Store Enabled) .................. 248
Figure 36-22. Transmit IBO Channel Interleave Mode Timing................................................................................ 249
Figure 36-23. Transmit IBO Frame Interleave Mode Timing................................................................................... 250
Figure 38-1. Intel Bus Read Timing (BTS = 0 / MUX = 1) ....................................................................................... 254
Figure 38-2. Intel Bus Write Timing (BTS = 0 / MUX = 1) ....................................................................................... 254
Figure 38-3. Motorola Bus Timing (BTS = 1 / MUX = 1).......................................................................................... 255
Figure 38-4. Intel Bus Read Timing (BTS = 0 / MUX = 0) ....................................................................................... 257
Figure 38-5. Intel Bus Write Timing (BTS = 0 / MUX = 0) ....................................................................................... 257
Figure 38-6. Motorola Bus Read Timing (BTS = 1 / MUX = 0) ................................................................................ 258
Figure 38-7. Motorola Bus Write Timing (BTS = 1 / MUX = 0) ................................................................................ 258
Figure 38-8. Receive Side Timing, Elastic Store Disabled (T1 Mode) .................................................................... 260
Figure 38-9. Receive Side Timing, Elastic Store Disabled (E1 Mode) .................................................................... 261
Figure 38-10. Receive Side Timing, Elastic Store Enabled (T1 Mode) ................................................................... 262
Figure 38-11. Receive Side Timing, Elastic Store Enabled (E1 Mode)................................................................... 263
Figure 38-12. Receive Line Interface Timing........................................................................................................... 264
Figure 38-13. Transmit Side Timing ........................................................................................................................ 266
Figure 38-14. Transmit Side Timing, Elastic Store Enabled.................................................................................... 267
Figure 38-15. Transmit Line Interface Timing.......................................................................................................... 268
Figure 39-1. DS21458 (17mm CSBGA) .................................................................................................................. 269
Figure 39-2. DS21455 (27mm BGA) ....................................................................................................................... 270
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
LIST OF TABLES
Table 5-1. DS21455 PIN DESCRIPTION .................................................................................................................. 29
Table 5-2. DS21458 PIN DESCRIPTION .................................................................................................................. 34
Table 6-1. REGISTER MAP SORTED BY ADDRESS .............................................................................................. 41
Table 10-1. T1 ALARM CRITERIA ............................................................................................................................ 63
Table 11-1. E1 SYNC/RESYNC CRITERIA .............................................................................................................. 65
Table 11-2 AUTO E-BIT CONDITIONS..................................................................................................................... 68
Table 11-3. E1 ALARM CRITERIA ............................................................................................................................ 70
Table 14-1. LIUC CONTROL..................................................................................................................................... 82
Table 15-1. T1 LINE CODE VIOLATION COUNTING OPTIONS ............................................................................. 86
Table 15-2. E1 LINE CODE VIOLATION COUNTING OPTIONS............................................................................. 86
Table 15-3. T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS ............................................................. 88
Table 15-4. T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS.............................................................. 89
Table 17-1. TIME SLOT NUMBERING SCHEMES................................................................................................. 101
Table 18-1. IDLE CODE ARRAY ADDRESS MAPPING......................................................................................... 108
Table 20-1. ELASTIC STORE DELAY AFTER INITIALIZATION............................................................................ 120
Table 24-1. HDLC CONTROLLER REGISTERS .................................................................................................... 142
Table 25-1. TPD CONTROL.................................................................................................................................... 164
Table 25-2. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0)............................. 165
Table 25-3. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1)............................ 165
Table 25-4. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0) ............................. 165
Table 25-5. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1) ............................ 165
Table 25-6. TRANSFORMER SPECIFICATIONS................................................................................................... 175
Table 28-1. TRANSMIT ERROR INSERTION SETUP SEQUENCE ...................................................................... 195
Table 28-2. ERROR INSERTION EXAMPLES ....................................................................................................... 197
Table 35-1. INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE............................................................ 220
Table 35-2. ID CODE STRUCTURE ....................................................................................................................... 221
Table 35-3. DEVICE ID CODES.............................................................................................................................. 221
Table 35-4. BOUNDARY SCAN CONTROL BITS .................................................................................................. 223
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
1. DESCRIPTION
The DS21455 and DS21458 are quad monolithic devices featuring independent transceivers that can be
software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer,
HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured
for Intel or Motorola bus operations. The DS21455* is a direct replacement for the older DS21Q55 quad
MCM device. The DS21458, which comes in a smaller package (17mm CSBGA) and features an
improved controller interface, is software compatible with the older DS21Q55.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit
interface is responsible for generating the necessary waveshapes for driving the network and providing
the correct source impedance depending on the type of media used. T1 waveform generation includes
DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and data from the network. The receive sensitivity
adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for
E1 applications and 0dB to 15dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase
jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications)
and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI
coder/decoder for interfacing to optical networks.
On the transmit side, clock/data, and frame-sync signals are provided to the framer by the backplane
interface section. The framer inserts the appropriate synchronization framing patterns and alarm
information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression)
and AMI line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes
to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data
and frame-sync signals to the backplane interface section.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and
receive data via the framer block. The HDLC controllers can be assigned to any time slot, group of time
slots, portion of a time slot, or to FDL (T1) or Sa bits (E1). Each controller has 128-bit FIFOs, thus
reducing the amount of processor overhead required to manage the flow of data. In addition, built-in
support for reducing the processor time required handles SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system.
Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1
network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also
manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up
to eight transceivers (two DS21455s/DS21458s) to share a high-speed backplane.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
The parallel port provides access for control and configuration of all the DS21455/DS21458’s features.
The Extended System Information Bus (ESIB) function allows up to eight transceivers, two DS21455s or
two DS21458s to be accessed via a single read for interrupt status or other user-selectable alarm status
information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit
loop-up and loop-down code generation and detection.
* The JTAG function on the DS21455/DS21458 is a single controller for all four transceivers, unlike
the DS21Q55, which has a JTAG controller-per-transceiver architecture.
1.1 Standards
§
§
§
§
§
ANSI:
AT&T:
ITU:
ETSI:
Japanese:
T1.403-1995, T1.231-1993, T1.408
TR54016, TR62411
G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161
ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12
JTG.703, JTI.431, JJ-20.11 (CMI coding only)
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
2. FEATURE HIGHLIGHTS
2.1 General
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DS21455: 27mm, 1.27 pitch BGA, compatible replacement for the DS21Q55
DS21458: 17mm, 1.00 pitch CSBGA
3.3V supply with 5V tolerant inputs and outputs
Evaluation kits
IEEE 1149.1 JTAG-boundary scan
Driver source code available from the factory
2.2 Line Interface
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Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,
6.276MHz, or 12.552MHz for T1-only operation
Fully software configurable
Short- and long-haul applications
Automatic receive sensitivity adjustments
Ranges include 0dB to -43dB or 0dB to -12dB for E1 applications; 0dB to -36dB or 0dB to -15dB
for T1 applications
Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
Internal receive termination option for 75Ω, 100Ω, and 120Ω lines
Monitor application gain settings of 20dB, 26dB, and 32dB
G.703 receive-synchronization signal-mode
Flexible transmit-waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
AIS generation independent of loopbacks
Alternating ones and zeros generation
Square-wave output
Open-drain output option
NRZ format option
Transmitter power-down
Transmitter 50mA short-circuit limiter with exceeded indication of current limit
Transmit open-circuit-detected indication
Line interface function can be completely decoupled from the framer/formatter
2.3 Clock Synthesizer
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Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Derived from recovered line clock or master clock
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
2.4 Jitter Attenuator
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32-bit or 128-bit crystal-less jitter attenuator
Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use
1.544MHz for T1 operation
Can be placed in either the receive or transmit path or disabled
Limit trip indication
2.5 Framer/Formatter
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Fully independent transmit and receive functionality
Full receive- and transmit-path transparency
T1 framing formats include D4, ESF, J1-D4, J1-ESF and SLC-96
Japanese J1 support for CRC6 and yellow alarm
E1 framing formats include FAS, CAS, and CRC-4
Detailed alarm- and status-reporting with optional interrupt support
Large path- and line-error counters for:
- T1 – BPV, CV, CRC6, and framing bit errors
- E1 – BPV, CV, CRC-4, E-bit, and frame alignment errors
- Timed or manual update modes
User-defined Idle Code Generation on a per-channel basis in both transmit and receive paths
Digital milliwatt code generation on the receive path
ANSI T1.403-1998 support
G.965 V5.2 link detect
RAI-CI detection and generation
AIS-CI detection and generation
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating-pattern generators and detectors
- Three independent generators and detectors
- Patterns from 1 bit to 8 bits or 16 bits in length
RCL, RLOS, RRA, and RAIS alarms interrupt on change of state
Flexible signaling support
- Software- or hardware-based
- Interrupt generated on change of signaling data
- Receive-signaling freeze on loss of sync, carrier loss, or frame slip
Hardware pins to indicate carrier loss and signaling freeze
Automatic RAI generation to ETS 300 011 specifications
Expanded access to Sa and Si bits
Option to extend carrier-loss criteria to a 1ms period as per ETS 300 233
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
2.6 System Interface
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Dual two-frame, independent receive and transmit elastic stores
- Independent control and clocking
- Controlled-slip capability with status
- Minimum-delay mode supported
Supports T1 to E1 conversion
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Interleaving PCM bus operation with rates of 4.096MHz, 8.192MHz, and 16.384MHz
Hardware-signaling capability
- Receive-signaling reinsertion to a backplane, multiframe sync
- Availability of signaling in a separate PCM data stream
- Signaling freezing
Access to the data streams in between the framer/formatter and the elastic stores (DS21455)
User-selectable synthesized clock output
2.7 HDLC Controllers
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Two independent HDLC controllers
Fast load and unload features for FIFOs
SS7 support for FISU transmit and receive
Independent 128-byte Rx and Tx buffers with interrupt support
Access FDL, Sa, or single/multiple DS0 channels
DS0 access includes Nx64 or Nx56
Compatible with polled or interrupt-driven environments
Bit Oriented Code (BOC) support
2.8 Test and Diagnostics
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Programmable Bit Error Rate Testing (BERT)
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Daly pattern
Error insertion for single bit or continuous
Insertion options include continuous and absolute number with selectable insertion rates
Total-bit and errored-bit counters
Payload Error Insertion
Errors can be inserted over the entire frame or selected channels
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel payload loopback)
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
2.9 Extended System Information Bus
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Host can read interrupt and alarm status on up to eight ports (two devices) with a single-bus read
2.10 Control Port
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8-bit parallel control port
Multiplexed or nonmultiplexed buses
Intel or Motorola formats
Supports polled or interrupt-driven environments
Software access to device ID and silicon revision
Software-reset supported with automatic clear on power-up
Hardware reset pin
Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In
each 125ms T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is
sent first followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1
to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to
refer to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a
1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
3. BLOCK DIAGRAM
Figure 3-1 shows a simplified block diagram highlighting the major components of the DS21458 and
DS21455.
Figure 3-1. DS21458 Block Diagram
MCLK2
MCLK1
TRANSCEIVER #4
TRANSCEIVER #3
8XCLK
TRANSCEIVER #2
RNEGO
RPOSO
RCLKO
2 HDLCs
MASTER
CLOCK
RECEIVE
LIU
RTIP
RRING
CLOCK & DATA
RECOVERY
LOCAL
LOOP
BACK
REMOTE
LOOP
BACK
FRAMER
LOOP
BACK
BERT
RECEIVE
FRAMER
SYNCHRONIZATION
ALARM MONITORING
SIGNALING EXTRACTION
HDLC EXTRACTION
DS0 CONDITIONING
HDB3/B8ZS DECODER
JITTER
ATTEN.
BACKPLANE
CLOCK
RECEIVE
BACKPLANE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
PAYLOAD LOOPBACK
TX
OR RX
PATH
TRANSMIT
LIU
TTIP
TRING
WAVESHAPE
GENERATION
TPD
TRANSMIT
FRAMER
FRAMING
CRC RECALCULATE(E1)
ALARM INSERTION
SIGNALING INSERTION
HDLC INSERTION
DS0 CONDITIONING
HDB3/B8ZS CODER
JITTER
ATTEN.
DS21458
2 HDLCs
(1 OF 4 TRANSCEIVERS)
JTAG
JTDO
JTDI
ESIB
TPOSI
TCLKO
TNEGO
JTCLK
JTMS ESIBS0
ESIBRD
JTRST
ESIBS1
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TRANSMIT
TRANSMIT
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
PAYLOAD LOOPBACK
BERT
CPU INTERFACE
MUX/NON-MUX, INTEL/MOTOROLA
BPCLK
RSYSCLK
RCLK
RSER
RSIG
RSIGF
RSYNC
RFSYNC
RMSYNC
RCHCLK
RCHBLK
RLCLK
RLINK
TSYSCLK
TCLK
TSER
TSIG
TSYNC
TSSYNC
TCHCLK
TCHBLK
TLCLK
TLINK
RLOS/LOTC
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 3-2. DS21455 Block Diagram
MCLK1 MCLK2
TRANSCEIVER #4
TRANSCEIVER #3
TRANSCEIVER #2
8XCLK
RPOSO
RPOSI
RNEGO
RNEGI
RCLKO
RCLKI
2 HDLCs
MASTER
CLOCK
MUX
CLOCK & DATA
RECOVERY
RRING
JITTER
ATTEN.
TRANSMIT
OR RECEIVE
PATH
TRANSMIT
LIU
TTIP
WAVESHAPE
GENERATION
TRING
BERT
RECEIVE
FRAMER
RECEIVE
LIU
RTIP
BACKPLANE
CLOCK
JITTER
ATTEN.
SYNCHRONIZATION
ALARM MONITORING
SIGNALING EXTRACTION
HDLC EXTRACTION
DS0 CONDITIONING
HDB3/B8ZS DECODER
DS21455
TRANSMIT
FRAMER
FRAMING
CRC RECALCULAION(E1)
ALARM INSERTION
SIGNALING INSERTION
HDLC INSERTION
DS0 CONDITIONING
HDB3/B8ZS CODER
MUX
RECEIVE
BACKPLANE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
TRANSMIT
TRANSMIT
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
LIUC/TPD
2 HDLCs BERT
JTAG
JTDO
JTCLK JTMS
JTDI
JTRST
ESIB
TPOSI
TPOSO
TPOSI
TNEGI
TNEGO
TCLKI
TCLKO
ESIBS0 ESIBRD
ESIBS1
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CPU INTERFACE
MUX/NON-MUX, INTEL/MOTOROLA
BPCLK
RSYSCLK
RCLK
RSER
RSIG
RSIGF
RSYNC
RFSYNC
RMSYNC
RCHCLK
RCHBLK
RLCLK
RLINK
TSYSCLK
TCLK
TSER
TSIG
TSYNC
TSSYNC
TCHCLK
TCHBLK
TLCLK
TLINK
RLOS/LOTC
DS21455/DS21458 Quad T1/E1/J1 Transceivers
4. DS21455/DS21458 DELTA
This section describes the differences between the DS21455 and DS21458.
4.1 Package
DS21455: 27mm, 256-pin, 1.27 ball pitch, BGA (This package has the same footprint and pinout as the
DS21Q55.)
DS21458: 17mm, 256-pin, 1.00 ball pitch, CSBGA
4.2 Controller Interface
DS21455: The CPU interface has 8 address lines with independent chip selects (4) per transceiver.
DS21458: The CPU interface has 10 address lines with a single chip select. The upper address lines, A8
and A9, act as coded transceiver selects.
4.3 ESIB Function
The ESIB function provides a fast method of determining interrupt and alarm status when multiple ports
(up to 8) are being controlled by a single processor.
DS21455: The three ESIB signals are brought out for each transceiver. The user must externally
configure the ESIB group.
DS21458: The ESIB signals are internally bused and only a single set of signals are brought out to enable
the connection of another DS21458 into an 8-port ESIB.
4.4 Framer/LIU Interim Signals
Access to the clock and bipolar data signals between the framer and LIU function may be used for
specialized applications. An internal MUX connects the framer and LIU if these signals are unused. The
MUX is controlled via the LIUC/TPD pin and LIUC bit in the LBCR register. The unused inputs must be
connected to ground.
DS21455: The user has access to all clock and data signals between the framer and LIU on all
transceivers as shown in Figure 4-1.
DS21458: The user has limited access to clock and data signals between the framer and LIU on all
transceivers as shown in Figure 4-2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 4-1. DS21455 Framer/LIU Interim Signals
RPOSO
RNEGO
RCLKO
RPOSI
RNEGI
RCLKI
RPOSO
RNEGO
RCLKO
RPOSI
RNEGI
RCLKI
#1
MUX
Rx
LIU
Tx
LIU
Rx
FRAMER
TPOSI
TNEGI
TCLKI
MUX
Rx
LIU
Tx
FRAMER
MUX
RPOSO
RNEGO
RCLKO
#2
Tx
LIU
Tx
FRAMER
MUX
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
RPOSO
RNEGO
RCLKO
RPOSI
RNEGI
RCLKI
TPOSO
TNEGO
TCLKO
RPOSI
RNEGI
RCLKI
#3
MUX
Rx
LIU
Tx
LIU
#4
Rx
FRAMER
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
MUX
Rx
LIU
Tx
FRAMER
MUX
Rx
FRAMER
Tx
LIU
LIUC
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Rx
FRAMER
Tx
FRAMER
MUX
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 4-2. DS21458 Framer/LIU Interim Signals
RPOSO2
RNEGO2
RCLKO2
RPOSO1
RNEGO1
RCLKO1
#2
#1
Rx
LIU
Rx
LIU
Rx
FRAMER
Tx
LIU
Tx
FRAMER
Rx
FRAMER
Tx
LIU
Tx
FRAMER
TPOSO1
TNEGO1
TCLKO1
TPOSO2
TNEGO2
TCLKO2
RPOSO3
RNEGO3
RCLKO3
RPOSO4
RNEGO4
RCLKO4
#3
Rx
LIU
#4
Rx
LIU
Rx
FRAMER
Tx
LIU
Tx
FRAMER
Rx
FRAMER
Tx
LIU
TPOSO3
TNEGO3
TCLKO3
Tx
FRAMER
TPOSO4
TNEGO4
TCLKO4
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5. PIN FUNCTION DESCRIPTION
5.1 Transmit Side Pins
Signal Name:
TCLK
Signal Description:
Transmit Clock
Signal Type:
Input
A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit-side formatter.
Signal Name:
TSER
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on
the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name:
TCHCLK
Signal Description:
Transmit Channel Clock
Signal Type:
Output
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a
gated transmit-bit clock for fractional T1/E1 applications. Synchronous with TCLK when the transmit-side elastic store is
disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.
Signal Name:
TCHBLK
Signal Description:
Transmit Channel Block
Signal Type:
Output
A user-programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the
transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for
locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
Signal Name:
TSYSCLK
Signal Description:
Transmit System Clock
Signal Type:
Input
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic-store function
is enabled. Should be tied low in applications that do not use the transmit-side elastic store. See the Interleaved PCM Bus
Operation section for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.
Signal Name:
TLCLK
Signal Description:
Transmit Link Clock
Signal Type:
Output
Demand clock for the transmit link data [TLINK] input.
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
TLINK
Signal Description:
Transmit Link Data
Signal Type:
Input
If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fsbit position (D4) or the Z-bit position (ZBTSI) or any combination of the Sa bit positions (E1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
TSYNC
Signal Description:
Transmit Sync
Signal Type:
Input/Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output
either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1.3 to
output double-wide pulses at signaling frames in T1 mode.
Signal Name:
TSSYNC
Signal Description:
Transmit System Sync
Signal Type:
Input
Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe
boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store.
Signal Name:
TSIG
Signal Description:
Transmit Signaling Input
Signal Type:
Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge
of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side
elastic store is enabled.
Signal Name:
TESO
Signal Description:
Transmit Elastic Store-Data Output
Signal Type:
Output
Updated on the rising edge of TCLK with data out of the transmit-side elastic store whether the elastic store is enabled or not.
This pin is normally tied to TDATA.
Signal Name:
TDATA
Signal Description:
Transmit Data
Signal Type:
Input
Sampled on the falling edge of TCLK with data to be clocked through the transmit-side formatter. This pin is normally tied to
TESO.
Signal Name:
TPOSO
Signal Description:
Transmit Positive-Data Output
Signal Type:
Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source
NRZ data via the output-data format (IOCR1.0)-control bit. This pin is normally tied to TPOSI.
Signal Name:
TNEGO
Signal Description:
Transmit Negative-Data Output
Signal Type:
Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to
TNEGI.
Signal Name:
TCLKO
Signal Description:
Transmit Clock Output
Signal Type:
Output
Buffered clock that is used to clock data through the transmit-side formatter (either TCLK or RCLKI). This pin is normally
tied to TCLKI.
Signal Name:
TPOSI (DS21455 Only)
Signal Description:
Transmit Positive-Data Input
Signal Type:
Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO
by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of this function. TPOSI and
TNEGI can be tied together in NRZ applications.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
TNEGI (DS21455 Only)
Signal Description:
Transmit Negative-Data Input
Signal Type:
Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO
by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function. TPOSI
and TNEGI can be tied together in NRZ applications.
Signal Name:
TCLKI (DS21455 Only)
Signal Description:
Transmit Clock Input
Signal Type:
Input
Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
5.2 Receive Side Pins
Signal Name:
RLINK
Signal Description:
Receive Link Data
Signal Type:
Output
T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.
Signal Name:
RLCLK
Signal Description:
Receive Link Clock
Signal Type:
Output
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
RCLK
Signal Description:
Receive Clock
Signal Type:
Output
1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.
Signal Name:
RCHCLK
Signal Description:
Receive Channel Clock
Signal Type:
Output
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel can also be programmed to output a
gated receive-bit clock for fractional T1/E1 applications. Synchronous with RCLK when the receive-side elastic store is
disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.
Signal Name:
RCHBLK
Signal Description:
Receive Channel Block
Signal Type:
Output
A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with
RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and
for per-channel conditioning. See the Channel Blocking Registers section.
Signal Name:
RSER
Signal Description:
Receive Serial Data
Signal Type:
Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive-side elastic store is enabled.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
RSYNC
Signal Description:
Receive Sync
Signal Type:
Input/Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe
(IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide
pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input
via IOCR1.4 at which a frame or multiframe boundary pulse is applied.
Signal Name:
RFSYNC
Signal Description:
Receive Frame Sync
Signal Type:
Output
An extracted 8kHz pulse, one RCLK wide, is output at this pin, which identifies frame boundaries.
Signal Name:
RMSYNC
Signal Description:
Receive Multiframe Sync
Signal Type:
Output
An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is output at this pin,
which identifies multiframe boundaries.
Signal Name:
RDATA
Signal Description:
Receive Data
Signal Type:
Output
Updated on the rising edge of RCLK with the data out of the receive-side framer.
Signal Name:
RSYSCLK
Signal Description:
Receive System Clock
Signal Type:
Input
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic-store function is enabled.
Should be tied low in applications that do not use the receive-side elastic store. See the Interleaved PCM Bus Operation
section for details on 4.096MHz and 8.192MHz operation using the IBO.
Signal Name:
RSIG
Signal Description:
Receive Signaling Output
Signal Type:
Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
RLOS/LOTC
Signal Description:
Receive Loss of Sync/Loss of Transmit Clock
Signal Type:
Output
A dual-function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5ms.
Signal Name:
RCL
Signal Description:
Receive Carrier Loss
Signal Type:
Output
Set high when the line interface detects a carrier loss.
Signal Name:
RSIGF
Signal Description:
Receive Signaling Freeze
Signal Type:
Output
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of
the condition.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
BPCLK
Signal Description:
Backplane Clock
Signal Type:
Output
A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
RPOSO
Signal Description:
Receive Positive-Data Output
Signal Type:
Output
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
Signal Name:
RNEGO
Signal Description:
Receive Negative-Data Output
Signal Type:
Output
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI.
Signal Name:
RCLKO
Signal Description:
Receive Clock Output
Signal Type:
Output
Buffered recovered clock from the network. This pin is normally tied to RCLKI.
Signal Name:
RPOSI (DS21455 Only)
Signal Description:
Receive Positive Data Input
Signal Type:
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
Signal Name:
RNEGI (DS21455 Only)
Signal Description:
Receive Negative Data Input
Signal Type:
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
Signal Name:
RCLKI (DS21455 Only)
Signal Description:
Receive Clock Input
Signal Type:
Input
Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function.
5.3 Parallel Control Port Pins
Signal Name:
INT
Signal Description:
Interrupt
Signal Type:
Output
Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.
Signal Name:
TSTRST
Signal Description:
Tri-State Control and Device Reset
Signal Type:
Input
A dual-function pin. A zero-to-one transition issues a hardware reset to the DS21455/DS21458 register set. A reset clears all
configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will tri-state all output and I/O
pins (including the parallel control port). Set low for normal operation. Useful in board-level testing.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
MUX
Signal Description:
Bus Operation
Signal Type:
Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
AD0 to AD7
Signal Description:
Data Bus [D0 to D7] or Address/Data Bus
Signal Type:
Input/Output
In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an
8-bit, multiplexed address/data bus.
Signal Name:
A0 to A6
Signal Description:
Address Bus
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), it serves as the address bus. In multiplexed bus operation (MUX = 1), these pins
are not used and should be tied low.
Signal Name:
A8 and A9 (DS21458 Only)
Signal Description:
Address Bus
Signal Type:
Input
Upper address pins for nonmultiplexed (MUX = 0), and multiplexed (MUX = 1) bus operation,.
Signal Name:
BTS
Signal Description:
Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD (DS),
ALE (AS), and WR (R/W) pins. If BTS = 1, then these pins assume the function listed in parentheses ().
Signal Name:
RD (DS)
Signal Description:
Read Input-Data Strobe
Signal Type:
Input
RD and DS are active-low signals. DS active HIGH when MUX = 0. See the bus timing diagrams.
Signal Name:
CS1 (DS21455 Only)
Signal Description:
Chip Select for Transceiver 1
Signal Type:
Input
Must be low to read or write to Transceiver 1 of the device. CS1 is an active-low signal.
Signal Name:
CS2 (DS21455 Only)
Signal Description:
Chip Select for Transceiver 2
Signal Type:
Input
Must be low to read or write to Transceiver 2 of the device. CS2 is an active-low signal.
Signal Name:
CS3 (DS21455 Only)
Signal Description:
Chip Select for Transceiver 3
Signal Type:
Input
Must be low to read or write to Transceiver 3 of the device. CS3 is an active-low signal.
Signal Name:
CS4 (DS21455 Only)
Signal Description:
Chip Select for Transceiver 4
Signal Type:
Input
Must be low to read or write to Transceiver 4 of the device. CS4 is an active-low signal.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
CS (DS21458 Only)
Signal Description:
Chip Select
Signal Type:
Input
Must be low to read or write to the device. CS is an active-low signal.
Signal Name:
ALE (AS)/A7
Signal Description:
Address Latch Enable (Address Strobe) or A7
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it
serves to demultiplex the bus on a positive-going edge.
Signal Name:
WR (R/W)
Signal Description:
Write Input (Read/Write)
Signal Type:
Input
WR is an active-low signal.
5.4 Extended System Information Bus
Signal Name:
ESIBS0
Signal Description:
Extended System Information Bus Select 0
Signal Type:
Input/Output
Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System
Information Bus (ESIB) section for more details.
Signal Name:
ESIBS1
Signal Description:
Extended System Information Bus Select 1
Signal Type:
Input/Output
Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System
Information Bus (ESIB) section for more details.
Signal Name:
ESIBRD
Signal Description:
Extended System Information Bus Read
Signal Type:
Input/Output
Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System
Information Bus (ESIB) section for more details.
5.5 JTAG Test Access Port Pins
Signal Name:
JTRST
Signal Description:
IEEE 1149.1 Test Reset
Signal Type:
Input
JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to
high. This action will set the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST
low. JTRST is pulled HIGH internally via a 10kW resistor operation.
Signal Name:
JTMS
Signal Description:
IEEE 1149.1 Test Mode Select
Signal Type:
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test-access port into the various defined IEEE 1149.1
states. This pin has a 10kW pullup resistor.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
JTCLK
Signal Description:
IEEE 1149.1 Test Clock Signal
Signal Type:
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
JTDI
Signal Description:
IEEE 1149.1 Test Data Input
Signal Type:
Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor.
Signal Name:
JTDO
Signal Description:
IEEE 1149.1 Test Data Output
Signal Type:
Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left
unconnected.
5.6 Line Interface Pins
Signal Name:
MCLK1
Signal Description:
Master Clock Input for Transceivers 1 and 2
Signal Type:
Input
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in
T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name:
MCLK2
Signal Description:
Master Clock Input for Transceivers 3 and 4
Signal Type:
Input
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in
T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name:
LIUC/TPD (DS21455), TPD (DS21458)
Signal Description:
Line Interface Unit Connect/Transmit Power-Down
Signal Type:
Input
This is a dual function pin depending on the state of the LTS bit in the LBCR register (LBCR.7).
LTS = 0: In this mode the LIUC/TPD pin, along with the LIUC bit of the LBCR register controls the connection between the
framer and the LIU. This function is only available on the DS21455. See the LIUC bit description in Section 14 and
Table 14-1.
LTS = 1: In this mode the LIUC/TPD pin along with the TPD bit in the LIC1 register (LIC1.0) controls the state of the
Transmit Power-Down function. See the TPD bit description in Section 25 and Table 25-1.
Signal Name:
RTIP and RRING
Signal Description:
Receive Tip and Ring
Signal Type:
Input
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the network. See Section 25 for details.
Signal Name:
TTIP and TRING
Signal Description:
Transmit Tip and Ring
Signal Type:
Output
Analog line-driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Section 25 for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
5.7 Supply Pins
Signal Name:
DVDD
Signal Description:
Digital Positive Supply
Signal Type:
Supply
3.3V ±5%. Should be tied to the RVDD and TVDD pins.
Signal Name:
RVDD
Signal Description:
Receive Analog Positive Supply
Signal Type:
Supply
3.3V ±5%. Should be tied to the DVDD and TVDD pins.
Signal Name:
TVDD
Signal Description:
Transmit Analog Positive Supply
Signal Type:
Supply
3.3V ±5% Should be tied to the RVDD and DVDD pins.
Signal Name:
DVSS
Signal Description:
Digital Signal Ground
Signal Type:
Supply
Should be tied to the RVSS and TVSS pins.
Signal Name:
RVSS
Signal Description:
Receive Analog Signal Ground
Signal Type:
Supply
0.0V. Should be tied to DVSS and TVSS.
Signal Name:
TVSS
Signal Description:
Transmit Analog Signal Ground
Signal Type:
Supply
0.0V. Should be tied to DVSS and RVSS.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
5.8 Pin Descriptions
Table 5-1. DS21455 PIN DESCRIPTION
PIN
U3
L17
V2
T4
V8
H4
U8
P4
M1
H17
F4
V13
P2
P3
A14
B5
K17
U11
J19
W15
U7
U9
U5
V4
U4
J3
N4
U2
V5
B12
C12
C16
D18
A9
B3
B6
C4
G20
M17
M20
P18
H3
U6
W8
A17
A20
B11
A5
NAME
A0
A1
A2
A3
A4
A5
A6
A7/ALE (AS)
BPCLK1
BPCLK2
BPCLK3
BPCLK4
BTS
CS1
CS2
CS3
CS4
D0/AD0
D1/AD1
D2/AD2
D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
TYPE
I
I
I
I
I
I
I
I
O
O
O
O
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FUNCTION
Address Bus Bit 0 (Lsb)
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Address Bus Bit 5
Address Bus Bit 6
Address Bus Bit 7 (Msb)/Address Latch Enable
Backplane Clock, Transceiver 1
Backplane Clock, Transceiver 2
Backplane Clock, Transceiver 3
Backplane Clock, Transceiver 4
Bus Type Select (0 = Intel/1 = Motorola)
Chip Select for Transceiver 1
Chip Select for Transceiver 2
Chip Select for Transceiver 3
Chip Select for Transceiver 4
Data Bus Bit 0/Address/Data Bus Bit 0 (Lsb)
Data Bus Bit 1/Address/Data Bus Bit 1
Data Bus Bit 2/Address/Data Bus Bit 2
Data Bus Bit 3/Address/Data Bus Bit 3
Data Bus Bit 4/Address/Data Bus Bit 4
Data Bus Bit 5/Address/Data Bus Bit 5
Data Bus Bit 6/Address/Data Bus Bit 6
Data Bus Bit 7/Address/Data Bus Bit 7 (Msb)
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
B7
B9
H20
L20
N17
J4
C13
C3
U13
W6
F18
D7
T20
V9
B17
A6
J20
U1
Y15
N1
V19
W13
V18
K2
T1
W20
U10
M2
G17
G4
Y12
J1
D14
F3
U14
N3
B13
E3
M18
M4
A15
A4
R17
M3
C14
B4
T17
N2
K4
D17
A2
V14
F1
NAME
DVSS
DVSS
DVSS
DVSS
DVSS
ESIBRD1
ESIBRD2
ESIBRD3
ESIBRD4
ESIBS0_1
ESIBS0_2
ESIBS0_3
ESIBS0_4
ESIBS1_1
ESIBS1_2
ESIBS1_3
ESIBS1_4
INT
JTCLK
JTDI
JTDO
JTMS
JTRST
LIUC/TPD
MCLK1
MCLK2
MUX
RCHBLK1
RCHBLK2
RCHBLK3
RCHBLK4
RCHCLK1
RCHCLK2
RCHCLK3
RCHCLK4
RCLK1
RCLK2
RCLK3
RCLK4
RCLKI1
RCLKI2
RCLKI3
RCLKI4
RCLKO1
RCLKO2
RCLKO3
RCLKO4
RD (DS)
RFSYNC1
RFSYNC2
RFSYNC3
RFSYNC4
RLCLK1
TYPE
—
—
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
O
O
O
O
I
O
O
O
O
O
FUNCTION
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Extended System Information Bus Read for Transceiver 1
Extended System Information Bus Read for Transceiver 2
Extended System Information Bus Read for Transceiver 3
Extended System Information Bus Read for Transceiver 4
Extended System Information Bus 0 for Transceiver 1
Extended System Information Bus 0 for Transceiver 2
Extended System Information Bus 0 for Transceiver 3
Extended System Information Bus 0 for Transceiver 4
Extended System Information Bus 1 for Transceiver 1
Extended System Information Bus 1 for Transceiver 2
Extended System Information Bus 1 for Transceiver 3
Extended System Information Bus 1 for Transceiver 4
Interrupt for All Four Transceivers
JTAG Clock
JTAG Data Input
JTAG Data Output
JTAG Test Mode Select
Jtag Reset
Line Interface Connect for All Four Transceivers or Transmit Power-Down Enable
Master Clock for Transceiver 1 and Transceiver 3
Master Clock for Transceiver 2 and Transceiver 4
Mux Bus Select
Receive Channel Block for Transceiver 1
Receive Channel Block for Transceiver 2
Receive Channel Block for Transceiver 3
Receive Channel Block for Transceiver 4
Receive Channel Clock for Transceiver 1
Receive Channel Clock for Transceiver 2
Receive Channel Clock for Transceiver 3
Receive Channel Clock for Transceiver 4
Receive Clock Output from the Framer on Transceiver 1
Receive Clock Output from the Framer on Transceiver 2
Receive Clock Output from the Framer on Transceiver 3
Receive Clock Output from the Framer on Transceiver 4
Receive Clock Input for the LIU on Transceiver 1
Receive Clock Input for the LIU on Transceiver 2
Receive Clock Input for the LIU on Transceiver 3
Receive Clock Input for the LIU on Transceiver 4
Receive Clock Output from the LIU on Transceiver 1
Receive Clock Output from the LIU on Transceiver 2
Receive Clock Output from the LIU on Transceiver 3
Receive Clock Output from the LIU On Transceiver 4
Read Input (Data Strobe)
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 1
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 2
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 3
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 4
Receive Link Clock for Transceiver 1
30 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
A12
D3
K18
G2
A13
A3
U12
H2
E17
E1
V11
L1
D16
F2
W16
R3
D13
A1
P17
L3
B15
C2
U17
R4
B14
B2
V15
L4
A16
B1
U15
Y11
Y14
Y17
Y20
J2
D15
E2
W17
L2
B16
C1
Y18
K1
C15
D2
V16
G1
D12
D1
V12
H1
F17
NAME
RLCLK2
RLCLK3
RLCLK4
RLINK1
RLINK2
RLINK3
RLINK4
RLOS/LOTC1
RLOS/LOTC2
RLOS/LOTC3
RLOS/LOTC4
RMSYNC1
RMSYNC2
RMSYNC3
RMSYNC4
RNEGI1
RNEGI2
RNEGI3
RNEGI4
RNEGO1
RNEGO2
RNEGO3
RNEGO4
RPOSI1
RPOSI2
RPOSI3
RPOSI4
RPOSO1
RPOSO2
RPOSO3
RPOSO4
RRING1
RRING2
RRING3
RRING4
RSER1
RSER2
RSER3
RSER4
RSIG1
RSIG2
RSIG3
RSIG4
RSIGF1
RSIGF2
RSIGF3
RSIGF4
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYSCLK1
RSYSCLK2
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I
I
FUNCTION
Receive Link Clock for Transceiver 2
Receive Link Clock for Transceiver 3
Receive Link Clock for Transceiver 4
Receive Link Data for Transceiver 1
Receive Link Data for Transceiver 2
Receive Link Data for Transceiver 3
Receive Link Data for Transceiver 4
Receive Loss of Sync/Loss of Transmit Clock for Transceiver 1
Receive Loss of Sync/Loss of Transmit Clock for Transceiver 2
Receive Loss of Sync/Loss of Transmit Clock for Transceiver 3
Receive Loss of Sync/Loss of Transmit Clock For Transceiver4
Receive Multiframe Sync for Transceiver 1
Receive Multiframe Sync for Transceiver 2
Receive Multiframe Sync for Transceiver 3
Receive Multiframe Sync for Transceiver 4
Receive Negative Data for the Framer on Transceiver 1
Receive Negative Data for the Framer on Transceiver 2
Receive Negative Data for the Framer on Transceiver 3
Receive Negative Data for the Framer on Transceiver 4
Receive Negative Data from the LIU on Transceiver 1
Receive Negative Data from the LIU on Transceiver 2
Receive Negative Data from the LIU on Transceiver 3
Receive Negative Data from the LIU on Transceiver 4
Receive Positive Data for the Framer on Transceiver 1
Receive Positive Data for the Framer on Transceiver 2
Receive Positive Data for the Framer on Transceiver 3
Receive Positive Data for the Framer on Transceiver 4
Receive Positive Data from the LIU on Transceiver 1
Receive Positive Data from the LIU on Transceiver 2
Receive Positive Data from the LIU on Transceiver 3
Receive Positive Data from the LIU on Transceiver 4
Receive Analog Ring Input for Transceiver 1
Receive Analog Ring Input For Transceiver 2
Receive Analog Ring Input For Transceiver 3
Receive Analog Ring Input For Transceiver 4
Receive Serial Data for Transceiver 1
Receive Serial Data for Transceiver 2
Receive Serial Data for Transceiver 3
Receive Serial Data for Transceiver 4
Receive Signaling Output for Transceiver 1
Receive Signaling Output for Transceiver 2
Receive Signaling Output for Transceiver 3
Receive Signaling Output for Transceiver 4
Receive Signaling Freeze Output for Transceiver 1
Receive Signaling Freeze Output for Transceiver 2
Receive Signaling Freeze Output for Transceiver 3
Receive Signaling Freeze Output for Transceiver 4
Receive Sync for Transceiver 1
Receive Sync for Transceiver 2
Receive Sync for Transceiver 3
Receive Sync for Transceiver 4
Receive System Clock for Transceiver 1
Receive System Clock for Transceiver 2
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
G3
W14
Y10
Y13
Y16
Y19
P1
J17
E4
W18
R2
T2
H19
J18
D4
D5
V20
W19
W1
F20
C11
U20
V10
A18
B8
L18
Y9
B19
B10
M19
V6
D19
C8
P20
W7
E18
A7
P19
V3
E20
D6
T18
W5
E19
C6
T19
R1
F19
D8
R20
T3
B20
D9
NAME
RSYSCLK3
RSYSCLK4
RTIP1
RTIP2
RTIP3
RTIP4
RVDD
RVDD
RVDD
RVDD
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
TCHBLK1
TCHBLK2
TCHBLK3
TCHBLK4
TCHCLK1
TCHCLK2
TCHCLK3
TCHCLK4
TCLK1
TCLK2
TCLK3
TCLK4
TCLKI1
TCLKI2
TCLKI3
TCLKI4
TCLKO1
TCLKO2
TCLKO3
TCLKO4
TLCLK1
TLCLK2
TLCLK3
TLCLK4
TLINK1
TLINK2
TLINK3
TLINK4
TNEGI1
TNEGI2
TNEGI3
TNEGI4
TNEGO1
TNEGO2
TNEGO3
TYPE
I
I
I
I
I
I
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
FUNCTION
Receive System Clock for Transceiver 3
Receive System Clock for Transceiver 4
Receive Analog Tip Input for Transceiver 1
Receive Analog Tip Input for Transceiver 2
Receive Analog Tip Input for Transceiver 3
Receive Analog Tip Input for Transceiver 4
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Transmit Channel Block for Transceiver 1
Transmit Channel Block for Transceiver 2
Transmit Channel Block for Transceiver 3
Transmit Channel Block for Transceiver 4
Transmit Channel Clock for Transceiver 1
Transmit Channel Clock for Transceiver 2
Transmit Channel Clock for Transceiver 3
Transmit Channel Clock for Transceiver 4
Transmit Clock for Transceiver 1
Transmit Clock for Transceiver 2
Transmit Clock for Transceiver 3
Transmit Clock for Transceiver 4
Transmit Clock Input for the LIU on Transceiver 1
Transmit Clock Input for the LIU on Transceiver 2
Transmit Clock Input for the LIU on Transceiver 3
Transmit Clock Input for the LIU on Transceiver 4
Transmit Clock Output from the Framer on Transceiver 1
Transmit Clock Output from the Framer on Transceiver 2
Transmit Clock Output from the Framer on Transceiver 3
Transmit Clock Output from the Framer on Transceiver 4
Transmit Link Clock for Transceiver 1
Transmit Link Clock for Transceiver 2
Transmit Link Clock for Transceiver 3
Transmit Link Clock for Transceiver 4
Transmit Link Data for Transceiver 1
Transmit Link Data for Transceiver 2
Transmit Link Data for Transceiver 3
Transmit Link Data for Transceiver 4
Transmit Negative-Data Input for the LIU on Transceiver 1
Transmit Negative-Data Input for the LIU on Transceiver 2
Transmit Negative-Data Input for the LIU on Transceiver 3
Transmit Negative-Data Input for the LIU on Transceiver 4
Transmit Negative-Data Output from Framer on Transceiver 1
Transmit Negative-Data Output from Framer on Transceiver 2
Transmit Negative-Data Output from Framer on Transceiver 3
32 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
N20
W3
C20
A8
R19
V7
C19
C9
N19
Y2
Y4
Y6
Y8
W9
C17
C10
K20
W10
C18
A10
L19
W12
B18
D10
K19
U16
V1
D20
C7
R18
W11
A19
A11
N18
Y1
Y3
Y5
Y7
W2
G19
D11
U19
W4
G18
C5
U18
K3
NAME
TNEGO4
TPOSI1
TPOSI2
TPOSI3
TPOSI4
TPOSO1
TPOSO2
TPOSO3
TPOSO4
TRING1
TRING2
TRING3
TRING4
TSER1
TSER2
TSER3
TSER4
TSIG1
TSIG2
TSIG3
TSIG4
TSSYNC1
TSSYNC2
TSSYNC3
TSSYNC4
TSTRST
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYSCLK1
TSYSCLK2
TSYSCLK3
TSYSCLK4
TTIP1
TTIP2
TTIP3
TTIP4
TVDD
TVDD
TVDD
TVDD
TVSS
TVSS
TVSS
TVSS
WR (R/W)
TYPE
O
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
I
I
I
O
O
O
O
—
—
—
—
—
—
—
—
I
FUNCTION
Transmit Negative-Data Output from Framer on Transceiver 4
Transmit Positive-Data Input for the LIU on Transceiver 1
Transmit Positive-Data Input for the LIU on Transceiver 2
Transmit Positive-Data Input for the LIU on Transceiver 3
Transmit Positive-Data Input for the LIU on Transceiver 4
Transmit Positive-Data Output from Framer on Transceiver 1
Transmit Positive-Data Output from Framer on Transceiver 2
Transmit Positive-Data Output from Framer on Transceiver 3
Transmit Positive-Data Output from Framer on Transceiver 4
Transmit Analog Ring Output for Transceiver 1
Transmit Analog Ring Output for Transceiver 2
Transmit Analog Ring Output for Transceiver 3
Transmit Analog Ring Output for Transceiver 4
Transmit Serial Data for Transceiver 1
Transmit Serial Data for Transceiver 2
Transmit Serial Data for Transceiver 3
Transmit Serial Data for Transceiver 4
Transmit Signaling Input for Transceiver 1
Transmit Signaling Input for Transceiver 2
Transmit Signaling Input for Transceiver 3
Transmit Signaling Input for Transceiver 4
Transmit System Sync for Transceiver 1
Transmit System Sync for Transceiver 2
Transmit System Sync for Transceiver 3
Transmit System Sync for Transceiver 4
Test/Reset
Transmit Sync for Transceiver 1
Transmit Sync for Transceiver 2
Transmit Sync for Transceiver 3
Transmit Sync for Transceiver 4
Transmit System Clock for Transceiver 1
Transmit System Clock for Transceiver 2
Transmit System Clock for Transceiver 3
Transmit System Clock for Transceiver 4
Transmit Analog Tip Output for Transceiver 1
Transmit Analog Tip Output for Transceiver 2
Transmit Analog Tip Output for Transceiver 3
Transmit Analog Tip Output for Transceiver 4
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Write Input (Read/Write)
33 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Table 5-2. DS21458 PIN DESCRIPTION
PIN
H2
E10
H3
G4
N7
B9
T7
G2
H6
J11
J5
H13
E8
N9
B10
M8
P8
D10
N8
P7
M7
R7
G1
G3
P4
P5
P6
C11
C12
C13
D3
E3
F3
L14
M14
N14
N4
N5
N6
D11
D12
D13
D4
E4
F4
L13
M13
N13
H8
J8
NAME
A0
A1
A2
A3
A4
A5
A6
A7/ALE (AS)
A8
A9
BPCLK1
BPCLK2
BPCLK3
BPCLK4
BTS
CS
D0/AD0
D1/AD1
D2/AD2
D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
ESIBRD
ESIBS0
TYPE
I
I
I
I
I
I
I
I
I
I
O
O
O
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O
I/O
FUNCTION
Address Bus Bit 0 (Lsb)
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Address Bus Bit 5
Address Bus Bit 6
Address Bus Bit 7 (Msb)/Address Latch Enable
Address Bus Bit 8
Address Bus Bit 9
Backplane Clock, Transceiver 1
Backplane Clock, Transceiver 2
Backplane Clock, Transceiver 3
Backplane Clock, Transceiver 4
Bus Type Select (0 = Intel/1 = Motorola)
Chip Select
Data Bus Bit 0/Address/Data Bus Bit 0 (Lsb)
Data Bus Bit 1/ Address/Data Bus Bit 1
Data Bus Bit 2/Address/Data Bus Bit 2
Data Bus Bit 3/Address/Data Bus Bit 3
Data Bus Bit 4/Address/Data Bus Bit 4
Data Bus Bit 5/Address/Data Bus Bit 5
Data Bus Bit 6/Address/Data Bus Bit 6
Data Bus Bit 7/Address/Data Bus Bit 7 (Msb)
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Positive Supply
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Extended System Information Bus Read
Extended System Information Bus 0
34 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
J9
H5
K16
C10
K13
J15
K14
D9
H4
J12
R8
E9
K9
P3
K3
G10
C7
R11
L2
G11
D7
M9
K8
F10
G5
K12
H9
R1
C14
A2
P14
A10
K4
G14
C6
P11
M2
F15
B6
R12
P2
C15
C3
T15
K5
E15
D6
P12
M3
G13
E6
M10
H10
NAME
ESIBS1
INT
JTCLK
JTDI
JTDO
JTMS
JTRST
TPD
MCLK1
MCLK2
MUX
Unused
N.C.
N.C.
RCHBLK1
RCHBLK2
RCHBLK3
RCHBLK4
RCHCLK1
RCHCLK2
RCHCLK3
RCHCLK4
RCLK1
RCLK2
RCLK3
RCLK4
Unused
RCLKO1
RCLKO2
RCLKO3
RCLKO4
RD (DS)
RFSYNC1
RFSYNC2
RFSYNC3
RFSYNC4
RLCLK1
RLCLK2
RLCLK3
RLCLK4
RLINK1
RLINK2
RLINK3
RLINK4
RLOS/LOTC1
RLOS/LOTC2
RLOS/LOTC3
RLOS/LOTC4
RMSYNC1
RMSYNC2
RMSYNC3
RMSYNC4
Unused
TYPE
I/O
O
I
I
O
I
I
I
I
I
I
I
—
—
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
FUNCTION
Extended System Information Bus 1
Interrupt for All Four Transceivers
JTAG Clock
JTAG Data Input
JTAG Data Output
JTAG Test Mode Select
JTAG Reset
Transmit Power-Down Enable
Master Clock for Transceiver 1 and Transceiver 3
Master Clock for Transceiver 2 and Transceiver 4
Mux Bus Select
Connect to VSS for Proper Operation
No Connection
No Connection
Receive Channel Block for Transceiver 1
Receive Channel Block for Transceiver 2
Receive Channel Block for Transceiver 3
Receive Channel Block for Transceiver 4
Receive Channel Clock for Transceiver 1
Receive Channel Clock for Transceiver 2
Receive Channel Clock for Transceiver 3
Receive Channel Clock for Transceiver 4
Receive Clock Output from the Framer on Transceiver 1
Receive Clock Output from the Framer on Transceiver 2
Receive Clock Output from the Framer on Transceiver 3
Receive Clock Output from the Framer on Transceiver 4
Connect to VSS for Proper Operation
Receive Clock Output from the LIU on Transceiver 1
Receive Clock Output from the LIU on Transceiver 2
Receive Clock Output from the LIU on Transceiver 3
Receive Clock Output from the LIU on Transceiver 4
Read Input (Data Strobe)
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 1
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 2
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 3
Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 4
Receive Link Clock for Transceiver 1
Receive Link Clock for Transceiver 2
Receive Link Clock for Transceiver 3
Receive Link Clock for Transceiver 4
Receive Link Data for Transceiver 1
Receive Link Data for Transceiver 2
Receive Link Data for Transceiver 3
Receive Link Data for Transceiver 4
Receive Loss of Sync/Loss of Transmit Clock for Transceiver 1
Receive Loss of Sync/Loss of Transmit Clock for Transceiver 2
Receive Loss of Sync/Loss of Transmit Clock for Transceiver 3
Receive Loss of Sync/Loss of Transmit Clock for Transceiver 4
Receive Multiframe Sync for Transceiver 1
Receive Multiframe Sync for Transceiver 2
Receive Multiframe Sync for Transceiver 3
Receive Multiframe Sync for Transceiver 4
Connect to VSS for Proper Operation
35 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
J2
H11
F8
P10
G8
J6
H12
F9
N10
L1
F16
A6
T11
J4
H14
C8
P9
K2
G15
B7
R10
L3
F14
E7
N11
K6
E14
B5
N12
J3
H15
B8
R9
K1
G16
A7
T10
H1
J16
A9
T8
N1
J1
M1
E16
H16
D16
A5
A8
A4
T12
T13
T9
NAME
RNEGO1
RNEGO2
RNEGO3
RNEGO4
Unused
RPOSO1
RPOSO2
RPOSO3
RPOSO4
RRING1
RRING2
RRING3
RRING4
RSER1
RSER2
RSER3
RSER4
RSIG1
RSIG2
RSIG3
RSIG4
RSIGF1
RSIGF2
RSIGF3
RSIGF4
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
RTIP1
RTIP2
RTIP3
RTIP4
RVDD
RVDD
RVDD
RVDD
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
TYPE
O
O
O
O
I
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FUNCTION
Receive Negative Data from the LIU on Transceiver 1
Receive Negative Data from the LIU on Transceiver 2
Receive Negative Data from the LIU on Transceiver 3
Receive Negative Data from the LIU on Transceiver 4
Connect to VSS for Proper Operation
Receive Positive Data from the LIU on Transceiver 1
Receive Positive Data from the LIU on Transceiver 2
Receive Positive Data from the LIU on Transceiver 3
Receive Positive Data from the LIU on Transceiver 4
Receive Analog Ring Input for Transceiver 1
Receive Analog Ring Input for Transceiver 2
Receive Analog Ring Input for Transceiver 3
Receive Analog Ring Input for Transceiver 4
Receive Serial Data for Transceiver 1
Receive Serial Data for Transceiver 2
Receive Serial Data for Transceiver 3
Receive Serial Data for Transceiver 4
Receive Signaling Output for Transceiver 1
Receive Signaling Output for Transceiver 2
Receive Signaling Output for Transceiver 3
Receive Signaling Output for Transceiver 4
Receive Signaling Freeze Output for Transceiver 1
Receive Signaling Freeze Output for Transceiver 2
Receive Signaling Freeze Output for Transceiver 3
Receive Signaling Freeze Output for Transceiver 4
Receive Sync for Transceiver 1
Receive Sync for Transceiver 2
Receive Sync for Transceiver 3
Receive Sync for Transceiver 4
Receive System Clock for Transceiver 1
Receive System Clock for Transceiver 2
Receive System Clock for Transceiver 3
Receive System Clock for Transceiver 4
Receive Analog Tip Input for Transceiver 1
Receive Analog Tip Input for Transceiver 2
Receive Analog Tip Input for Transceiver 3
Receive Analog Tip Input for Transceiver 4
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Positive Supply
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
36 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
N2
E13
C5
R13
J7
D15
B4
P13
L5
G12
F6
L9
L6
F12
F7
L11
T2
A15
B2
R16
J14
J13
P1
C16
C4
T14
K7
F11
G7
L12
M5
E12
E5
M12
T1
B15
A1
T16
L4
F13
D5
L10
R2
A16
B1
R15
R4
T4
A13
B13
D1
D2
N15
NAME
TCHBLK1
TCHBLK2
TCHBLK3
TCHBLK4
TCHCLK1
TCHCLK2
TCHCLK3
TCHCLK4
TCLK1
TCLK2
TCLK3
TCLK4
Unused
Unused
Unused
Unused
TCLKO1
TCLKO2
TCLKO3
TCLKO4
TEST1
TEST2
TLCLK1
TLCLK2
TLCLK3
TLCLK4
TLINK1
TLINK2
TLINK3
TLINK4
Unused
Unused
Unused
Unused
TNEGO1
TNEGO2
TNEGO3
TNEGO4
Unused
Unused
Unused
Unused
TPOSO1
TPOSO2
TPOSO3
TPOSO4
TRING1
TRING1
TRING2
TRING2
TRING3
TRING3
TRING4
TYPE
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
O
—
—
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
FUNCTION
Transmit Channel Block for Transceiver 1
Transmit Channel Block for Transceiver 2
Transmit Channel Block for Transceiver 3
Transmit Channel Block for Transceiver 4
Transmit Channel Clock for Transceiver 1
Transmit Channel Clock for Transceiver 2
Transmit Channel Clock for Transceiver 3
Transmit Channel Clock for Transceiver 4
Transmit Clock for Transceiver 1
Transmit Clock for Transceiver 2
Transmit Clock for Transceiver 3
Transmit Clock for Transceiver 4
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Transmit Clock Output from the Framer on Transceiver 1
Transmit Clock Output from the Framer on Transceiver 2
Transmit Clock Output from the Framer on Transceiver 3
Transmit Clock Output from the Framer on Transceiver 4
Used for Factory Test – Do Not Connect
Used for Factory Test – Do Not Connect
Transmit Link Clock for Transceiver 1
Transmit Link Clock for Transceiver 2
Transmit Link Clock for Transceiver 3
Transmit Link Clock for Transceiver 4
Transmit Link Data for Transceiver 1
Transmit Link Data for Transceiver 2
Transmit Link Data for Transceiver 3
Transmit Link Data for Transceiver 4
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Transmit Negative-Data Output from Framer on Transceiver 1
Transmit Negative-Data Output from Framer on Transceiver 2
Transmit Negative-Data Output from Framer on Transceiver 3
Transmit Negative-Data Output from Framer on Transceiver 4
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Connect to VSS for Proper Operation
Transmit Positive-Data Output from Framer on Transceiver 1
Transmit Positive-Data Output from Framer on Transceiver 2
Transmit Positive-Data Output from Framer on Transceiver 3
Transmit Positive-Data Output from Framer on Transceiver 4
Transmit Analog Ring Output for Transceiver 1
Transmit Analog Ring Output for Transceiver 1
Transmit Analog Ring Output for Transceiver 2
Transmit Analog Ring Output for Transceiver 2
Transmit Analog Ring Output for Transceiver 3
Transmit Analog Ring Output for Transceiver 3
Transmit Analog Ring Output for Transceiver 4
37 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN
N16
M6
G9
G6
K10
L7
E11
F5
K11
M4
D14
A3
M11
K15
N3
B16
B3
R14
H7
J10
D8
L8
R3
T3
A14
B14
C1
C2
P15
P16
R6
T6
A11
B11
F1
F2
L15
L16
R5
T5
A12
B12
E1
E2
M15
M16
C9
NAME
TRING4
TSER1
TSER2
TSER3
TSER4
TSIG1
TSIG2
TSIG3
TSIG4
TSSYNC1
TSSYNC2
TSSYNC3
TSSYNC4
TSTRST
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYSCLK1
TSYSCLK2
TSYSCLK3
TSYSCLK4
TTIP1
TTIP1
TTIP2
TTIP2
TTIP3
TTIP3
TTIP4
TTIP4
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVSS
TVSS
TVSS
TVSS
TVSS
TVSS
TVSS
TVSS
WR (R/W)
TYPE
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
I
I
I
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
FUNCTION
Transmit Analog Ring Output for Transceiver 4
Transmit Serial Data for Transceiver 1
Transmit Serial Data for Transceiver 2
Transmit Serial Data for Transceiver 3
Transmit Serial Data for Transceiver 4
Transmit Signaling Input for Transceiver 1
Transmit Signaling Input for Transceiver 2
Transmit Signaling Input for Transceiver 3
Transmit Signaling Input for Transceiver 4
Transmit System Sync for Transceiver 1
Transmit System Sync for Transceiver 2
Transmit System Sync for Transceiver 3
Transmit System Sync for Transceiver 4
Test/Reset
Transmit Sync for Transceiver 1
Transmit Sync for Transceiver 2
Transmit Sync for Transceiver 3
Transmit Sync for Transceiver 4
Transmit System Clock for Transceiver 1
Transmit System Clock for Transceiver 2
Transmit System Clock for Transceiver 3
Transmit System Clock for Transceiver 4
Transmit Analog Tip Output for Transceiver 1
Transmit Analog Tip Output for Transceiver 1
Transmit Analog Tip Output for Transceiver 2
Transmit Analog Tip Output for Transceiver 2
Transmit Analog Tip Output for Transceiver 3
Transmit Analog Tip Output for Transceiver 3
Transmit Analog Tip Output for Transceiver 4
Transmit Analog Tip Output for Transceiver 4
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Positive Supply
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Transmit Analog Signal Ground
Write Input (Read/Write)
38 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
5.9 Packages
The package diagrams below show the lead pattern that will be placed on the target PC board. This is the
same pattern that would be seen as viewed from the top.
Figure 5-1. DS21455 Pin Diagram, 27mm BGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
RNEGI3
RFSYNC3
RLINK3
RCLKI3
DVSS
ESIBS13
TCLKO3
TPOSI3
DVDD
TSIG3
TSYSCLK3
RLCLK2
RLINK2
CS2
RCLKI2
RPOSO2
DVSS
B
RPOSO3
RPOSI3
DVDD
RCLKO3
CS3
DVDD
DVSS
TCHCLK3
DVSS
TCLK3
DVSS
DVDD
RCLK2
RPOSI2
RNEGO2
RSIG2
ESIBS12
TSSYNC2
TCLK2
TNEGO2
C
RSIG3
RNEGO3
EISBRD3
DVDD
TVSS
TLINK3
TSYNC3
TCLKI3
TPOSO3
TSER3
TCHBLK3
DVDD
EISBRD2
RCLKO2
RSIGF2
DVDD
TSER2
TSIG2
TPOSO2
TPOSI2
D
RSYNC3
RSIGF3
RLCLK3
RVSS
RVSS
TLCLK3
ESIBS03
TNEGI3
TNEGO3
TSSYNC3
TVDD
RSYNC2
RNEGI2
RCHCLK2
RSER2
DVDD
TCLKI2
TSYNC2
E
RLOS3
RSER3
RCLK3
RVDD
RLOS2
TCLKO2
TLINK2
TLCLK2
F
RLCLK1
BPCLK3
RSYSCLK2
ESIBS02
TNEGI2
TCHBLK2
G
RSYNC1
RLINK1
RCHBLK2
TVSS
TVDD
DVDD
H
RSYSCLK1
RLOS1
DVSS
A5
BPCLK2
N.C.
RVSS
DVSS
J
RCHCLK1
RSER1
DVDD
EISBRD1
RVDD
RVSS
D1/AD1
ESIBS14
K
RSIGF1
LIUC/TPD
WR
RFSYNC1
CS4
RLCLK4
TSSYNC4
TSER4
L
RMSYNC1
RSIG1
RNEGO1
RPOSO1
A1
TCHCLK4
TSIG4
DVSS
M
BPCLK1
RCHBLK1
RCLKO1
RCLKI1
DVDD
RCLK4
TCLK4
DVDD
N
JTDI
RD
RCLK1
DVDD
DVSS
TSYSCLK4
TPOSO4
TNEGO4
P
RVDD1
BTS
CS1
A7/ALE
(AS)
RNEGI4
DVDD
TCLKO4
TCLKI4
R
TNEGI1
RVSS
RNEGI1
RPOSI1
RCLKI4
TSYNC4
TPOSI4
TNEGI4
T
MCLK1
RVSS
TNEGO1
A3
RCLKO4
TLCLK4
TLINK4
ESIBS04
U
INT
DVDD
A0
D7/AD7
D5/AD5
DVSS
D3/AD3
A6
D4/AD4
MUX
D0/AD0
RLINK4
EISBRD4
RCHCLK4
RPOSO4
TSTRST
RNEGO4
TVSS
TVDD
TCHBLK4
V
TSYNC1
A2
TLCLK1
D6/AD6
DVDD
TCLKI1
TPOSO1
A4
ESIBS11
TCHCLK1
RLOS4
RSYNC4
BPCLK4
RFSYNC4
RPOSI4
RSIGF4
N.C.
JTRST
JTDO
RVSS
W
TCHBLK1
TVDD
TPOSI1
TVSS
TLINK1
ESIBS01
TCLKO1
DVSS
TSER1
TSIG1
JTMS
RSYSCLK4
D2/AD2
RMSYNC4
RSER4
RVDD
RVSS
MCLK2
Y
TTIP1
TRING1
TTIP2
TRING2
TTIP3
TRING3
TTIP4
TRING4
TCLK1
RTIP1
RTIP2
RRING2
JTCLK
RTIP3
RRING3
RSIG4
RTIP4
RRING4
RMSYNC3 RCHCLK3
RMSYNC2 RFSYNC2
RSYSCLK3 RCHBLK3
TSYSCLK1 TSSYNC1
RRING1
RCHBLK4
18
19
TCHCLK2 TSYSCLK2
20
DVSS
NOTE: Locations C3, C13, J4, and U13 are used for the Extended System Information Bus (ESIB). These pin locations
on the DS21Q352, DS21Q354, DS21Q552, and DS21Q554 are connected to ground. When replacing a
DS21Qx5y with a DS21455, these signals should be routed to control logic to gain access to the ESIB. If these
pins remain connected to ground, the ESIB function will be disabled. Pins labeled as “N.C.” must be
unconnected.
39 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 5-2. DS21458 Pin Diagram, 17mm CSBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
TNEG0
RCLKO3
TSSYNC3
RVSS
RVSS
RRING3
RTIP3
RVSS
RVDD
RD (DS)
TVDD
TVSS
TRING2
TTIP2
TCLKO2
TPOSO2
B
TPOSO3
TCLKO3
TSYNC3
TCHCLK3
RSYNC3
RLCLK3
RSIG3
RSYSCLK3
A5
BTS
TVDD
TVSS
TRING2
TTIP2
TNEGO2
TSYNC2
C
TTIP3
TTIP3
RLINK3
TLCLK3
RSER3
WR (R/W)
JTDI
DVDD
DVDD
DVDD
RCLKO2
RLINK2
TLCLK2
D
TRING3
TRING3
DVDD
DVSS
UNUSED
TPD
D1/AD1
DVSS
DVSS
DVSS
TSSYNC2 TCHCLK2
E
TVSS
TVSS
DVDD
DVSS
UNUSED RMSYNC3
F
TVDD
TVDD
DVDD
DVSS
TSIG3
G
D6/AD6
A7/ALE
(AS)
D7/AD7
A3
H
RVDD
A0
A2
J
RVSS
K
RTIP
RSIG1
L
RRING1
RCHCLK1
M
RVSS
RLCLK1
N
RVSS
TCHBLK1
TSYNC1
P
TLCLK1
RLINK1
R
RCLKO1
T
TNEGO1
TCHBLK3 RFSYNC3 RCHBLK3
RLOS/
LOTC3
RCHCLK3 TSYSCLK3
RVSS
RSIGF3
BPCLK3
UNUSED
A1
TSIG2
UNUSED
TCHBLK2
RSYNC2
RLOS/
LOTC2
RVSS
TCLK3
UNUSED
RNEGO3
RPOSO3
RCLK2
TLINK3
UNUSED
UNUSED
RSIGF2
RLCLK2
RRING2
RCLK3
TSER3
TLINK3
UNUSED
TSER2
RSIG2
RTIP2
MCLK1
INT
A8
TSYSCLK1
ESIBRD
UNUSED
UNUSED
RNEGO2
RPOSO2
BPCLK2
RSER2
RSYSCLK2
RVSS
RSER1
BPCLK1
RPOSO1
TCHCLK1
ESIBS0
ESIBS1
TSYSCLK2
A9
MCLK2
TEST2
TEST1
JTMS
RVDD
RLOS/
LOTC1
RSYNC1
TLINK1
RCLK1
UNUSED
TSER4
TSIG4
RCLK4
JTDO
JTRST
JSTRST
JTCLK
TCLK1
UNUSED
TSIG1
TSYSCLK4
TCLK4
UNUSED
UNUSED
TLINK4
DVSS
DVDD
TVDD
TVDD
UNUSED
TSER1
D4/AD4
CS
UNUSED
DVSS
DVDD
TVSS
TVSS
DVSS
DVSS
DVSS
A4
D2/AD2
BPCLK4
RPOSO4
RSIGF4
RSYNC4
DVSS
DVDD
TRING4
TRING4
UNUSED
DVDD
DVDD
DVDD
D3/AD3
D0/AD0
RSER4
RNEGO4
RFSYNC4
RLOS/
LOTC4
TCHCLK4
RCLKO4
TTIP4
TTIP4
TPOSO1
TTIP1
TRING1
TVSS
TVDD
D5/AD5
MUX
RSYSCLK4
RSIG4
RCHBLK4
RLCLK4
TCHBLK4
TSYNC4
TPOSO4
TCLKO4
TCLKO1
TTIP1
TRING1
TVSS
TVDD
A6
RVDD
RVSS
RTIP4
RRING4
RVSS
RVSS
TLCLK4
RLINK4
TNEGO4
RNEGO1 RSYSCLK1
RCHBLK1 RFSYNC1
RSIGF1
UNUSED
RMSYNC1 TSSYNC1
RCHBLK2 RCHCLK2
RCHCLK4 RMSYNC4 TSSYNC4
NOTE: Pins labeled as “UNUSED” must be connected to VSS.
40 of 270
TCLK2
RMSYNC2 RFSYNC2
DS21455/DS21458 Quad T1/E1/J1 Transceivers
6. PARALLEL PORT
The transceiver is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The transceiver can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in
the AC Electrical Characteristics for more details.
6.1 Register Map
Table 6-1. REGISTER MAP SORTED BY ADDRESS
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
REGISTER NAME
Master Mode Register
I/O Configuration Register 1
I/O Configuration Register 2
T1 Receive Control Register 1
T1 Receive Control Register 2
T1 Transmit Control Register 1
T1 Transmit Control Register 2
T1 Common Control Register 1
Software Signaling Insertion Enable 1
Software Signaling Insertion Enable 2
Software Signaling Insertion Enable 3
Software Signaling Insertion Enable 4
T1 Receive Digital Milliwatt Enable Register 1
T1 Receive Digital Milliwatt Enable Register 2
T1 Receive Digital Milliwatt Enable Register 3
Device Identification Register
Information Register 1
Information Register 2
Information Register 3
—
Interrupt Information Register 1
Interrupt Information Register 2
Status Register 1
Interrupt Mask Register 1
Status Register 2
Interrupt Mask Register 2
Status Register 3
Interrupt Mask Register 3
Status Register 4
Interrupt Mask Register 4
Status Register 5
Interrupt Mask Register 5
Status Register 6
Interrupt Mask Register 6
Status Register 7
Interrupt Mask Register 7
Status Register 8
Interrupt Mask Register 8
Status Register 9
Interrupt Mask Register 9
Per-Channel Pointer Register
Per-Channel Data Register 1
41 of 270
REGISTER
ABBREVIATION
MSTRREG
IOCR1
IOCR2
T1RCR1
T1RCR2
T1TCR1
T1TCR2
T1CCR1
SSIE1
SSIE2
SSIE3
SSIE4
T1RDMR1
T1RDMR2
T1RDMR3
IDR
INFO1
INFO2
INFO3
—
IIR1
IIR2
SR1
IMR1
SR2
IMR2
SR3
IMR3
SR4
IMR4
SR5
IMR5
SR6
IMR6
SR7
IMR7
SR8
IMR8
SR9
IMR9
PCPR
PCDR1
PAGE
49
78
79
53
53
55
56
57
104
104
105
105
61
61
61
72
62
170
69
—
51
51
171
172
72
73
74
75
76
77
118
118
150
151
150
151
125
126
190
191
46
47
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ADDRESS
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
REGISTER NAME
Per-Channel Data Register 2
Per-Channel Data Register 3
Per-Channel Data Register 4
Information Register 4
Information Register 5
Information Register 6
Information Register 7
HDLC #1 Receive Control
HDLC #2 Receive Control
E1 Receive Control Register 1
E1 Receive Control Register 2
E1 Transmit Control Register 1
E1 Transmit Control Register 2
BOC Control Register
Receive Signaling Change Of State Information 1
Receive Signaling Change Of State Information 2
Receive Signaling Change Of State Information 3
Receive Signaling Change Of State Information 4
Receive Signaling Change Of State Interrupt Enable 1
Receive Signaling Change Of State Interrupt Enable 2
Receive Signaling Change Of State Interrupt Enable 3
Receive Signaling Change Of State Interrupt Enable 4
Signaling Control Register
Error Count Configuration Register
Line Code Violation Count Register 1
Line Code Violation Count Register 2
Path Code Violation Count Register 1
Path Code Violation Count Register 2
Frames Out of Sync Count Register 1
Frames Out of Sync Count Register 2
E-Bit Count Register 1
E-Bit Count Register 2
Loopback Control Register
Per-Channel Loopback Enable Register 1
Per-Channel Loopback Enable Register 2
Per-Channel Loopback Enable Register 3
Per-Channel Loopback Enable Register 4
Elastic Store Control Register
Transmit Signaling Register 1
Transmit Signaling Register 2
Transmit Signaling Register 3
Transmit Signaling Register 4
Transmit Signaling Register 5
Transmit Signaling Register 6
Transmit Signaling Register 7
Transmit Signaling Register 8
Transmit Signaling Register 9
Transmit Signaling Register 10
Transmit Signaling Register 11
Transmit Signaling Register 12
Transmit Signaling Register 13
Transmit Signaling Register 14
Transmit Signaling Register 15
42 of 270
REGISTER
ABBREVIATION
PCDR2
PCDR3
PCDR4
INFO4
INFO5
INFO6
INFO7
H1RC
H2RC
E1RCR1
E1RCR2
E1TCR1
E1TCR2
BOCC
RSINFO1
RSINFO2
RSINFO3
RSINFO4
RSCSE1
RSCSE2
RSCSE3
RSCSE4
SIGCR
ERCNT
LCVCR1
LCVCR2
PCVCR1
PCVCR2
FOSCR1
FOSCR2
EBCR1
EBCR2
LBCR
PCLR1
PCLR2
PCLR3
PCLR4
ESCR
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS13
TS14
TS15
PAGE
47
47
47
152
152
152
69
144
144
64
65
66
67
124
99
99
99
99
99
99
99
99
96
85
87
87
88
88
90
90
90
90
80
83
83
84
84
117
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ADDRESS
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
REGISTER NAME
Transmit Signaling Register 16
Receive Signaling Register 1
Receive Signaling Register 2
Receive Signaling Register 3
Receive Signaling Register 4
Receive Signaling Register 5
Receive Signaling Register 6
Receive Signaling Register 7
Receive Signaling Register 8
Receive Signaling Register 9
Receive Signaling Register 10
Receive Signaling Register 11
Receive Signaling Register 12
Receive Signaling Register 13
Receive Signaling Register 14
Receive Signaling Register 15
Receive Signaling Register 16
Common Control Register 1
Common Control Register 2
Common Control Register 3
Common Control Register 4
Transmit Channel Monitor Select
Transmit DS0 Monitor Register
Receive Channel Monitor Select
Receive DS0 Monitor Register
Line Interface Control 1
Line Interface Control 2
Line Interface Control 3
Line Interface Control 4
Unused. Must be set = 00h for proper operation
Transmit Line Build-Out Control
Idle Array Address Register
Per-Channel Idle Code Value Register
Transmit Idle Code Enable Register 1
Transmit Idle Code Enable Register 2
Transmit Idle Code Enable Register 3
Transmit Idle Code Enable Register 4
Receive Idle Code Enable Register 1
Receive Idle Code Enable Register 2
Receive Idle Code Enable Register 3
Receive Idle Code Enable Register 4
Receive Channel Blocking Register 1
Receive Channel Blocking Register 2
Receive Channel Blocking Register 3
Receive Channel Blocking Register 4
Transmit Channel Blocking Register 1
Transmit Channel Blocking Register 2
Transmit Channel Blocking Register 3
Transmit Channel Blocking Register 4
HDLC #1 Transmit Control
HDLC #1 FIFO Control
HDLC #1 Receive Channel Select 1
HDLC #1 Receive Channel Select 2
43 of 270
REGISTER
ABBREVIATION
TS16
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS13
RS14
RS15
RS16
CCR1
CCR2
CCR3
CCR4
TDS0SEL
TDS0M
RDS0SEL
RDS0M
LIC1
LIC2
LIC3
LIC4
—
TLBC
IAAR
PCICR
TCICE1
TCICE2
TCICE3
TCICE4
RCICE1
RCICE2
RCICE3
RCICE4
RCBR1
RCBR2
RCBR3
RCBR4
TCBR1
TCBR2
TCBR3
TCBR4
H1TC
H1FC
H1RCS1
H1RCS2
PAGE
102
97
97
97
97
97
97
97
97
97
97
97
97
97
97
97
97
71
208
209
210
91
91
92
92
164
167
168
169
—
166
110
110
110
110
111
111
111
111
112
112
113
113
114
114
113
114
115
115
143
145
146
146
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ADDRESS
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
REGISTER NAME
HDLC #1 Receive Channel Select 3
HDLC #1 Receive Channel Select 4
HDLC #1 Receive Time Slot Bits/Sa Bits Select
HDLC #1 Transmit Channel Select1
HDLC #1 Transmit Channel Select 2
HDLC #1 Transmit Channel Select 3
HDLC #1 Transmit Channel Select 4
HDLC #1 Transmit Time Slot Bits/Sa Bits Select
HDLC #1 Receive Packet Bytes Available
HDLC #1 Transmit FIFO
HDLC #1 Receive FIFO
HDLC #1 Transmit FIFO Buffer Available
HDLC #2 Transmit Control
HDLC #2 FIFO Control
HDLC #2 Receive Channel Select 1
HDLC #2 Receive Channel Select 2
HDLC #2 Receive Channel Select 3
HDLC #2 Receive Channel Select 4
HDLC #2 Receive Time Slot Bits/Sa Bits Select
HDLC #2 Transmit Channel Select 1
HDLC #2 Transmit Channel Select 2
HDLC #2 Transmit Channel Select 3
HDLC #2 Transmit Channel Select 4
HDLC #2 Transmit Time Slot Bits/Sa Bits Select
HDLC #2 Receive Packet Bytes Available
HDLC #2 Transmit FIFO
HDLC #2 Receive FIFO
HDLC #2 Transmit FIFO Buffer Available
Extend System Information Bus Control Register 1
Extend System Information Bus Control Register 2
Extend System Information Bus Register 1
Extend System Information Bus Register 2
Extend System Information Bus Register 3
Extend System Information Bus Register 4
In-Band Code Control Register
Transmit Code Definition Register 1
Transmit Code Definition Register 2
Receive Up Code Definition Register 1
Receive Up Code Definition Register 2
Receive Down Code Definition Register 1
Receive Down Code Definition Register 2
In-Band Receive Spare Control Register
Receive Spare Code Definition Register 1
Receive Spare Code Definition Register 2
Receive FDL Register
Transmit FDL Register
Receive FDL Match Register 1
Receive FDL Match Register 2
Unused. Must be set = 00h for proper operation
Interleave Bus Operation Control Register
Receive Align Frame Register
Receive Nonalign Frame Register
Receive Si Align Frame
44 of 270
REGISTER
ABBREVIATION
H1RCS3
H1RCS4
H1RTSBS
H1TCS1
H1TCS2
H1TCS3
H1TCS4
H1TTSBS
H1RPBA
H1TF
H1RF
H1TFBA
H2TC
H2FC
H2RCS1
H2RCS2
H2RCS3
H2RCS4
H2RTSBS
H2TCS1
H2TCS2
H2TCS3
H2TCS4
H2TTSBS
H2RPBA
H2TF
H2RF
H2TFBA
ESIBCR1
ESIBCR2
ESIB1
ESIB2
ESIB3
ESIB4
IBCC
TCD1
TCD2
RUPCD1
RUPCD2
RDNCD1
RDNCD2
RSCC
RSCD1
RSCD2
RFDL
TFDL
RFDLM1
RFDLM2
—
IBOC
RAF
RNAF
RSiAF
PAGE
146
146
147
148
148
148
148
149
153
154
154
153
143
145
146
146
146
146
147
148
148
148
148
149
153
154
154
153
205
206
207
207
207
207
180
181
181
182
182
183
184
184
185
185
156
157
156
156
—
200
128
128
130
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ADDRESS
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3–F9, FA–FF
REGISTER NAME
Receive Si Nonalign Frame
Receive Remote Alarm Bits
Receive Sa4 Bits
Receive Sa5 Bits
Receive Sa6 Bits
Receive Sa7 Bits
Receive Sa8 Bits
Transmit Align Frame Register
Transmit Nonalign Frame Register
Transmit Si Align Frame
Transmit Si Nonalign Frame
Transmit Remote Alarm Bits
Transmit Sa4 Bits
Transmit Sa5 Bits
Transmit Sa6 Bits
Transmit Sa7 Bits
Transmit Sa8 Bits
Transmit Sa Bit Control Register
BERT Alternating Word Count Rate
BERT Repetitive Pattern Set Register 1
BERT Repetitive Pattern Set Register 2
BERT Repetitive Pattern Set Register 3
BERT Repetitive Pattern Set Register 4
BERT Control Register 1
BERT Control Register 2
Unused. Must be set = 00h for proper operation
BERT Bit Count Register 1
BERT Bit Count Register 2
BERT Bit Count Register 3
BERT Bit Count Register 4
BERT Error Count Register 1
BERT Error Count Register 2
BERT Error Count Register 3
BERT Interface Control Register
Error Rate Control Register
Number Of Errors 1
Number Of Errors 2
Number Of Errors Left 1
Number Of Errors Left 2
Unused. Must be set = 00h for proper operation
Pulse Shape Adjustment 1
Pulse Shape Adjustment 2
Unused. Must be set = 00h for proper operation
45 of 270
REGISTER
ABBREVIATION
RSiNAF
RRA
RSa4
RSa5
RSa6
RSa7
RSa8
TAF
TNAF
TSiAF
TSiNAF
TRA
TSa4
TSa5
TSa6
TSa7
TSa8
TSACR
BAWC
BRP1
BRP2
BRP3
BRP4
BC1
BC2
—
BBC1
BBC2
BBC3
BBC4
BEC1
BEC2
BEC3
BIC
ERC
NOE1
NOE2
NOEL1
NOEL2
—
PSA1
PSA2
—
PAGE
131
131
132
137
133
133
134
129
129
135
136
136
137
137
138
138
139
140
191
192
192
192
192
187
188
—
193
193
193
193
194
194
194
189
196
197
197
198
198
—
—
—
—
DS21455/DS21458 Quad T1/E1/J1 Transceivers
7. SPECIAL PER-CHANNEL REGISTER OPERATION
Some of the features described in the data sheet that operate on a per-channel basis use a special method
for channel selection. The registers involved are the per-channel pointer registers (PCPR) and per-channel
data registers 1 to 4 (PCDR1–4). The user selects the function(s) that are to be applied on a per-channel
basis by setting the appropriate bit(s) in the PCPR register. The user then writes to the PCDR registers to
select the channels for that function. The following is an example of mapping the transmit and receive
BERT function to channels 9, 10, 11, 12, 20, and 21:
Write 11h to PCPR
Write 00h to PCDR1
Write 0fh to PCDR2
Write 18h to PCDR3
Write 00h to PCDR4
More information about how to use these per-channel features can be found in their respective sections in
the data sheet.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSAOICS
0
PCPR
Per-Channel Pointer Register
28h
6
RSRCS
0
5
RFCS
0
4
BRCS
0
3
THSCS
0
2
PEICS
0
Bit 0/BERT Transmit Channel Select (BTCS).
Bit 1/Transmit Fractional Channel Select (TFCS).
Bit 2/Payload Error Insert Channel Select (PEICS).
Bit 3/Transmit Hardware Signaling Channel Select (THSCS).
Bit 4/BERT Receive Channel Select (BRCS).
Bit 5/Receive Fractional Channel Select (RFCS).
Bit 6/Receive Signaling Reinsertion Channel Select (RSRCS).
Bit 7/Receive Signaling All Ones Insertion Channel Select (RSAOICS).
46 of 270
1
TFCS
0
0
BTCS
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
PCDR1
Per-Channel Data Register 1
29h
Bit #
Name
Default
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
Register Name:
Register Description:
Register Address:
PCDR2
Per-Channel Data Register 2
2Ah
Bit #
Name
Default
7
6
5
4
3
2
1
0
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
Register Name:
Register Description:
Register Address:
PCDR3
Per-Channel Data Register 3
2Bh
Bit #
Name
Default
7
6
5
4
3
2
1
0
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
Register Name:
Register Description:
Register Address:
PCDR4
Per-Channel Data Register 4
2Ch
Bit #
Name
Default
7
6
5
4
3
2
1
0
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
47 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
8. PROGRAMMING MODEL
The DS21455/DS21458 register map is divided into three groups: T1 specific features, E1 specific
features, and common features. The typical programming sequence begins with issuing a reset to the
device, selecting T1 or E1 operation in the master mode register, enabling T1 or E1 functions, and
enabling the common functions. The act of resetting the device automatically clears all configuration and
status registers. Therefore, it is not necessary to load unused registers with zeros.
Figure 8-1. Programming Sequence
POWER-ON
ISSUE RESET
SELECT T1 OR E1 OPERATION IN
MASTER MODE REGISTER
PROGRAM E1 SPECIFIC REGISTERS
PROGRAM T1 SPECIFIC REGISTERS
PROGRAM COMMON REGISTERS
DS21455/DS21458 OPERATIONAL
48 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
8.1 Power-Up Sequence
The DS21455/DS21458 contain an on-chip power-up reset function, which automatically clears the
writeable register space immediately after power is supplied to the device. The user can issue a chip reset
at any time. Issuing a reset will disrupt traffic until the device is reprogrammed. The reset can be issued
through hardware using the TSTRST pin or through software using the SFTRST function in the master
mode register. The LIRST (LIC2.6) should be toggled from zero to one to reset the line interface
circuitry. (It will take the DS21455/DS21458 about 40ms to recover from the LIRST bit being toggled.)
Finally, after the TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores
should be reset (this step can be skipped if the elastic stores are disabled).
8.1.1 Master Mode Register
Register Name:
Register Description:
Register Address:
MSTRREG
Master Mode Register
00h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
TEST1
0
2
TEST0
0
1
T1/E1
0
0
SFTRST
0
Bit 0/Software Issued Reset (SFTRST).
A 0 to 1 transition causes the register space to be cleared. A reset clears all configuration and status registers. The bit
automatically clears itself when the reset has completed.
Bit 1/Operating Mode (T1/E1).
Used to select the operating mode of the framer/formatter (digital) portion of the DS21455. The operating mode of the LIU
must also be programmed.
0 = T1 operation
1 = E1 operation
Bits 2, 3/Test Mode Bits (TEST0, TEST1).
Test modes are used to force the output pins of the DS21455 into known states. This can facilitate the checkout of assemblies
during the manufacturing process and also be used to isolate devices from shared buses.
TEST1
0
0
1
1
TEST0
0
1
0
1
EFFECT ON OUTPUT PINS
Operate normally
Force all output pins into tri-state (including all I/O pins and parallel port pins)
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
Bits 4–7/Unused, must be set to zero for proper operation.
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8.2 Interrupt Handling
Various alarms, conditions, and events in the DS21455/DS21458 can cause interrupts. For simplicity,
these are all referred to as events in this explanation. All STATUS registers can be programmed to
produce interrupts. Each status register has an associated interrupt mask register. For example, SR1
(Status Register 1) has an interrupt control register called IMR1 (Interrupt Mask Register 1). Status
registers are the only sources of interrupts. On power-up, all writeable registers are automatically cleared.
Since bits in the IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no
interrupts can occur until the host selects which events are to product interrupts. Since there are
potentially many sources of interrupts, several features are available to help sort out and identify which
event is causing an interrupt. When an interrupt occurs, the host should first read the IIR1, IIR2, and IIR3
registers (interrupt information registers) to identify which status register(s) is producing the interrupt.
Once that is determined, the individual status register or registers can be examined to determine the exact
source. In eight port configurations, two DS21455/DS21458s can be connected together via the 3-wire
ESIB feature. This allows all eight transceivers to be interrogated by a single CPU port read cycle. The
host can determine the synchronization status or interrupt status of eight devices with a single read. The
ESIB feature also allows the user to select from various events to be examined via this method. For more
information, see the ESIB section in this data sheet.
Once an interrupt has occurred, the interrupt handler routine should clear the IMRx registers to stop
further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt
hander routine should restore the state of the IMRx registers.
8.3 Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the
appropriate bit in a status register will be set to a one. All of the status registers operate in a latched
fashion, which means that if an event or condition occurs a bit is set to a one. It will remain set until the
user reads that bit. An event bit will be cleared when it is read and it will not be set again until the event
has occurred again. Condition bits such as RBL, RLOS, etc., will remain set if the alarm is still present.
The user will always proceed a read of any of the status registers with a write. The byte written to the
register will inform the DS21455/DS21458 which bits the user wishes to read and have cleared. The user
will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a
zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written
to a bit location, the read register will be updated with the latest information. When a zero is written to a
bit position, the read register will not be updated and the previous value will be held. A write to the status
registers will be immediately followed by a read of the same register. This write-read scheme allows an
external microcontroller or microprocessor to individually poll certain bits without disturbing the other
bits in the register. This operation is key in controlling the DS21455/DS21458 with higher-order
languages.
Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically
network conditions such as loss of sync, or all ones detect. Event bits are typically markers such as the
one-second timer, elastic store slip, etc. Each status register bit is labeled as a condition or event bit.
Some of the status registers have bits for both the detection of a condition and the clearance of the
condition. For example, SR2 has a bit that is set when the device goes into a loss of sync state (SR2.0, a
condition bit) and a bit that is set (SR2.4, an event bit) when the loss of sync condition clears (goes in
sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear”
event but rather the status bit can produce interrupts on both edges, setting, and clearing. These bits are
marked as “double interrupt bits.” An interrupt will be produced when the condition occurs and when it
clears.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
8.4 Information Registers
Information registers operate the same as status registers except they cannot cause interrupts. They are all
latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read only
register and it reports the status of the E1 synchronizer in real time. INFO7 and some of the bits in INFO6
and INFO5 are not latched and it is not necessary to precede a read of these bits with a write.
8.5 Interrupt Information Registers
The Interrupt Information Registers provide an indication of which Status Registers (SR1 through SR9)
are generating an interrupt. When an interrupt occurs, the host can read IIR1 and IIR2 to quickly identify
which of the 9 status registers are causing the interrupt.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SR8
0
IIR1
Interrupt Information Register 1
14h
6
SR7
0
5
SR6
0
4
SR5
0
Register Name:
Register Description:
Register Address:
IIR2
Interrupt Information Register 2
15h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
SR4
0
2
SR3
0
1
SR2
0
0
SR1
0
3
—
0
2
—
0
1
—
0
0
SR9
0
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9. CLOCK MAP
Figure 9-1 shows the clock map of the DS21455/DS21458. The routing for the transmit and receive
clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only
one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification
and clarity.
Figure 9-1. Clock Map
MCLK
PRE-SCALER
LIC4.MPS0
LIC4.MPS1
2.048 TO 1.544
SYNTHESIZER
LIC2.3
DJA = 1
8 x PLL
LOCAL
LOOPBACK
RCL = 1
RXCLK
JITTER ATTENUATOR
SEE LIC1 REGISTER
LLB = 0
LTCA
RCL = 0
TO
LIU
JAS = 0
AND
DJA = 0
DJA = 0
REMOTE
LOOPBACK
FRAMER
LOOPBACK
FLB = 0
LLB = 1
JAS = 0
OR
DJA = 1
TXCLK
JAS = 1
OR
DJA = 1
PAYLOAD
LOOPBACK
(SEE NOTES)
BPCLK
SYNTH
RECEIVE
FRAMER
BPCLK
RCLK
FLB = 1
RLB = 1
LTCA
JAS = 1
AND
DJA = 0
8XCLK
RLB = 0
PLB = 1
TRANSMIT
FORMATTER
PLB = 0
TCLK
MUX
A
B
C
TCLK
The TCLK MUX is dependent on the state of the TCSS0 and TCSS1 bits in the LIC1 register and the
state of the TCLK pin.
TCSS1
0
TCSS0
0
0
1
1
0
1
1
TRANSMIT CLOCK SOURCE
The TCLK pin (C) is always the source of Transmit Clock.
Switch to the recovered clock (B) when the signal at the TCLK pin fails to
transition after 1 channel time.
Use the scaled signal (A) derived from MCLK as the Transmit Clock. The TCLK
pin is ignored.
Use the recovered clock (B) as the Transmit Clock. The TCLK pin is ignored.
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10. T1 FRAMER/FORMATTER CONTROL REGISTERS
The T1 framer portion of the DS21455/DS21458 is configured via a set of nine control registers.
Typically, the control registers are only accessed when the system is first powered up. Once the device
has been initialized, the control registers will only need to be accessed when there is a change in the
system configuration. There are two receive-control registers (T1RCR1 and T1RCR2), two transmit
control registers (T1TCR1 and T1TCR2), and a common control register (T1CCR1). Each of these
registers is described in this section.
10.1 T1 Control Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
T1RCR1
T1 Receive Control Register 1
03h
6
ARC
0
5
OOF1
0
4
OOF2
0
3
SYNCC
0
2
SYNCT
0
1
SYNCE
0
0
RESYNC
0
Bit 0/Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive side framer is initiated.
Must be cleared and set again for a subsequent resync.
Bit 1/Sync Enable (SYNCE).
0 = auto resync enabled
1 = auto resync disabled
Bit 2/Sync Time (SYNCT).
0 = qualify 10 bits
1 = qualify 24 bits
Bit 3/Sync Criteria (SYNCC).
In D4 Framing Mode:
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode:
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
Bits 4 to 5/Out-of-Frame Select Bits (OOF2, OOF1).
OOF2
0
0
1
1
OOF1
0
1
0
1
OUT-OF-FRAME CRITERIA
2/4 frame bits in error
2/5 frame bits in error
2/6 frame bits in error
2/6 frame bits in error
Bit 6/Auto Resync Criteria (ARC).
0 = resync on OOF or RCL event
1 = resync on OOF only
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
T1RCR2
T1 Receive Control Register 2
04h
6
RFM
0
5
RB8ZS
0
4
RSLC96
0
3
RZSE
0
2
RZBTSI
0
1
RJC
0
0
RD4YM
0
Bit 0/Receive Side D4 Yellow Alarm Select (RD4YM).
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
Bit 1/Receive Japanese CRC6 Enable (RJC).
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Bit 2/Receive Side ZBTSI Support Enable (RZBTSI). Allows ZBTSI information to be output on RLINK pin.
0 = ZBTSI disabled
1 = ZBTSI enabled
Bit 3/Receive FDL Zero Destuffer Enable (RZSE). Set this bit to zero if using the internal HDLC/BOC controller instead of
the legacy support for the FDL. See Legacy FDL Support (T1 Mode) for details.
0 = zero destuffer disabled
1 = zero destuffer enabled
Bit 4/Receive SLC–96 Enable (RSLC96). Only set this bit to a one in SLC-96 framing applications. See D4/SLC–96
Operation for details.
0 = SLC–96 disabled
1 = SLC–96 enabled
Bit 5/Receive B8ZS Enable (RB8ZS).
0 = B8ZS disabled
1 = B8ZS enabled
Bit 6/Receive Frame Mode Select (RFM).
0 = D4 framing mode
1 = ESF framing mode
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TJC
0
T1TCR1
T1 Transmit Control Register 1
05h
6
TFPT
0
5
TCPT
0
4
TSSE
0
3
GB7S
0
2
TFDLS
0
1
TBL
0
0
TYEL
0
Bit 0/Transmit Yellow Alarm (TYEL).
0 = do not transmit yellow alarm
1 = transmit yellow alarm
Bit 1/Transmit Blue Alarm (TBL).
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOS and TNEG
Bit 2/TFDL Register Select (TFDLS).
0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC controller or the TLINK pin
Bit 3/Global Bit 7 Stuffing (GB7S).
0 = allow the SSIEx registers to determine which channels containing all zeros are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of how the SSIEx registers are programmed
Bit 4/Transmit Software Signaling Enable (TSSE).
0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx registers still
define which channels are to have B7 stuffing preformed
1 = source signaling data as enabled by the SSIEx registers
Bit 5/Transmit CRC Pass Through (TCPT).
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F-bit time
Bit 6/Transmit F-Bit Pass Through (TFPT).
0 = F bits sourced internally
1 = F bits sampled at TSER
Bit 7/Transmit Japanese CRC6 Enable (TJC).
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TB8ZS
0
T1TCR2
T1 Transmit Control Register 2
06h
6
TSLC96
0
5
TZSE
0
4
FBCT2
0
3
FBCT1
0
2
TD4YM
0
1
TZBTSI
0
0
TB7ZS
0
Bit 0/Transmit Side Bit 7 Zero Suppression Enable (TB7ZS).
0 = no stuffing occurs
1 = Bit 7 force to a one in channels with all zeros
Bit 1/Transmit Side ZBTSI Support Enable (TZBTSI). Allows ZBTSI information to be input on TLINK pin.
0 = ZBTSI disabled
1 = ZBTSI enabled
Bit 2/Transmit Side D4 Yellow Alarm Select (TD4YM).
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12
Bit 3/F-Bit Corruption Type 1. (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4
framing mode) or FPS (ESF framing mode) bits to be corrupted, causing the remote end to experience a loss of
synchronization.
Bit 4/F-Bit Corruption Type 2. (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS
(ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 5/Transmit FDL Zero Stuffer Enable (TZSE). Set this bit to zero if using the internal HDLC controller instead of the
legacy support for the FDL. See I/O Pin Configuration Options for details.
0 = zero stuffer disabled
1 = zero stuffer enabled
Bit 6/Transmit SLC–96/Fs-Bit Insertion Enable (TSLC96). Only set this bit to a one in D4 framing and SLC-96
applications. Must be set to one to source the Fs pattern from the TFDL register. See D4/SLC–96 Operation for details.
0 = SLC–96/Fs-bit insertion disabled
1 = SLC–96/Fs-bit insertion enabled
Bit 7/Transmit B8ZS Enable (TB8ZS).
0 = B8ZS disabled
1 = B8ZS enabled
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
T1CCR1
T1 Common Control Register 1
07h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
TRAI-CI
0
3
TAIS-CI
0
2
TFM
0
1
PDE
0
0
TLOOP
0
Bit 0/Transmit Loop Code Enable (TLOOP). See Programmable In-Band Loop Codes Generation and Detection for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as defined in registers TCD1 and TCD2
Bit 1/Pulse Density Enforcer Enable (PDE). The framer always examines both the transmit and receive data streams for
violations of the following rules, which are required by ANSI T1.403: no more than 15 consecutive zeros and at least N ones
in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the transmit and receive data streams
are reported in the INFO1.6 and INFO1.7 bits respectively. When this bit is set to one, the device will force the transmitted
stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to
zero since B8ZS encoded data streams cannot violate the pulse density requirements.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
Bit 2/Transmit Frame Mode Select (TFM).
0 = D4 framing mode
1 = ESF framing mode
Bit 3/Transmit AIS-CI Enable (TAIS-CI). Setting this bit and the TBL bit (T1TCR1.1) causes the AIS-CI code to be
transmitted at TPOSO and TNEGO, as defined in ANSI T1.403.
0 = do not transmit the AIS-CI code
1 = transmit the AIS-CI code (T1TCR1.1 must also be set = 1)
Bit 4/Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RAI-CI code to be transmitted in the FDL bit
position.
0 = do not transmit the ESF RAI-CI code
1 = transmit the ESF RAI-CI code
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
10.2 T1 Transmit Transparency
The software-signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion
from the transmit-signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIEx
register allows signaling data to be sourced from the signaling registers for that channel.
In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in
the channels. If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will the
channel have bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a
zero when a yellow alarm is transmitted. Also, the user has the option to globally override the SSIEx
registers from determining which channels are to have bit 7 stuffing performed. If the T1TCR1.3 and
T1TCR2.0 bits are set to one, then all 24 T1 channels will have bit 7 stuffing performed on them,
regardless of how the SSIEx registers are programmed. In this manner, the SSIEx registers are only
affecting channels that are to have robbed-bit signaling inserted into them.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
10.3 AIS-CI and RAI-CI Generation and Detection
The DS21455/DS21458 can transmit and detect the RAI-CI and AIS-CI codes in T1 mode. These codes
are compatible with and do not interfere with the standard RAI (Yellow) and AIS (Blue) alarms. These
codes are defined in ANSI T1.403.
The AIS-CI code (alarm indication signal-customer installation) is the same for both ESF and D4
operation. Setting the TAIS-CI bit in the T1CCR1 register and the TBL bit in the T1TCR1 register causes
the DS21455/DS21458 to transmit the AIS-CI code. The RAIS-CI status bit in the SR4 register indicates
the reception of an AIS-CI signal.
The RAI-CI (remote alarm indication-customer installation) code for T1 ESF operation is a special form
of the ESF Yellow Alarm (an unscheduled message). Setting the RAIS-CI bit in the T1CCR1 register
causes the DS21455/DS21458 to transmit the RAI-CI code. The RAI-CI code causes a standard Yellow
Alarm to be detected by the receiver. When the host processor detects a Yellow Alarm, it can then test the
alarm for the RAI-CI state by checking the BOC detector for the RAI-CI flag. That flag is a 011111 code
in the 6-bit BOC message.
The RAI-CI code for T1 D4 operation is a 10001011 flag in all 24 time slots. To transmit the RAI-CI
code the host sets all 24 channels to idle with a 10001011 idle code. Since this code meets the
requirements for a standard T1 D4 Yellow Alarm, the host can use the receive channel monitor function
to detect the 100001011 code whenever a standard Yellow Alarm is detected.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
10.4 T1 Receive-Side Digital-Milliwatt Code Generation
Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers
(T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should
be overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern
that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMRx registers
represents a particular channel. If a bit is set to a one, then the receive data in that channel will be
replaced with the digital-milliwatt code. If a bit is set to zero, no replacement occurs.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH8
0
T1RDMR1
T1 Receive Digital-Milliwatt Enable Register 1
0Ch
6
CH7
0
5
CH6
0
4
CH5
0
3
CH4
0
2
CH3
0
1
CH2
0
0
CH1
0
Bits 0 to 7/Receive Digital-Milliwatt Enable for Channels 1 to 8 (CH1 to CH8).
0 = do not affect the receive data associated with this channel
1 = replace the receive data associated with this channel with digital-milliwatt code
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH16
0
T1RDMR2
T1 Receive Digital-Milliwatt Enable Register 2
0Dh
6
CH15
0
5
CH14
0
4
CH13
0
3
CH12
0
2
CH11
0
1
CH10
0
0
CH9
0
Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 9 to 16 (CH9 to CH16).
0 = do not affect the receive data associated with this channel
1 = replace the receive data associated with this channel with digital-milliwatt code
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH24
0
T1RDMR3
T1 Receive Digital-Milliwatt Enable Register 3
0Eh
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
Bits 0 to 7/Receive Digital-Milliwatt Enable for Channels 17 to 24 (CH17 to CH24).
0 = do not affect the receive data associated with this channel
1 = replace the receive data associated with this channel with digital-milliwatt code
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0
CH17
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
10.5 T1 Information Register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPDV
0
INFO1
Information Register 1
10h
6
TPDV
0
5
COFA
0
4
8ZD
0
3
16ZD
0
2
SEFE
0
1
B8ZS
0
0
FBE
0
Bit 0/Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
Bit 1/B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RPOS and RNEG independent of
whether the B8ZS mode is selected or not via T1TCR2.7. Useful for automatically setting the line coding.
Bit 2/Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in error.
Bit 3/Sixteen Zero Detect Event (16ZD). Set when a string of at least 16 consecutive zeros (regardless of the length of the
string) have been received at RPOSI and RNEGI.
Bit 4/Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the length of the
string) have been received at RPOSI and RNEGI.
Bit 5/Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or multiframe
alignment.
Bit 6/Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not meet the ANSI T1.403
requirements for pulse density.
Bit 7/Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403
requirements for pulse density.
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Table 10-1. T1 ALARM CRITERIA
ALARM
Blue Alarm (AIS) (Note 1)
SET CRITERIA
Over a 3ms window, five or fewer
zeros are received
CLEAR CRITERIA
Over a 3ms window, six or more zeros are
received
D4 Bit-2 Mode (T1RCR2.0 = 0)
Bit 2 of 256 consecutive channels
is set to zero for at least 254
occurrences
Bit 2 of 256 consecutive channels is set to
zero for less than 254 occurrences
D4 12th F-bit Mode (T1RCR2.0 = 1;
this mode is also referred to as the
“Japanese Yellow Alarm”)
12th framing bit is set to one for
two consecutive occurrences
12th framing bit is set to zero for two
consecutive occurrences
ESF Mode
16 consecutive patterns of 00FF
appear in the FDL
192 consecutive zeros are
received
14 or fewer patterns of 00FF hex out of 16
possible appear in the FDL
14 or more ones out of 112 possible bit
positions are received, starting with the
first one received
Yellow Alarm (RAI)
Red Alarm (LRCL) (Also referred to
as Loss of Signal)
Note 1:
The definition of blue alarm (or alarm indication signal) is an unframed, all-ones signal. Blue alarm detectors should be able to
operate properly in the presence of a 10E-3 error rate, and they should not falsely trigger on a framed, all-ones signal. The blue
alarm criteria in the DS21455/DS21458 have been set to achieve this performance. It is recommended that the RBL bit be
qualified with the RLOS bit.
Note 2:
ANSI specifications use a different nomenclature than this data sheet does; the following terms are equivalent:
RBL = AIS
RCL = LOS
RLOS = LOF
RYEL = RAI
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
11. E1 FRAMER/FORMATTER CONTROL REGISTERS
The E1 framer portion of the DS21455/DS21458 is configured via a set of four control registers.
Typically, the control registers are only accessed when the system is first powered up. Once the device
has been initialized, the control registers will only need to be accessed when there is a change in the
system configuration. There are two receive control registers (E1RCR1 and E1RCR2) and two transmit
control registers (E1TCR1 and E1TCR2). There are also four status and information registers. Each of
these eight registers is described in this section.
11.1 E1 Control Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSERC
0
E1RCR1
E1 Receive Control Register 1
33h
6
RSIGM
0
5
RHDB3
0
4
RG802
0
3
RCRC4
0
2
FRC
0
1
SYNCE
0
0
RESYNC
0
Bit 0/Resync (RESYNC). When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent
resync.
Bit 1/Sync Enable (SYNCE).
0 = auto resync enabled
1 = auto resync disabled
Bit 2/Frame Resync Criteria (FRC).
0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
Bit 3/Receive CRC-4 Enable (RCRC4).
0 = CRC-4 disabled
1 = CRC-4 enabled
Bit 4/Receive G.802 Enable (RG802). See the Signaling Operation section for details.
0 = do not force RCHBLK high during bit 1 of time slot 26
1 = force RCHBLK high during bit 1 of time slot 26
Bit 5/Receive HDB3 Enable (RHDB3).
0 = HDB3 disabled
1 = HDB3 enabled
Bit 6/Receive Signaling Mode Select (RSIGM).
0 = CAS signaling mode
1 = CCS signaling mode
Bit 7/RSER Control (RSERC).
0 = allow RSER to output data as received under all conditions
1 = force RSER to one under loss-of-frame alignment conditions
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Table 11-1. E1 SYNC/RESYNC CRITERIA
FRAME OR
MULTIFRAME
LEVEL
FAS
SYNC CRITERIA
RESYNC CRITERIA
FAS present in frame N
and N + 2, and FAS not
present in frame N + 1
ITU SPEC.
Three consecutive incorrect FAS
received
G.706
4.1.1
4.1.2
Alternate: (E1RCR1.2 = 1) The
above criteria is met or three
consecutive incorrect bit 2 of nonFAS received.
CRC-4
CAS
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
Sa8S
0
Two valid MF alignment
words found within 8ms
915 or more CRC-4 codewords out
of 1000 received in error
Valid MF alignment word
found and previous time
slot 16 contains code other
than all zeros
Two consecutive MF alignment
words received in error
G.706
4.2 and 4.3.2
G.732 5.2
E1RCR2
E1 Receive Control Register 2
34h
6
Sa7S
0
5
Sa6S
0
4
Sa5S
0
3
Sa4S
0
2
—
0
1
—
0
0
RCLA
0
Bit 0/Receive Carrier Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a Receive Carrier Loss condition
for both the framer and Line Interface (LIU)
0 = RCL declared upon 255 consecutive zeros (125µs)
1 = RCL declared upon 2048 consecutive zeros (1ms)
Bit 1/Unused, must be set to zero for proper operation.
Bit 2/Unused, must be set to zero for proper operation.
Bit 3/Sa4-Bit Select (Sa4S). Set to one to have RLCLK pulse at the Sa4-bit position; set to zero to force RLCLK low during
Sa4-bit position. See the Functional Timing Diagrams section for details.
Bit 4/Sa5-Bit Select (Sa5S). Set to one to have RLCLK pulse at the Sa5-bit position; set to zero to force RLCLK low during
Sa5-bit position. See the Functional Timing Diagrams section for details.
Bit 5/Sa6-Bit Select (Sa6S). Set to one to have RLCLK pulse at the Sa6-bit position; set to zero to force RLCLK low during
Sa6-bit position. See the Functional Timing Diagrams section for details.
Bit 6/Sa7-Bit Select (Sa7S). Set to one to have RLCLK pulse at the Sa7-bit position; set to zero to force RLCLK low during
Sa7-bit position. See the Functional Timing Diagrams section for details.
Bit 7/Sa8-Bit Select (Sa8S). Set to one to have RLCLK pulse at the Sa8-bit position; set to zero to force RLCLK low during
Sa8-bit position. See the Functional Timing Diagrams section for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TFPT
0
E1TCR1
E1 Transmit Control Register 1
35h
6
T16S
0
5
TUA1
0
4
TSiS
0
3
TSA1
0
2
THDB3
0
1
TG802
0
0
TCRC4
0
Bit 0/Transmit CRC-4 Enable (TCRC4).
0 = CRC-4 disabled
1 = CRC-4 enabled
Bit 1/Transmit G.802 Enable (TG802). See the Functional Timing Diagrams section for details.
0 = do not force TCHBLK high during bit 1 of time slot 26
1 = force TCHBLK high during bit 1 of time slot 26
Bit 2/Transmit HDB3 Enable (THDB3).
0 = HDB3 disabled
1 = HDB3 enabled
Bit 3/Transmit Signaling All Ones (TSA1).
0 = normal operation
1 = force time slot 16 in every frame to all ones
Bit 4/Transmit International Bit Select (TSiS).
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to zero)
Bit 5/Transmit Unframed All Ones (TUA1).
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOSO and TNEGO
Bit 6/Transmit Time Slot 16 Data Select (T16S). See the Transmit Signaling section for details.
0 = time slot 16 determined by the SSIEx registers and the THSCS function in the PCPR register
1 = source time slot 16 from TS1 to TS16 registers
Bit 7/Transmit Time Slot 0 Pass Through (TFPT).
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
Sa8S
0
E1TCR2
E1 Transmit Control Register 2
36h
6
Sa7S
0
5
Sa6S
0
4
Sa5S
0
3
Sa4S
0
2
AEBE
0
1
AAIS
0
0
ARA
0
Bit 0/Automatic Remote Alarm Generation (ARA).
0 = disabled
1 = enabled
Bit 1/Automatic AIS Generation (AAIS).
0 = disabled
1 = enabled
Bit 2/Automatic E-Bit Enable (AEBE).
0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
Bit 3/Sa4-Bit Select (Sa4S). Set to one to source the Sa4 bit from the TLINK pin; set to zero to not source the Sa4 bit. See the
Functional Timing Diagrams section for details.
Bit 4/Sa5-Bit Select (Sa5S). Set to one to source the Sa5 bit from the TLINK pin; set to zero to not source the Sa5 bit. See the
Functional Timing Diagrams section for details.
Bit 5/Sa6-Bit Select (Sa6S). Set to one to source the Sa6 bit from the TLINK pin; set to zero to not source the Sa6 bit. See the
Functional Timing Diagrams section for details.
Bit 6/Sa7-Bit Select (Sa7S). Set to one to source the Sa7 bit from the TLINK pin; set to zero to not source the Sa7 bit. See the
Functional Timing Diagrams section for details.
Bit 7/Sa8-Bit Select (Sa8S). Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit. See the
Functional Timing Diagrams section for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
11.2 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm.
11.2.1 Auto AIS
When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive side framer
to determine if any of the following conditions are present: loss of receive frame synchronization, AIS
alarm (all ones) reception, or loss of receive carrier (or signal). If any one (or more) of the above
conditions is present, then the framer will either force an AIS or remote alarm.
11.2.2 Auto RAI
When automatic RAI generation is enabled (E1TCR2.0 = 1), the framer monitors the receive side to
determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm
(all ones) reception, or loss of receive carrier (or signal) or if CRC-4 multiframe synchronization cannot
be found within 128ms of FAS synchronization (if CRC-4 is enabled). If any one (or more) of the above
conditions is present, then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300
011 specifications and a constant remote alarm will be transmitted if the DS21455/DS21458 cannot find
CRC-4 multiframe synchronization within 400ms as per G.706.
Note: It is an illegal state to have both automatic AIS generation and automatic remote alarm
generation enabled at the same time.
11.2.3 Auto E-Bit
When automatic E-Bit generation is enabled (E1TCR2.2 = 1), and the transmitter is in CRC-4 mode, the
transmitter will automatically set the E-Bit according to the following.
Table 11-2 AUTO E-BIT CONDITIONS
CONDITION
Receive CRC-4 disabled
Receive CRC-4 enabled but not synchronized
Receive CRC-4 enabled, Synchronized, with CRC Sub Multiframe codeword error
Receiver synchronized in CRC-4 mode with no CRC Sub Multiframe codeword errors
E-BIT
STATE
0
0
0
1
11.2.4 G.706 CRC-4 Interworking
G.706 Specifies a method to allow automatic interworking between equipment with and without CRC-4
capability. When basic frame alignment is established the device begins searching for the CRC-4
alignment pattern. If after 8ms the CRC-4 alignment is not found, it is assumed that frame alignment was
invalid and the device returns to the basic frame alignment search to establish new frame alignment.
After the new frame alignment is established the device starts a new 8ms search period for CRC-4
alignment. If CRC-4 alignment is found, the device starts CRC-4 performance monitoring and setting of
the transmitted E-bits according to G.706. (See the Auto E-bit section.) If CRC-4 alignment is not
achieved the device continues to return to the basic frame alignment procedure followed by an 8ms
search period for CRC-4. This process continues for 400ms. At the end of this 400ms period, it is
assumed that the far end equipment is non-CRC-4, the search for CRC-4 alignment is terminated and the
E-bits transmitter toward the far end equipment are set continuously = 0. The DS21455/DS21458 provide
a flexible method for implementing this procedure. Once the device is put into the receive CRC-4 mode, a
counter begins to run. The user can access this counter via Information Register 7.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
11.3 E1 Information Registers
Register Name:
Register Description:
Register Address:
INFO3
Information Register 3
12h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
—
0
2
CRCRC
0
1
FASRC
0
0
CASRC
0
Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error.
(Note: During a CRC resync the FAS synchronizer is brought online to verify the FAS alignment. If during this process a
FAS emulator exists, the FAS synchronizer may temporarily align to the emulator. The FASRC will go active indicating a
search for a valid FAS has been activated.)
Bit 1/FAS Resync Criteria Met Event (FASRC. Set when three consecutive FAS words are received in error.
Bit 2/CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CSC5
0
INFO7
Information Register 7 (Real Time)
30h
6
CSC4
0
5
CSC3
0
4
CSC2
0
3
CSC0
0
2
FASSA
0
1
CASSA
0
0
CRC4SA
0
Bit 0/CRC-4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC-4 MF alignment word.
Bit 1/CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.
Bit 2/FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level.
Bit 3 to 7/CRC-4 Sync Counter Bits (CSC0 and CSC2 to CSC4). The CRC-4 sync counter increments each time the 8msCRC-4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the
CRC-4 level. The counter can also be cleared by disabling the CRC-4 mode (E1RCR1.3 = 0). This counter is useful for
determining the amount of time the framer has been searching for synchronization at the CRC-4 level. ITU G.706 suggests that
if synchronization at the CRC-4 level cannot be obtained within 400ms, then the search should be abandoned and proper action
taken. The CRC-4 sync counter will rollover. CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not
accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.)
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Table 11-3. E1 ALARM CRITERIA
ALARM
RLOS
RCL
RRA
SET CRITERIA
An RLOS condition exists on
power-up prior to initial
synchronization, when a resync
criteria has been met, or when a
manual resync has been initiated
via E1RCR1.0
255 or 2048 consecutive zeros
received as determined by
E1RCR2.0
Bit 3 of non-align frame set to
one for three consecutive
occasions
RUA1
Fewer than three zeros in two
frames (512 bits)
RDMA
Bit 6 of time slot 16 in frame 0
has been set for two consecutive
multiframes
V52LNK
CLEAR CRITERIA
ITU
SPEC.
In 255-bit times, at least 32 ones
are received
G.775/G.962
Bit 3 of nonalign frame set to
zero for three consecutive
occasions
O.162
2.1.4
More than two zeros in two
frames (512 bits)
O.162
1.6.1.2
Two out of three Sa7 bits are
zero
G.965
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
12. COMMON CONTROL AND STATUS REGISTERS
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
CCR1
Common Control Register 1
70h
6
CRC4R
0
5
SIE
0
4
ODM
0
3
—
0
2
TCSS1
0
1
TCSS0
0
0
RLOSF
0
Bit 0/Function of the RLOS/LOTC Output (RLOSF).
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
Bit 1/Transmit Clock Source Select Bit 0 (TCSS0).
Bit 2/Transmit Clock Source Select Bit 1 (TCSS1).
TCSS1
TCSS0
TRANSMIT CLOCK SOURCE
0
0
The TCLK pin is always the source of transmit clock.
0
1
Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition
after one channel time.
1
0
Use the scaled signal present at MCLK as the transmit clock. The TCLK pin is ignored.
1
1
Use the signal present at RCLK as the transmit clock. The TCLK pin is ignored.
Bit 3/Unused, must be set to zero for proper operation.
Bit 4/Output Data Mode (ODM).
0 = pulses at TPOSO and TNEGO are one full TCLKO period wide
1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide
Bit 5/Signaling Integration Enable (SIE).
0 = signaling changes of state reported on any change in selected channels
1 = signaling must be stable for three multiframes for a change of state to be reported
Bit 6/CRC-4 Recalculate (CRC4R) (E1 Only).
0 = transmit CRC-4 generation and insertion operates in normal mode
1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method
Bit 7/ Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ID7
1
IDR
Device Identification Register
0Fh
6
ID6
0
5
ID5
1
4
ID4
1
3
ID3
X
2
ID2
X
1
ID1
X
0
ID0
X
Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip.
IDO is the LSB of a decimal code that represents the chip revision.
Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the device ID.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RYELC
0
SR2
Status Register 2
18h
6
RUA1C
0
5
FRCLC
0
4
RLOSC
0
3
RYEL
0
2
RUA1
0
1
FRCL
0
0
RLOS
0
Bit 0/Receive Loss of Sync Condition (RLOS). Set when the device is not synchronized to the received data stream.
Bit 1/Framer Receive Carrier Loss Condition (FRCL). Set when 255 (or 2048 if E1RCR2.0 = 1) E1 mode or 192 T1 mode
consecutive zeros have been detected at RPOSI and RNEGI.
Bit 2/Receive Unframed All Ones (T1, Blue Alarm, E1, AIS) Condition (RUA1). Set when an unframed all ones code is
received at RPOSI and RNEGI.
Bit 3/Receive Yellow Alarm Condition (RYEL) (T1 Only). Set when a yellow alarm is received at RPOSI and RNEGI.
Bit 4/Receive Loss of Sync Clear Event (RLOSC). Set when the framer achieves synchronization; will remain set until read.
Bit 5/Framer Receive Carrier Loss Clear Event (FRCLC). Set when carrier loss condition at RPOSI and RNEGI is no
longer detected.
Bit 6/Receive Unframed All Ones Clear Event (RUA1C). Set when the unframed all ones condition is no longer detected.
Bit 7/Receive Yellow Alarm Clear Event (RYELC) (T1 Only). Set when the yellow alarm condition is no longer detected.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RYELC
0
IMR2
Interrupt Mask Register 2
19h
6
RUA1C
0
5
FRCLC
0
4
RLOSC
0
3
RYEL
0
Bit 0/Receive Loss of Sync Condition (RLOS).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 1/Framer Receive Carrier Loss Condition (FRCL).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 2/Receive Unframed All Ones (Blue Alarm) Condition (RUA1).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 3/Receive Yellow Alarm Condition (RYEL).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 4/Receive Loss of Sync Clear Event (RLOSC).
0 = interrupt masked
1 = interrupt enabled
Bit 5/Framer Receive Carrier Loss Condition Clear (FRCLC).
0 = interrupt masked
1 = interrupt enabled
Bit 6/Receive Unframed All Ones Condition Clear Event (RUA1C).
0 = interrupt masked
1 = interrupt enabled
Bit 7/Receive Yellow Alarm Clear Event (RYELC).
0 = interrupt masked
1 = interrupt enabled
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2
RUA1
0
1
FRCL
0
0
RLOS
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LSPARE
0
SR3
Status Register 3
1Ah
6
LDN
0
5
LUP
0
4
LOTC
0
3
LORC
0
2
V52LNK
0
1
RDMA
0
0
RRA
0
Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI
Bit 1/Receive Distant MF Alarm Condition (RDMA) (E1 Only). Set when bit 6 of time slot 16 in frame 0 has been set for
two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.
Bit 2/V5.2 Link Detected Condition (V52LNK) (E1 Only). Set on detection of a V5.2 link identification signal. (G.965).
Bit 3/Loss of Receive Clock Condition (LORC). Set when the RCLKI pin has not transitioned for one channel time.
Bit 4/Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for one channel time. Will
force the LOTC pin high if enabled via CCR1.0.
Bit 5/Loop-Up Code Detected Condition (LUP) (T1 Only). Set when the loop up code as defined in the RUPCD1/2 register
is being received. See the Programmable In-Band Loop Code Generation and Detection section for details.
Bit 6/Loop-Down Code Detected Condition (LDN). (T1 only) Set when the loop down code as defined in the RDNCD1/2
register is being received. See the Programmable In-Band Loop Code Generation and Detection section for details.
Bit 7/Spare Code Detected Condition (LSPARE). (T1 only) Set when the spare code as defined in the RSCD1/2 registers is
being received. See the Programmable In-Band Loop Code Generation and Detection section for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LSPARE
0
IMR3
Interrupt Mask Register 3
1Bh
6
LDN
0
5
LUP
0
4
LOTC
0
3
LORC
0
Bit 0/Receive Remote Alarm Condition (RRA).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 1/Receive Distant MF Alarm Condition (RDMA).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 2/V5.2 Link Detected Condition (V52LNK).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 3/Loss of Receive Clock Condition (LORC).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 4/Loss of Transmit Clock Condition (LOTC).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 5/Loop-Up Code Detected Condition (LUP).
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
Bit 6/Loop-Down Code Detected Condition (LDN).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
Bit 7/Spare Code Detected Condition (LSPARE).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
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2
V52LNK
0
1
RDMA
0
0
RRA
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RAIS-CI
0
SR4
Status Register 4
1Ch
6
RSA1
0
5
RSA0
0
4
TMF
0
3
TAF
0
2
RMF
0
1
RCMF
0
0
RAF
0
Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250ms at the beginning of align frames. Used to alert the host
that Si and Sa bits are available in the RAF and RNAF registers.
Bit 1/Receive CRC-4 Multiframe Event (RCMF) (E1 Only). Set on CRC-4 multiframe boundaries; will continue to be set
every 2ms on an arbitrary boundary if CRC-4 is disabled.
Bit 2/Receive Multiframe Event (RMF).
E1 Mode: Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the
host that signaling data is available.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
Bit 3/Transmit Align Frame Event (TAF) (E1 Only). Set every 250ms at the beginning of align frames. Used to alert the
host that the TAF and TNAF registers need to be updated.
Bit 4/Transmit Multiframe Event (TMF).
E1 Mode: Set every 2ms (regardless if CRC-4 is enabled) on transmit multiframe boundaries. Used to alert the host that
signaling data needs to be updated.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
Bit 5/Receive Signaling All Zeros Event (RSA0) (E1 Only). Set when over a full MF time slot 16 contains all zeros.
Bit 6/Receive Signaling All Ones Event (RSA1) (E1 Only). Set when the contents of time slot 16 contains fewer than three
zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
Bit 7/Receive AIS-CI Event (RAIS-CI) (T1 Only). Set when the receiver detects the AIS-CI pattern as defined in ANSI
T1.403.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RAIS-CI
0
IMR4
Interrupt Mask Register 4
1Dh
6
RSA1
0
5
RSA0
0
4
TMF
0
3
TAF
0
Bit 0/Receive Align Frame Event (RAF).
0 = interrupt masked
1 = interrupt enabled
Bit 1/Receive CRC-4 Multiframe Event (RCMF).
0 = interrupt masked
1 = interrupt enabled
Bit 2/Receive Multiframe Event (RMF).
0 = interrupt masked
1 = interrupt enabled
Bit 3/Transmit Align Frame Event (TAF).
0 = interrupt masked
1 = interrupt enabled
Bit 4/Transmit Multiframe Event (TMF).
0 = interrupt masked
1 = interrupt enabled
Bit 5/Receive Signaling All-Zeros Event (RSA0).
0 = interrupt masked
1 = interrupt enabled
Bit 6/Receive Signaling All-Ones Event (RSA1).
0 = interrupt masked
1 = interrupt enabled
Bit 7/Receive AIS-CI Event (RAIS-CI)
0 = interrupt masked
1 = interrupt enabled
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2
RMF
0
1
RCMF
0
0
RAF
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
13. I/O PIN CONFIGURATION OPTIONS
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSMS
0
IOCR1
I/O Configuration Register 1
01h
6
RSMS2
0
5
RSMS1
0
4
RSIO
0
3
TSDW
0
2
TSM
0
1
TSIO
0
0
ODF
0
Bit 0/Output Data Format (ODF).
0 = bipolar data at TPOSO and TNEGO
1 = NRZ data at TPOSO; TNEGO = 0
Bit 1/TSYNC I/O Select (TSIO).
0 = TSYNC is an input
1 = TSYNC is an output
Bit 2/TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin.
0 = frame mode
1 = multiframe mode
Bit 3/TSYNC Double-Wide (TSDW) (T1 Only). (Note: This bit must be set to zero when IOCR1.2 = 1 or when
IOCR1.1 = 0.)
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
Bit 4/RSYNC I/O Select (RSIO). (Note: this bit must be set to zero when ESCR.0 = 0.)
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
Bit 5/RSYNC Mode Select 1 (RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In input
mode (elastic store must be enabled) multiframe mode is only useful when receive signaling re-insertion is enabled.
0 = frame mode
1 = multiframe mode
Bit 6/RSYNC Mode Select 2 (RSMS2).
T1 Mode: RSYNC pin must be programmed in the output frame mode (IOCR1.5 = 0, IOCR1.4 = 0).
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
E1 Mode: RSYNC pin must be programmed in the output multiframe mode
(IOCR1.5 = 1, IOCR1.4 = 0).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC-4 multiframe boundaries
Bit 7/RSYNC Multiframe Skip Control (RSMS). Useful in framing format conversions from D4 to ESF. This function is not
available when the receive-side elastic store is enabled. RSYNC must be set to output multiframe pulses (IOCR1.5 = 1 and
IOCR1.4 = 0).
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
IOCR2
I/O Configuration Register 2
02h
Bit #
Name
Default
7
6
5
4
3
2
1
0
RCLKINV
TCLKINV
RSYNCINV
TSYNCINV
TSSYNCINV
H100EN
TSCLKM
RSCLKM
0
0
0
0
0
0
0
0
Bit 0/RSYSCLK Mode Select (RSCLKM).
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz or IBO enabled (See the Interleaved PCM Bus Operation section.)
Bit 1/TSYSCLK Mode Select (TSCLKM).
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048/4.096/8.192MHz or IBO enabled (See the Interleaved PCM Bus Operation section.)
Bit 2/H.100 SYNC Mode (H100EN).
0 = normal operation
1 = SYNC shift
Bit 3/TSSYNC Invert (TSSYNCINV).
0 = no inversion
1 = invert
Bit 4/TSYNC Invert (TSYNCINV).
0 = no inversion
1 = invert
Bit 5/RSYNC Invert (RSYNCINV).
0 = no inversion
1 = invert
Bit 6/TCLK Invert (TCLKINV).
0 = no inversion
1 = invert
Bit 7/RCLK Invert (RCLKINV).
0 = no inversion
1 = invert
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
14. LOOPBACK CONFIGURATIONS
The DS21455/DS21458 have four loopback configurations including Framer, Payload, Local, and
Remote loopback. Figure 14-1 depicts a normal signal flow without any loopbacks enabled.
Payload loopback may be done on a per-channel basis if both the transmit and receive paths are
synchronous (RCLK = TCLK and RSYNC = TSYNC). See Section 14.1.
Figure 14-1. Normal Signal Flow Diagram
RECEIVE
LIU
JITTER
ATTENUATOR
RECEIVE
FRAMER
BACKPLANE
I/F
TRANSMIT
LIU
JITTER
ATTENUATOR
TRANSMIT
FRAMER
BACKPLANE
I/F
NORMAL MODE
Register Name:
Register Description:
Register Address:
LBCR
Loopback Control Register
4Ah
Bit #
Name
Default
6
—
0
7
LTS
0
5
—
0
4
LIUC
0
3
LLB
0
2
RLB
0
1
PLB
0
0
FLB
0
Bit 0/Framer Loopback (FLB).
0 = loopback disabled
1 = loopback enabled
RECEIVE
LIU
JITTER
ATTENUATOR
RECEIVE
FRAMER
BACKPLANE
I/F
TRANSMIT
LIU
JITTER
ATTENUATOR
TRANSMIT
FRAMER
BACKPLANE
I/F
FRAMER LOOPBACK
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
This loopback is useful in testing and debugging applications. In FLB, the device will loop data from the transmit side back to
the receive side. When FLB is enabled, the following will occur:
1) T1 Mode: An unframed all ones code will be transmitted at TPOSO and TNEGO.
E1 Mode: Normal data will be transmitted at TPOSO and TNEGO.
2) Data at RPOSI and RNEGI will be ignored.
3) All receive-side signals will take on timing synchronous with TCLK instead of RCLKI.
4) Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable
condition.
Bit 1/Payload Loopback (PLB).
0 = loopback disabled
1 = loopback enabled
RECEIVE
LIU
JITTER
ATTENUATOR
RECEIVE
FRAMER
BACKPLANE
I/F
TRANSMIT
LIU
JITTER
ATTENUATOR
TRANSMIT
FRAMER
BACKPLANE
I/F
PAYLOAD LOOPBACK (CAN BE DONE ON A PER-CHANNEL BASIS)
When PLB is enabled, the following will occur:
1)
2)
3)
4)
5)
Data will be transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of TCLK.
All of the receive side signals will continue to operate normally.
The TCHCLK and TCHBLK signals are forced low.
Data at the TSER, TDATA, and TSIG pins is ignored.
The TLCLK signal will become synchronous with RCLK instead of TCLK.
T1 Mode: Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4
framing applications. In a PLB situation, the device will loop the 192 bits of payload data (with BPVs corrected) from the
receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back,
they are reinserted by the device.
E1 Mode: In a PLB situation, the device will loop the 248 bits of payload data (with BPVs corrected) from the receive section
back to the transmit section. The transmit section will modify the payload as if it was input at TSER. The FAS word, Si, Sa
and E bits, and CRC-4 are not looped back, they are reinserted by the device.
Bit 2/Remote Loopback (RLB). In this loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the
TPOSO and TNEGO pins. Data will continue to pass through the receive side framer of the device as it would normally and
the data from the transmit side formatter will be ignored.
0 = loopback disabled
1 = loopback enabled
RECEIVE
LIU
JITTER
ATTENUATOR
RECEIVE
FRAMER
BACKPLANE
I/F
TRANSMIT
LIU
JITTER
ATTENUATOR
TRANSMIT
FRAMER
BACKPLANE
I/F
REMOTE LOOPBACK
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Bit 3/Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the
transceiver. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback
will pass through the jitter attenuator.
0 = loopback disabled
1 = loopback enabled
RECEIVE
LIU
JITTER
ATTENUATOR
RECEIVE
FRAMER
BACKPLANE
I/F
TRANSMIT
LIU
JITTER
ATTENUATOR
TRANSMIT
FRAMER
BACKPLANE
I/F
LOCAL LOOPBACK
Bit 4/Line Interface Unit Mux Control (LIUC). This bit along with the LIUC/TPD pin and LBCR.7 controls the connection
between the LIU and the Framer. See the LTS (LBCR.7) description below. When the LIUC/TPD pin is connected high or
LBCR.7 = 1, the LIUC bit has control. When the LIUC/TPD pin is connected low the framer and LIU are separated and the
LIUC bit has no effect. For the DS21458 this bit should always be set = 0.
Table 14-1. LIUC CONTROL
LBCR.7
(LTS)
LIUC/TPD
PIN
LBCR.4
(LIUC)
0
0
0
0
0
1
0
1
0
0
1
1
1
x
0
1
x
1
FUNCTION
LIU and Framer Separated
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins active
(This function not available on the DS21458)
LIU and Framer Separated
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins active
(This function not available on the DS21458)
LIU and Framer Connected
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins ignored
(This function not available on the DS21458)
LIU and Framer Separated
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins active
(This function not available on the DS21458)
LIU and Framer Connected
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins ignored
LIU and Framer Separated
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins active
(This function not available on the DS21458)
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/LIUC/TPD Pin Function Select (LTS). This bit selects the function the of the LIUC/TPD pin. On the DS21458, this
bit should always be set = 1.
0 = LIUC/TPD pin functions as the LIUC control (This function is not available on the DS21458)
1 = LIUC/TPD pin functions as the TPD control
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
14.1 Per-Channel Payload Loopback
The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane
should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this
loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method
to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on
which channels can be looped back or on how many channels can be looped back.
Each of the bit position in the PCLRs (PCLR1/PCLR2/PCLR3/PCLR4) represent a DS0 channel in the
outgoing frame. When these bits are set to a one, data from the corresponding receive channel will
replace the data from the TSER pin for that channel.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH8
0
PCLR1
Per-Channel Loopback Enable Register 1
4Bh
6
CH7
0
5
CH6
0
4
CH5
0
3
CH4
0
2
CH3
0
1
CH2
0
0
CH1
0
1
CH10
0
0
CH9
0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 1 to 8 (CH1 to CH8).
0 = loopback disabled
1 = enable loopback. Source data from the corresponding receive channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH16
0
PCLR2
Per-Channel Loopback Enable Register 2
4Ch
6
CH15
0
5
CH14
0
4
CH13
0
3
CH12
0
2
CH11
0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 9 to 16 (CH9 to CH16).
0 = loopback disabled
1 = enable loopback. Source data from the corresponding receive channel
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH24
0
PCLR3
Per-Channel Loopback Enable Register 3
4Dh
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
0
CH17
0
1
CH26
0
0
CH25
0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 17 to 24 (CH17 to CH24).
0 = loopback disabled
1 = enable loopback. Source data from the corresponding receive channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH32
0
PCLR4
Per-Channel Loopback Enable Register 4
4Eh
6
CH31
0
5
CH30
0
4
CH29
0
3
CH28
0
2
CH27
0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 25 to 32 (CH25 to CH32).
0 = loopback disabled
1 = enable loopback. Source data from the corresponding receive channel
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
15. ERROR COUNT REGISTERS
The DS21455/DS21458 contain four counters that are used to accumulate line coding errors, path errors,
and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode
only), 62ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When
updated automatically, the user can use the interrupt from the timer to determine when to read these
registers. All four counters will saturate at their respective maximum counts and they will not rollover
(Note: Only the line-code violation count register has the potential to overflow but the bit error would
have to exceed 10E-2 before this would occur).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
ERCNT
Error Counter Configuration Register
41h
6
MECU
0
5
ECUS
0
4
EAMS
0
3
VCRFS
0
2
FSBE
0
1
MOSCRF
0
0
LCVCRF
0
Bit 0/T1 Line Code Violation Count Register Function Select (LCVCRF).
0 = do not count excessive zeros
1 = count excessive zeros
Bit 1/Multiframe Out-of-Sync Count Register Function Select (MOSCRF).
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
Bit 2/PCVCR Fs-Bit Error Report Enable (FSBE).
0 = do not report bit errors in Fs-bit position; only Ft-bit position
1 = report bit errors in Fs-bit position as well as Ft-bit position
Bit 3/E1 Line Code Violation Count Register Function Select (VCRFS).
0 = count Bipolar Violations (BPVs)
1 = count Code Violations (CVs)
Bit 4/Error Accumulation Mode Select (EAMS).
0 = ERCNT.5 determines accumulation time
1 = ERCNT.6 determines accumulation time
Bit 5/Error Counter Update Select (ECUS).
T1 Mode: 0 = Update error counters once a second
1 = Update error counters every 42ms (333 frames)
E1 Mode: 0 = Update error counters once a second
1 = Update error counters every 62.5ms (500 frames)
Bit 6/Manual Error Counter Update (MECU). When enabled by ERCNT.4, the changing of this bit from a zero to a one
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a
minimum of 1.5 RCLK clock periods before reading the error count registers to allow for proper update.
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
15.1 Line Code Violation Count Register (LCVCR)
15.1.1 T1 Operation
T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mode is set
for the receive side, then B8ZS codewords are not counted. This counter is always enabled; it is not
disabled during receive loss of synchronization (RLOS = 1) conditions.
Table 15-1. T1 LINE CODE VIOLATION COUNTING OPTIONS
COUNT EXCESSIVE
ZEROS?
(ERCNT.0)
No
Yes
No
Yes
B8ZS ENABLED?
(T1RCR2.5)
No
No
Yes
Yes
WHAT IS COUNTED IN THE LCVCRs
BPVs
BPVs + 16 Consecutive Zeros
BPVs (B8ZS Codewords Not Counted)
BPVs + 8 Consecutive Zeros
15.1.2 E1 Operation
Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive
marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side, then HDB3
codewords are not counted as BPVs. If ERCNT.3 is set, then the LVC counts code violations as defined
in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most
applications, the framer should be programmed to count BPVs when receiving AMI code and to count
CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync
conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would
have to be greater than 10** -2 before the VCR would saturate.
Table 15-2. E1 LINE CODE VIOLATION COUNTING OPTIONS
E1 CODE VIOLATION SELECT
(ERCNT.3)
0
1
WHAT IS COUNTED IN THE
LCVCRs
BPVs
CVs
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LCVC15
0
LCVCR1
Line Code Violation Count Register 1
42h
6
LCVC14
0
5
LCVC13
0
4
LCVC12
0
3
LCVC11
0
2
LCVC10
0
1
LCVC9
0
0
LCCV8
0
Bits 0 to 7/Line Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation
count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LCVC7
0
LCVCR2
Line Code Violation Count Register 2
43h
6
LCVC6
0
5
LCVC5
0
4
LCVC4
0
3
LCVC3
0
2
LCVC2
0
1
LCVC1
0
0
LCVC0
0
Bits 0 to 7/Line Code Violation Counter Bits 0 to 7 (LCVC0 to LCVC7). LCV0 is the LSB of the 16-bit code violation
count.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
15.2 Path Code Violation Count Register (PCVCR)
15.2.1 T1 Operation
The path code violation count register records either Ft, Fs, or CRC6 errors in T1 frames. When the
receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the
CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft
framing bit position. Via the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs
framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS = 1)
conditions. See Table 15-3 for a detailed description of exactly what errors the PCVCR counts.
Table 15-3. T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS
FRAMING MODE
D4
D4
ESF
COUNT Fs ERRORS?
No
Yes
Don’t Care
WHAT IS COUNTED IN THE PCVCRs
Errors in the Ft Pattern
Errors in Both the Ft and Fs Patterns
Errors in the CRC6 Codewords
15.2.2 E1 Operation
The PCVCR records CRC-4 errors. Since the maximum CRC-4 count in a one-second period is 1000, this
counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4 level; it
will continue to count if loss of multiframe sync occurs at the CAS level.
The PCVCR1 is the most significant word and PCVCR2 is the least significant word of a 16-bit counter
that records path violations (PVs).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
PCVC15
0
PCVCR1
Path Code Violation Count Register 1
44h
6
PCVC14
0
5
PCVC13
0
4
PCVC12
0
3
PCVC11
0
2
PCVC10
0
1
PCVC9
0
0
PCVC8
0
Bits 0 to 7/Path Code Violation Counter Bits 8 to 15 (PCVC8 to PCVC15). PCVC15 is the MSB of the 16-bit path code
violation count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
PCVC7
0
PCVCR2
Path Code Violation Count Register 2
45h
6
PCVC6
0
5
PCVC5
0
4
PCVC4
0
3
PCVC3
0
2
PCVC2
0
1
PCVC1
0
0
PCVC0
0
Bits 0 to 7/Path Code Violation Counter Bits 0 to 7 (PCVC0 to PCVC7). PCVC0 is the LSB of the 16-bit path code
violation count.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
15.3 Frames Out Of Sync Count Register (FOSCR)
15.3.1 T1 Operation
The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This
number is useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and
ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this
mode, it is not disabled during receive loss of synchronization (RLOS = 1) conditions. The FOSCR has
alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or
errors in the FPS framing pattern (in the ESF mode). When the FOSCR is operated in this mode, it is
disabled during receive loss of synchronization (RLOS = 1) conditions. See Table 15-4 for a detailed
description of what the FOSCR is capable of counting.
Table 15-4. T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS
FRAMING MODE
(T1RCR1.3)
D4
D4
ESF
ESF
COUNT MOS OR F-BIT ERRORS
(ERCNT.1)
MOS
F-Bit
MOS
F-Bit
WHAT IS COUNTED IN THE
FOSCRs
Number of Multiframes Out of Sync
Errors in the Ft Pattern
Number of Multiframes Out of Sync
Errors in the FPS Pattern
15.3.2 E1 Operation
The FOSCR counts word errors in the frame alignment signal in time slot 0. This counter is disabled
when RLOS is high. FAS errors will not be counted when the framer is searching for FAS alignment
and/or synchronization at either the CAS or CRC-4 multiframe level. Since the maximum FAS word
error count in a one-second period is 4000, this counter cannot saturate.
The FOSCR1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16bit counter that records frames out of sync.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FOS15
0
FOSCR1
Frames Out Of Sync Count Register 1
46h
6
FOS14
0
5
FOS13
0
4
FOS12
0
3
FOS11
0
2
FOS10
0
1
FOS9
0
0
FOS8
0
Bits 0 to 7/Frames Out of Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out of sync
count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FOS7
0
FOSCR2
Frames Out Of Sync Count Register 2
47h
6
FOS6
0
5
FOS5
0
4
FOS4
0
3
FOS3
0
2
FOS2
0
1
FOS1
0
0
FOS0
0
Bits 0 to 7/Frames Out of Sync Counter Bits 0 to 7 (FOS0 to FOS7). FOS0 is the LSB of the 16-bit frames out of sync
count.
15.4 E-Bit Counter Register (EBCR)
This counter is only available in the E1 mode. EBCR1 (EBCR1) is the most significant word and EBCR2
is the least significant word of a 16-bit counter that records far end block errors (FEBE), as reported in
the first bit of frames 13 and 15 on E1 lines running with CRC-4 multiframe. These count registers will
increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a onesecond period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either
the FAS or CRC-4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EB15
0
EBCR1
E-Bit Count Register 1
48h
6
EB14
0
5
EB13
0
4
EB12
0
3
EB11
0
2
EB10
0
1
EB9
0
0
EB8
0
Bits 0 to 7/E-Bit Counter Bits 8 to 15 (EB8 to EB15). EB15 is the MSB of the 16-bit E-bit count.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EB7
0
EBCR2
E-Bit Count Register 2
49h
6
EB6
0
5
EB5
0
4
EB4
0
3
EB3
0
2
EB2
0
1
EB1
0
Bits 0 to 7/E-Bit Counter Bits 0 to 7 (EB0 to EB7). EB0 is the LSB of the 16-bit E-bit count.
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0
EB0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
16. DS0 MONITORING FUNCTION
The DS21455/DS21458 can monitor one DS0 64kbps channel in the transmit direction and one DS0
channel in the receive direction at the same time. In the transmit direction the user will determine which
channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the
receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0
channel pointed to by the TCM0 to TCM4 bits will appear in the transmit DS0 monitor (TDS0M) register
and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the receive DS0 (RDS0M)
register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode
of the appropriate T1 or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1
channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit
direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values
would be programmed into TDS0SEL and RDS0SEL:
TCM4 = 0
TCM3 = 0
TCM2 = 1
TCM1 = 0
TCM0 = 1
RCM4 = 0
RCM3 = 1
RCM2 = 1
RCM1 = 1
RCM0 = 0
16.1 Transmit DS0 Monitor Registers
Register Name:
Register Description:
Register Address:
TDS0SEL
Transmit Channel Monitor Select
74h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
TCM4
0
3
TCM3
0
2
TCM2
0
1
TCM1
0
0
TCM0
0
Bits 0 to 4 Transmit Channel Monitor Bits (TCM0 to TCM4). TCM0 is the LSB of a 5-bit channel select that determines
which transmit channel data will appear in the TDS0M register.
Bits 5 to 7/Unused, must be set to zero for proper operation.
Register Name:
Register Description:
Register Address:
TDS0M
Transmit DS0 Monitor Register
75h
Bit #
Name
Default
6
B2
0
7
B1
0
5
B3
0
4
B4
0
3
B5
0
2
B6
0
1
B7
0
0
B8
0
Bits 0 to 7/Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the transmit channel
monitor select register. B8 is the LSB of the DS0 channel (last bit to be transmitted).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
16.2 Receive DS0 Monitor Registers
Register Name:
Register Description:
Register Address:
RDS0SEL
Receive Channel Monitor Select
76h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
RCM4
0
3
RCM3
0
2
RCM2
0
1
RCM1
0
0
RCM0
0
Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel-select that determines
which receive DS0 channel data will appear in the RDS0M register.
Bits 5 to 7/Unused, must be set to zero for proper operation.
Register Name:
Register Description:
Register Address:
RDS0M
Receive DS0 Monitor Register
77h
Bit #
Name
Default
6
B2
0
7
B1
0
5
B3
0
4
B4
0
3
B5
0
2
B6
0
1
B7
0
0
B8
0
Bits 0 to 7/Receive DS0 Channel Bits (B1 to B8). Receive-channel data that has been selected by the receive-channel
monitor-select register. B8 is the LSB of the DS0 channel (last bit to be received).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17. SIGNALING OPERATION
There are two methods to access receive signaling data and provide transmit signaling data: processorbased (i.e., software-based) or hardware-based. Processor-based refers to access through the transmit and
receive signaling registers, RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG
pins. Both methods can be used simultaneously.
17.1 Receive Signaling
Figure 17-1. Simplified Diagram of Receive Signaling Path
PER-CHANNEL
CONTROL
T1/E1 DATA STREAM
SIGNALING
EXTRACTION
RECEIVE SIGNALING
REGISTERS
CHANGE OF STATE
INDICATION
REGISTERS
ALL
ONES
RE-INSERTION
CONTROL
SIGNALING
BUFFERS
93 of 270
RSER
RSYNC
RSIG
DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.1.1 Processor-Based Receive Signaling
The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and
copied into the receive signaling registers, RS1 through RS16. In T1 mode, only RS1 through RS12 are
used. The signaling information in these registers is always updated on multiframe boundaries. This
function is always enabled.
17.1.1.1 Change Of State
In order to avoid constant monitoring of the receive signaling registers, the DS21455/DS21458 can be
programmed to alert the host when any specific channel or channels undergo a change of their signaling
state. RSCSE1 through RSCSE4 for E1 and RSCSE1 through RSCSE3 for T1 are used to select which
channels can cause a change of state indication. The change of state is indicated in Status Register 5
(SR1.5). If signaling integration, CCR1.5, is enabled then the new signaling state must be constant for
three multiframes before a change of state indication is indicated. The user can enable the INT pin to
toggle low upon detection of a change in signaling by setting the IMR1.5 bit. The signaling integration
mode is global and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the
RSINFO1 through RSINFO4 registers. The information from this registers will tell the user which RSx
register to read for the new signaling data. All changes are indicated in the RSINFO1–RSINFO4 register
regardless of the RSCSE1–RSCSE4 registers.
17.1.2 Hardware-Based Receive Signaling
In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin.
RSIG is a signaling PCM-stream output on a channel-by-channel basis from the signaling buffer. The
signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSER. The
signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted
into the original data stream in a different alignment that is determined by a multiframe signal from the
RSYNC pin. In this mode, the receive elastic store can be enabled or disabled. If the receive elastic store
is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF
framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The
RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the
AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6
contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is updated once a
multiframe (1.5ms) unless a freeze is in effect. See the Functional Timing Diagrams for some examples.
17.1.2.1 Receive-Signaling Reinsertion at RSER
In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will be
reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the
RSER data stream. The original signaling data based on the Fs/ESF frame positions and the realigned
data based on the user supplied multiframe sync applied at RSYNC. In voice channels this extra copy of
signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is
activated on a per-channel basis. For reinsertion, the elastic store must be enabled; however, the
backplane clock can be either 1.544MHz or 2.048MHz.
Signaling reinsertion mode is enabled, on a per-channel basis by setting the RSRCS bit high in the PCPR
register. The channels that are to have signaling reinserted are selected by writing to the PCDR1-PCDR3
registers for T1 mode and PCDR1–PCDR4 registers for E1 mode. In E1 mode, the user will generally
select all channels when doing reinsertion.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.1.2.2 Force Receive Signaling All Ones
In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling-bit positions to a one.
This is done by using the per-channel register, which is described in the Special Per-Channel Operation
section. The user sets the BTCS bit in the PCPR register. The channels that are to be forced to one are
selected by writing to the PCDR1–PCDR3 registers.
17.1.2.3 Receive-Signaling Freeze
The signaling data in the four-multiframe signaling buffer will be frozen in a known good state upon
either a loss of synchronization (OOF event), carrier loss, or frame slip. This action meets the
requirements of BellCore TR–TSY–000170 for signaling freezing. To allow this freeze action to occur,
the RFE control bit (SIGCR.4) should be set high. The user can force a freeze by setting the RFF control
bit (SIGCR.3) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The
four multiframe buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin
(and at the RSER pin if receive signaling reinsertion is enabled). When freezing is enabled (RFE = 1), the
signaling data will be held in the last known good state until the corrupting error condition subsides.
When the error condition subsides, the signaling data will be held in the old state for at least an additional
9ms (or 4.5ms in D4 framing mode) before being allowed to be updated with new signaling data.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
SIGCR
Signaling Control Register
40h
Bit #
Name
Default
6
—
0
7
GRSRE
0
5
—
0
4
RFE
0
3
RFF
0
2
RCCS
0
1
TCCS
0
0
FRSAO
0
Bit 0/Force Receive Signaling All Ones (FRSAO). In T1 mode, this bit forces all signaling data at the RSIG and RSER pin to
all ones. This bit has no effect in E1 mode.
0 = normal signaling data at RSIG and RSER
1 = force signaling data at RSIG and RSER to all ones
Bit 1/Transmit Time Slot Control for CAS Signaling (TCCS). Controls the order that signaling is transmitted from the
transmit signaling registers. This bit should be set = 0 in T1 mode.
0 = signaling data is CAS format
1 = signaling data is CCS format
Bit 2/Receive Time Slot Control for CAS Signaling (RCCS). Controls the order that signaling is placed into the receive
signaling registers. This bit should be set = 0 in T1 mode.
0 = signaling data is CAS format
1 = signaling data is CCS format
Bit 3/Receive Force Freeze (RFF). Freezes receive-side signaling at RSIG (and RSER if receive signaling reinsertion is
enabled); will override receive-freeze enable (RFE). See the Receive Signaling Freeze section.
0 = do not force a freeze event
1 = force a freeze event
Bit 4/Receive Freeze Enable (RFE). See the Receive Signaling Freeze section.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER if receive signaling reinsertion is enabled).
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling channels
without programming all channels through the per-channel function.
0 = do not reinsert all signaling
1 = reinsert all signaling
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
(MSB)
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
Register Name:
Register Description:
Register Address:
(MSB)
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
RS1 to RS12
Receive Signaling Registers (T1 Mode, ESF Format)
60h to 6Bh
CH2-C
CH4-C
CH6-C
CH8-C
CH10-C
CH12-C
CH14-C
CH16-C
CH18-C
CH20-C
CH22-C
CH24-C
CH2-D
CH4-D
CH6-D
CH8-D
CH10-D
CH12-D
CH14-D
CH16-D
CH18-D
CH20-D
CH22-D
CH24-D
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
CH1-C
CH3-C
CH5-C
CH7-C
CH9-C
CH11-C
CH13-C
CH15-C
CH17-C
CH19-C
CH21-C
CH23-C
(LSB)
CH1-D
CH3-D
CH5-D
CH7-D
CH9-D
CH11-D
CH13-D
CH15-D
CH17-D
CH19-D
CH21-D
CH23-D
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS1 to RS12
Receive Signaling Registers (T1 Mode, D4 Format)
60h to 6Bh
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
(LSB)
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
Note: In D4 format, TS1–TS12 contain signaling data for two frames. Bold type indicates data for second frame.
97 of 270
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
(MSB)
0
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH26-A
CH28-A
CH30-A
0
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
CH26-B
CH28-B
CH30-B
Register Name:
Register Description:
Register Address:
(MSB)
1
9
17
25
33
41
49
57
65
73
81
89
97
105
113
121
2
10
18
26
34
42
50
58
66
74
82
90
98
106
114
122
RS1 to RS16
Receive Signaling Registers (E1 Mode, CAS Format)
60h to 6Fh
0
CH2-C
CH4-C
CH6-C
CH8-C
CH10-C
CH12-C
CH14-C
CH16-C
CH18-C
CH20-C
CH22-C
CH24-C
CH26-C
CH28-C
CH30-C
0
CH2-D
CH4-D
CH6-D
CH8-D
CH10-D
CH12-D
CH14-D
CH16-D
CH18-D
CH20-D
CH22-D
CH24-D
CH26-D
CH28-D
CH30-D
X
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
CH25-A
CH27-A
CH29-A
Y
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
CH25-B
CH27-B
CH29-B
X
CH1-C
CH3-C
CH5-C
CH7-C
CH9-C
CH11-C
CH13-C
CH15-C
CH17-C
CH19-C
CH21-C
CH23-C
CH25-C
CH27-C
CH29-C
(LSB)
X
CH1-D
CH3-D
CH5-D
CH7-D
CH9-D
CH11-D
CH13-D
CH15-D
CH17-D
CH19-D
CH21-D
CH23-D
CH25-D
CH27-D
CH29-D
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS13
RS14
RS15
RS16
(LSB)
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
128
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS13
RS14
RS15
RS16
RS1 to RS16
Receive Signaling Registers (E1 Mode, CCS Format)
60h to 6Fh
3
11
19
27
35
43
51
59
67
75
83
91
99
107
115
123
4
12
20
28
36
44
52
60
68
76
84
92
100
108
116
124
5
13
21
29
37
45
53
61
69
77
85
93
101
109
117
125
6
14
22
30
38
46
54
62
70
78
86
94
102
110
118
126
98 of 270
7
15
23
31
39
47
55
63
71
79
87
95
103
111
119
127
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
(MSB)
CH8
CH16
CH24
CH7
CH15
CH23
RSCSE1, RSCSE2, RSCSE3, RSCSE4
Receive Signaling Change Of State Interrupt Enable
3Ch, 3Dh, 3Eh, 3Fh
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
(LSB)
CH1
CH9
CH17
CH25
RSCSE1
RSCSE2
RSCSE3
RSCSE4
Setting any of the CH1 through CH30 bits in the RSCSE1 through RSCSE4 registers will cause an interrupt when that
channel’s signaling data changes state.
Register Name:
Register Description:
Register Address:
(MSB)
CH8
CH16
CH24
CH7
CH15
CH23
RSINFO1, RSINFO2, RSINFO3, RSINFO4
Receive Signaling Change Of State Information
38h, 39h, 3Ah, 3Bh
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
(LSB)
CH1
CH9
CH17
CH25
RSINFO1
RSINFO2
RSINFO3
RSINFO4
When a channel’s signaling data changes state, the respective bit in registers RSINFO1-4 will be set. If the channel was also
enabled as an interrupt source by setting the appropriate bit in RSCSE1–4, an interrupt is generated. The bit will remain set
until read.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.2 Transmit Signaling
Figure 17-2.Simplified Diagram of Transmit Signaling Path
TRANSMIT
SIGNALING
REGISTERS
1
0
0
T1/E1 DATA
STREAM
TSER
0
1
1
B7
SIGNALING
BUFFERS
TSIG
T1TCR1.4
PER-CHANNEL
CONTROL
PER-CHANNEL
CONTROL
PCPR.3
SSIE1 - SSIE4
ONLY APPLIES TO T1 MODE
17.2.1 Processor-Based Transmit Signaling
In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1–TS16) via
the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register
for placement in the appropriate bit position in the outgoing data stream. The user can utilize the transmit
multiframe interrupt in status register 4 (SR4.4) to know when to update the signaling bits. The user need
not update any transmit signaling register for which there is no change of state for that register.
Each transmit signaling register contains the robbed-bit signaling (T1) or TS16 CAS signaling (E1) for
two time slots that will be inserted into the outgoing stream if enabled to do so via T1TCR1.4 (T1 Mode)
or E1TCR1.6 (E1 Mode). In T1 mode, only TS1 through TS12 are used.
Signaling data can be sourced from the TS registers on a per-channel basis by utilizing the softwaresignaling insertion-enable registers, SSIE1 through SSIE4.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.2.1.1 T1 Mode
In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1–TS12 contain a
full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel
(A and B). In T1 D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions
for the next multiframe. In D4 mode, two multiframes of signaling data can be loaded into TS1–TS12.
The framer will load the contents of TS1–TS12 into the outgoing shift register every other D4
multiframe. In D4 mode the host should load new contents into TS1–TS12 on every other multiframe
boundary and no later than 120µs after the boundary.
17.2.1.2 E1 Mode
In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common
channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two
different channel number schemes in E1. In channel numbering, TS0 through TS31 are labeled channels 1
through 32. In phone-channel numbering, TS1 through TS15 are labeled channel 1 through channel 15,
and TS17 through TS31 are labeled channel 15 through channel 30.
Table 17-1. TIME SLOT NUMBERING SCHEMES
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TS
Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Phone
Channel
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
(MSB)
0
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH26-A
CH28-A
CH30-A
0
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
CH26-B
CH28-B
CH30-B
Register Name:
Register Description:
Register Address:
(MSB)
1
17
33
49
65
81
97
113
13
29
45
61
77
93
109
125
2
18
34
50
66
82
98
114
14
30
46
62
78
94
110
126
TS1 to TS16
Transmit Signaling Registers (E1 Mode, CAS Format)
50h to 5Fh
0
CH2-C
CH4-C
CH6-C
CH8-C
CH10-C
CH12-C
CH14-C
CH16-C
CH18-C
CH20-C
CH22-C
CH24-C
CH26-C
CH28-C
CH30-C
0
CH2-D
CH4-D
CH6-D
CH8-D
CH10-D
CH12-D
CH14-D
CH16-D
CH18-D
CH20-D
CH22-D
CH24-D
CH26-D
CH28-D
CH30-D
X
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
CH25-A
CH27-A
CH29-A
Y
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
CH25-B
CH27-B
CH29-B
X
CH1-C
CH3-C
CH5-C
CH7-C
CH9-C
CH11-C
CH13-C
CH15-C
CH17-C
CH19-C
CH21-C
CH23-C
CH25-C
CH27-C
CH29-C
(LSB)
X
CH1-D
CH3-D
CH5-D
CH7-D
CH9-D
CH11-D
CH13-D
CH15-D
CH17-D
CH19-D
CH21-D
CH23-D
CH25-D
CH27-D
CH29-D
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS13
TS14
TS15
TS16
TS1 to TS16
Transmit Signaling Registers (E1 Mode, CCS Format)
50h to 5Fh
3
19
35
51
67
83
99
115
15
31
47
63
89
95
111
127
4
20
36
52
68
84
100
116
16
32
48
64
80
96
112
128
5
9
25
41
57
73
89
105
121
21
37
53
69
85
101
117
6
10
26
42
58
74
90
106
122
22
38
54
70
86
102
118
102 of 270
7
11
27
43
59
75
91
107
123
23
39
55
71
87
103
119
(LSB)
8
12
28
44
60
76
92
108
124
24
40
56
72
88
104
120
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS13
TS14
TS15
TS16
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
(MSB)
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
Register Name:
Register Description:
Register Address:
(MSB)
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
TS1 to TS16
Transmit Signaling Registers (T1 Mode, ESF Format)
50h to 5Bh
CH2-C
CH4-C
CH6-C
CH8-C
CH10-C
CH12-C
CH14-C
CH16-C
CH18-C
CH20-C
CH22-C
CH24-C
CH2-D
CH4-D
CH6-D
CH8-D
CH10-D
CH12-D
CH14-D
CH16-D
CH18-D
CH20-D
CH22-D
CH24-D
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
CH1-C
CH3-C
CH5-C
CH7-C
CH9-C
CH11-C
CH13-C
CH15-C
CH17-C
CH19-C
CH21-C
CH23-C
(LSB)
CH1-D
CH3-D
CH5-D
CH7-D
CH9-D
CH11-D
CH13-D
CH15-D
CH17-D
CH19-D
CH21-D
CH23-D
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
(LSB)
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS1 to TS16
Transmit Signaling Registers (T1 Mode, D4 Format)
50h to 5Bh
CH2-A
CH4-A
CH6-A
CH8-A
CH10-A
CH12-A
CH14-A
CH16-A
CH18-A
CH20-A
CH22-A
CH24-A
CH2-B
CH4-B
CH6-B
CH8-B
CH10-B
CH12-B
CH14-B
CH16-B
CH18-B
CH20-B
CH22-B
CH24-B
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
CH1-B
CH3-B
CH5-B
CH7-B
CH9-B
CH11-B
CH13-B
CH15-B
CH17-B
CH19-B
CH21-B
CH23-B
CH1-A
CH3-A
CH5-A
CH7-A
CH9-A
CH11-A
CH13-A
CH15-A
CH17-A
CH19-A
CH21-A
CH23-A
Note: In D4 format, TS1–TS12 contain signaling data for two frames. Bold type indicates data for second frame.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode
In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling
registers along with the signaling data.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH7
0
SSIE1
Software Signaling Insertion Enable 1
08h
6
CH6
0
5
CH5
0
4
CH4
0
3
CH3
0
2
CH2
0
1
CH1
0
0
UCAW
0
Bit 0/Upper CAS Align/Alarm Word (UCAW). Selects the upper CAS align/alarm pattern (0000) to be sourced from the
upper 4 bits of the TS1 register.
0 = do not source the upper CAS align/alarm pattern from the TS1 register
1 = source the upper CAS align/alarm pattern from the TS1 register
Bits 1 to 7/Software Signaling Insertion Enable for Channels 1 to 7 (CH1 to CH7). These bits determine which channels
are to have signaling inserted form the Transmit Signaling registers.
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH15
0
SSIE2
Software Signaling Insertion Enable 2
09h
6
CH14
0
5
CH13
0
4
CH12
0
3
CH11
0
2
CH10
0
1
CH9
0
0
CH8
0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 8 to 15 (CH8 to CH15). These bits determine which channels
are to have signaling inserted form the transmit signaling registers.
0 = do not source signaling data from the TS registers for this channel
1 = source signaling data from the TS registers for this channel
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH22
0
SSIE3
Software Signaling Insertion Enable 3
0Ah
6
CH21
0
5
CH20
0
4
CH19
0
3
CH18
0
2
CH17
0
1
CH16
0
0
LCAW
0
Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced from the lower
4 bits of the TS1 register.
0 = do not source the lower CAS align/alarm bits from the TS1 register
1 = source the lower CAS alarm align/bits from the TS1 register
Bits 1 to 7/Software Signaling Insertion Enable for LCAW and Channels 16 to 22 (CH16 to CH22). These bits determine
which channels are to have signaling inserted form the Transmit Signaling registers.
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH30
0
SSIE4
Software Signaling Insertion Enable 4
0Bh
6
CH29
0
5
CH28
0
4
CH27
0
3
CH26
0
2
CH25
0
1
CH24
0
0
CH23
0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 23 to 30 (CH23 to CH30). These bits determine which
channels are to have signaling inserted form the transmit signaling registers.
0 = do not source signaling data from the TS registers for this channel
1 = source signaling data from the TS registers for this channel
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.2.3 Software Signaling Insertion Enable Registers, T1 Mode
In T1 mode, only registers SSIE1 through SSIE3 are used since there are only 24 channels in a T1 frame.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH8
0
SSIE1
Software Signaling Insertion Enable 1
08h
6
CH7
0
5
CH6
0
4
CH5
0
3
CH4
0
2
CH3
0
1
CH2
0
0
CH1
0
Bits 0 to 7/Software Signaling Insertion Enable for and Channels 1 to 8 (CH1 to CH8). These bits determine what
channels are to have signaling inserted form the transmit signaling registers.
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH16
0
SSIE2
Software Signaling Insertion Enable 2
09h
6
CH15
0
5
CH14
0
4
CH13
0
3
CH12
0
2
CH11
0
1
CH10
0
0
CH9
0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 9 to 16 (CH9 to CH16). These bits determine what channels
are to have signaling inserted form the transmit signaling registers.
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH24
0
SSIE3
Software Signaling Insertion Enable 3
0Ah
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
0
CH17
0
Bits 0 to 7/Software Signaling Insertion Enable for and Channels 17 to 24 (CH17 to CH24). These bits determine what
channels are to have signaling inserted form the transmit signaling registers.
0 = do not source signaling data from the TSx registers for this channel
1 = source signaling data from the TSx registers for this channel
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.2.4 Hardware-Based Transmit Signaling
In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered
and inserted to the data stream being input at the TSER pin.
Signaling data can be input on a per-channel basis via the transmit-hardware signaling-channel select
(THSCS) function. The framer can be set up to take the signaling data presented at the TSIG pin and
insert the signaling data into the PCM data stream that is being input at the TSER pin. The user has the
ability to control what channels are to have signaling data from the TSIG pin inserted into them on a perchannel basis. See the Special Per-Channel Operation section. The signaling insertion capabilities of the
framer are available whether the transmit-side elastic store is enabled or disabled. If the elastic store is
enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
18. PER-CHANNEL IDLE CODE GENERATION
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive
directions. When operated in the T1 mode, only the first 24 channels are used; the remaining channels,
CH25–CH32 are not used.
The DS21455/DS21458 contain a 64-byte idle code array accessed by the idle array address register
(IAAR) and the per-channel idle code register (PCICR). The contents of the array contain the idle codes
to be substituted into the appropriate transmit or receive channels. This substitution can be enabled and
disabled on a per-channel basis by the transmit-channel idle-code enable registers (TCICE1–4) and
receive-channel idle-code enable registers (RCICE1–4).
To program idle codes, first select a channel by writing to the IAAR register. Then write the idle code to
the PCICR register.
Bits 6 and 7 (GTIC, GRIC) of the IAAR register can be used to block write a common idle code to all
transmit or receive positions in the array with a single write to the PCICR register. The user can use the
block write feature to set a common idle code for all transmit and receive channels in the IAAR by setting
both GTIC and GRIC = 1. When a block write is enabled by GTIC or GRIC, the value placed in the
PCICR register will be written to all addresses in the transmit or receive idle array and to whatever
address is in the lower 6 bits of the IAAR register. Therefore, when enabling only one of the block
functions, GTIC or GRIC, the user must set the lower 6 bits of the IAAR register to any address in that
block. Bits 6 and 7 of the IAAR register must be set = 0 for read operations.
The TCICE1–4 and RCICE1–4 are used to enable idle-code replacement on a per-channel basis.
Table 18-1. IDLE CODE ARRAY ADDRESS MAPPING
BITS 0–5 OF IAAR REGISTER
0
1
2
MAPS TO CHANNEL
Transmit Channel 1
Transmit Channel 2
Transmit Channel 3
…
…
30
31
32
33
34
Transmit Channel 31
Transmit Channel 32
Receive Channel 1
Receive Channel 2
Receive Channel 3
…
…
62
63
Receive Channel 31
Receive Channel 32
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
18.1 Idle Code Programming Examples
The following example sets transmit channel 3 idle code to 7Eh:
Write IAAR = 02h
Write PCICR = 7Eh
;select channel 3 in the array
;set idle code to 7Eh
The following example sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of
idle codes for those channels:
Write IAAR = 02h
Write PCICR = 7Eh
Write PCICR = 7Eh
Write PCICR = 7Eh
Write PCICR = 7Eh
Write TCICE1 = 3Ch
;select channel 3 in the array
;set channel 3 idle code to 7Eh
;set channel 4 idle code to 7Eh
;set channel 5 idle code to 7Eh
;set channel 6 idle code to 7Eh
;enable transmission of idle codes for channels 3, 4, 5, and 6
The following example sets transmit channels 3, 4, 5, and 6 idle code to 7Eh, EEh, FFh, and 7Eh
respectively:
Write IAAR = 02h
Write PCICR = 7Eh
Write PCICR = EEh
Write PCICR = FFh
Write PCICR = 7Eh
The following example sets all transmit idle codes to 7Eh:
Write IAAR = 40h
Write PCICR = 7Eh
The following example sets all receive and transmit idle codes to 7Eh and enables idle code substitution
in all E1 transmit and receive channels:
Write IAAR = C0h
Write PCICR = 7Eh
Write TCICE1 = FEh
Write TCICE2 = FFh
Write TCICE3 = FEh
Write TCICE4 = FFh
Write RCICE1 = FEh
Write RCICE2 = FFh
Write RCICE3 = FEh
Write RCICE4 = FFh
;enable block write to all transmit and receive positions in the array
;7Eh is idle code
;enable idle code substitution for transmit channels 2 through 8
;Although an idle code was programmed for channel 1 by the block write ;function above,
enabling it for channel 1 would step on the frame ;alignment, alarms, and Sa bits
;enable idle code substitution for transmit channels 9 through 16
;enable idle code substitution for transmit channels 18 through 24
;Although an idle code was programmed for channel 17 by the block write ;function above,
enabling it for channel 17 would step on the CAS frame ;alignment, and signaling information
;enable idle code substitution for transmit channels 25 through 32
;enable idle code substitution for receive channels 2 through 8
;enable idle code substitution for receive channels 9 through 16
;enable idle code substitution for receive channels 18 through 24
;enable idle code substitution for receive channels 25 through 32
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
GRIC
0
IAAR
Idle Array Address Register
7Eh
6
GTIC
0
5
IAA5
0
4
IAA4
0
3
IAA3
0
2
IAA2
0
1
IAA1
0
0
IAA0
0
Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). IAA0 is the LSB of the 5-bit Channel Code.
Bit 6/Global Transmit Idle Code (GTIC). Setting this bit will cause all transmit idle codes to be set to the value written to
the PCICR register. When using this bit, the user must place any transmit address in the IAA0 through IAA5 bits (00h–1Fh).
This bit must be set = 0 for read operations.
Bit 7/Global Receive Idle Code (GRIC). Setting this bit will cause all receive idle codes to be set to the value written to the
PCICR register. When using this bit, the user must place any receive address in the IAA0 through IAA5 bits (20h–3Fh). This
bit must be set = 0 for read operations.
Register Name:
Register Description:
Register Address:
PCICR
Per-Channel Idle Code Register
7Fh
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bits 0 to 7/Per-Channel Idle Code Bits (C0 to C7). C0 is the LSB of the code (this bit is transmitted last).
The TCICE1/2/3/4 are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the
T1 or E1 line should be overwritten with the code placed in the per-channel code array.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH8
0
TCICE1
Transmit Channel Idle Code Enable Register 1
80h
6
CH7
0
5
CH6
0
4
CH5
0
3
CH4
0
2
CH3
0
1
CH2
0
0
CH1
0
1
CH10
0
0
CH9
0
Bits 0 to 7/Transmit Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8).
0 = do not insert data from the idle code array into the transmit data stream
1 = insert data from the idle code array into the transmit data stream
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH16
0
TCICE2
Transmit Channel Idle Code Enable Register 2
81h
6
CH15
0
5
CH14
0
4
CH13
0
3
CH12
0
2
CH11
0
Bits 0 to 7/Transmit Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16).
0 = do not insert data from the idle code array into the transmit data stream
1 = insert data from the idle code array into the transmit data stream
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH24
0
TCICE3
Transmit Channel Idle Code Enable Register 3
82h
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
0
CH17
0
Bits 0 to 7/Transmit Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).
0 = do not insert data from the idle code array into the transmit data stream
1 = insert data from the idle code array into the transmit data stream
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH32
0
TCICE4
Transmit Channel Idle Code Enable Register 4
83h
6
CH31
0
5
CH30
0
4
CH29
0
3
CH28
0
2
CH27
0
1
CH26
0
0
CH25
0
Bits 0 to 7/Transmit Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32).
0 = do not insert data from the idle code array into the transmit data stream
1 = insert data from the idle code array into the transmit data stream
The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the 24 T1
or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in
the per-channel code array.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH8
0
RCICE1
Receive Channel Idle Code Enable Register 1
84h
6
CH7
0
5
CH6
0
4
CH5
0
3
CH4
0
2
CH3
0
1
CH2
0
0
CH1
0
1
CH10
0
0
CH9
0
Bits 0 to 7/Receive Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8).
0 = do not insert data from the idle code array into the receive data stream
1 = insert data from the idle code array into the receive data stream
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH16
0
RCICE2
Receive Channel Idle Code Enable Register 2
85h
6
CH15
0
5
CH14
0
4
CH13
0
3
CH12
0
2
CH11
0
Bits 0 to 7/Receive Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16).
0 = do not insert data from the idle code array into the receive data stream
1 = insert data from the idle code array into the receive data stream
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH24
0
RCICE3
Receive Channel Idle Code Enable Register 3
86h
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
0
CH17
0
Bits 0 to 7/Receive Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).
0 = do not insert data from the idle code array into the receive data stream
1 = insert data from the idle code array into the receive data stream
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH32
0
RCICE4
Receive Channel Idle Code Enable Register 4
87h
6
CH31
0
5
CH30
0
4
CH29
0
3
CH28
0
2
CH27
0
1
CH26
0
Bits 0 to 7/Receive Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32).
0 = do not insert data from the idle code array into the receive data stream
1 = insert data from the idle code array into the receive data stream
112 of 270
0
CH25
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
19. CHANNEL BLOCKING REGISTERS
The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel
blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced high or
low during individual channels. These outputs can be used to block clocks to a USART or LAPD
controller in ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and
TCHBLK pin will be held high during the entire corresponding channel time. Channels 25 through 32 are
ignored when the device is operated in the T1 mode.
Also, the DS21455/DS21458 can internally generate and output a bursty clock on a per-channel basis (N
x 64kbps / 56kbps). See the Fractional T1/E1 Support section.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH8
0
RCBR1
Receive Channel Blocking Register 1
88h
6
CH7
0
5
CH6
0
4
CH5
0
3
CH4
0
2
CH3
0
1
CH2
0
0
CH1
0
1
CH10
0
0
CH9
0
Bits 0 to 7/Receive Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8).
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH16
0
RCBR2
Receive Channel Blocking Register 2
89h
6
CH15
0
5
CH14
0
4
CH13
0
3
CH12
0
2
CH11
0
Bits 0 to 7/Receive Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16).
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
113 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH24
0
RCBR3
Receive Channel Blocking Register 3
8Ah
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
0
CH17
0
Bits 0 to 7/Receive Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24).
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH32
0
RCBR4
Receive Channel Blocking Register 4
8Bh
6
CH31
0
5
CH30
0
4
CH29
0
3
CH28
0
2
CH27
0
1
CH26
0
0
CH25
0
Bits 0 to 7/Receive Channels 25 to 32 Channel Blocking Control Bits (CH25 to CH32).
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH8
0
TCBR1
Transmit Channel Blocking Register 1
8Ch
6
CH7
0
5
CH6
0
4
CH5
0
3
CH4
0
2
CH3
0
1
CH2
0
0
CH1
0
Bits 0 to 7/Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8).
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH16
0
TCBR2
Transmit Channel Blocking Register 2
8Dh
6
CH15
0
5
CH14
0
4
CH13
0
3
CH12
0
2
CH11
0
1
CH10
0
Bits 0 to 7/Transmit Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16).
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
114 of 270
0
CH9
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH24
0
TCBR3
Transmit Channel Blocking Register 3
8Eh
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
0
CH17
0
Bits 0 to 7/Transmit Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24).
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CH32
0
TCBR4
Transmit Channel Blocking Register 4
8Fh
6
CH31
0
5
CH30
0
4
CH29
0
3
CH28
0
2
CH27
0
1
CH26
0
Bits 0 to 7/Transmit Channels 25 to 32 Channel Blocking Control Bits (CH25 to CH32).
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
115 of 270
0
CH25
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
20. ELASTIC STORES OPERATION
The DS21455/DS21458 contain dual two-frame, fully independent elastic stores, one for the receive
direction and one for the transmit direction. The transmit- and receive-side elastic stores can be
enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or
2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate to which
the other elastic store is interfacing.
The elastic stores have two main purposes. First, they can be used for rate conversion. When the device is
in the T1 mode, the elastic stores can rate-convert the T1 data stream to a 2.048MHz backplane. In E1
mode, the elastic store can rate-convert the E1 data stream to a 1.544MHz backplane. Second, they can be
used to absorb the differences in frequency and phase between the T1 or E1 data stream and an
asynchronous (not locked) backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the
elastic stores will manage the rate difference and perform controlled slips, deleting or repeating frames of
data in order to manage the difference between the network and the backplane.
The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. See the
Interleaved PCM Bus Operation section.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
ESCR
Elastic Store Control Register
4Fh
Bit #
Name
Default
6
TESR
0
7
TESALGN
0
5
TESMDM
0
4
TESE
0
3
RESALGN
0
2
RESR
0
1
RESMDM
0
0
RESE
0
Bit 0/Receive Elastic Store Enable (RESE).
0 = elastic store is bypassed
1 = elastic store is enabled
Bit 1/Receive Elastic Store Minimum Delay Mode (RESMDM). See the Minimum Delay Mode section for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32-bit depth
Bit 2/Receive Elastic Store Reset (RESR). Setting this bit from a zero to a one forces the read and write pointers into
opposite frames, maximizing the delay through the receive elastic store. Should be toggled after RSYSCLK has been applied
and is stable. See the Elastic Stores Initialization section for details. Do not leave this bit set HIGH.
Bit 3/Receive Elastic Store Align (RESALGN). Setting this bit from a zero to a one will force the receive elastic store’s
write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater
or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be
disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent
align. See the Elastic Stores Initialization section for details.
Bit 4/Transmit Elastic Store Enable (TESE).
0 = elastic store is bypassed
1 = elastic store is enabled
Bit 5/Transmit Elastic Store Minimum Delay Mode (TESMDM). See the Minimum Delay Mode section for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32-bit depth
Bit 6/Transmit Elastic Store Reset (TESR). Setting this bit from a zero to a one forces the read and write pointers into
opposite frames, maximizing the delay through the transmit elastic store. Transmit data is lost during the reset. Should be
toggled after TSYSCLK has been applied and is stable. See the Elastic Stores Initialization section for details. Do not leave
this bit set HIGH.
Bit 7/Transmit Elastic Store Align (TESALGN). Setting this bit from a zero to a one will force the transmit elastic store’s
write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater
or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be
disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent
align. See the Elastic Stores Initialization section for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
SR5
Status Register 5
1Eh
Bit #
Name
Default
6
—
0
7
—
0
5
TESF
0
4
TESEM
0
3
TSLIP
0
2
RESF
0
1
RESEM
0
0
RSLIP
0
Bit 0/Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted
a frame.
Bit 1/Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is
repeated.
Bit 2/Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is deleted.
Bit 3/Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either repeated or
deleted a frame.
Bit 4/Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is
repeated.
Bit 5/Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted.
Register Name:
Register Description:
Register Address:
IMR5
Interrupt Mask Register 5
1Fh
Bit #
Name
Default
6
—
0
7
—
0
5
TESF
0
4
TESEM
0
3
TSLIP
0
Bit 0/Receive Elastic Store Slip Occurrence Event (RSLIP).
0 = interrupt masked
1 = interrupt enabled
Bit 1/Receive Elastic Store Empty Event (RESEM).
0 = interrupt masked
1 = interrupt enabled
Bit 2/Receive Elastic Store Full Event (RESF).
0 = interrupt masked
1 = interrupt enabled
Bit 3/Transmit Elastic Store Slip Occurrence Event (TSLIP).
0 = interrupt masked
1 = interrupt enabled
Bit 4/Transmit Elastic Store Empty Event (TESEM).
0 = interrupt masked
1 = interrupt enabled
Bit 5/Transmit Elastic Store Full Event (TESF).
0 = interrupt masked
1 = interrupt enabled
118 of 270
2
RESF
0
1
RESEM
0
0
RSLIP
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
20.1 Receive Side
See the IOCR1 and IOCR2 registers for information on clock and I/O configurations.
If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz
clock at the RSYSCLK pin. For higher rate system-clock applications, see the Interleaved PCM Bus
Operation section. The user has the option of either providing a frame/multiframe sync at the RSYNC pin
or having the RSYNC pin provide a pulse on frame/multiframe boundaries. If signaling reinsertion is
enabled, signaling data in TS16 is realigned to the multiframe-sync input on RSYNC. Otherwise, a
multiframe-sync input on RSYNC is treated as a simple frame boundary by the elastic store. The framer
will always indicate frame boundaries on the network side of the elastic store via the RFSYNC output
whether the elastic store is enabled or not. Multiframe boundaries will always be indicated via the
RMSYNC output. If the elastic store is enabled, then RMSYNC will output the multiframe boundary on
the backplane side of the elastic store.
20.1.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the data output at RSER will be
forced to all ones every fourth channel and the F-bit will be passed into the MSB of TS0. Hence, channels
1 (bits 1–7), 5, 9, 13, 17, 21, 25, and 29 (time slots 0 (bits 1–7), 4, 8, 12, 16, 20, 24, and 28) will be forced
to a one. Also, in 2.048MHz applications, the RCHBLK output will be forced high during the same
channels as the RSER pin. This is useful in T1 to E1 conversion applications. If the two-frame elastic
buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data
will be repeated at RSER and the SR5.0 and SR5.1 bits will be set to a one. If the buffer fills, then a full
frame of data will be deleted and the SR5.0 and SR5.2 bits will be set to a one.
20.1.2 E1 Mode
If the elastic store is enabled, then either CAS or CRC-4 multiframe boundaries will be indicated via the
RMSYNC output. If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth
channel of the received E1 data will be deleted and a F-bit position (which will be forced to one) will be
inserted. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will be
deleted from the received E1 data stream. Also, in 1.544MHz applications, the RCHBLK output will not
be active in channels 25 through 32 (or in other words, RCBR4 is not active). If the two-frame elastic
buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data
will be repeated at RSER and the SR5.0 and SR5.1 bits will be set to a one. If the buffer fills, then a full
frame of data will be deleted and the SR5.0 and SR5.2 bits will be set to a one.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
20.2 Transmit Side
See the IOCR1 and IOCR2 registers for information on clock and I/O configurations.
The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic
store is enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher-rate
system clock applications, see the Interleaved PCM Bus Operation section. Controlled slips in the
transmit elastic store are reported in the SR5.3 bit and the direction of the slip is reported in the SR5.4
and SR5.5 bits.
20.2.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER will be
ignored every fourth channel. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16,
20, 24, and 28) will be ignored. The user can supply frame or multiframe sync pulse to the TSSYNC
input. Also, in 2.048MHz applications, the TCHBLK output will be forced high during the channels
ignored by the framer.
20.2.2 E1 Mode
A 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a framesync pulse or a multiframe-sync pulse to the TSSYNC input.
20.3 Elastic Stores Initialization
There are two elastic-store initializations that can be used to improve performance in certain applications:
elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read
and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are
locked to RCLK/TCLK, respectively). See Table 20-1 for details.
Table 20-1. ELASTIC STORE DELAY AFTER INITIALIZATION
INITIALIZATION
Receive Elastic Store Reset
Transmit Elastic Store Reset
Receive Elastic Store Align
Transmit Elastic Store Align
REGISTER BIT
ESCR.2
ESCR.6
ESCR.3
ESCR.7
DELAY
8 Clocks < Delay < 1 Frame
1 Frame < Delay < 2 Frames
½ Frame < Delay < 1 ½ Frames
½ Frame < Delay < 1 ½ Frames
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
20.4 Minimum-Delay Mode
When minimum delay mode is enabled the elastic stores will be forced to a maximum depth of 32 bits
instead of the normal two-frame depth. ESCR.5 and ESCR.1 enable the transmit and receive elastic store
minimum-delay modes. This feature is useful primarily in applications that interface T1 to a 2.048MHz
bus without adding the latency that would be associated with using the elastic store in full buffer mode.
Certain restrictions apply when minimum delay mode is used. Minimum-delay mode can only be
used when the elastic store’s system clock is locked to its network clock (e.g., RCLK locked to
RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RSYNC must be
configured as an output. In E1 operation TSYNC must be configured as an input when transmit
minimum delay mode is enabled. In T1 operation TSYNC can be configured as an input or output when
transmit minimum delay mode is enabled. In a typical application RSYSCLK and TSYSCLK are locked
to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All of the slip
contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK
and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits
(ESCR.2 and ESCR.6) should be toggled from a zero to a one to ensure proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
21. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)
The DS21455/DS21458 can implement the G.706 CRC-4 recalculation at intermediate path points. When
this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC
multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit
positions; this change in data content will be used to modify the CRC-4 checksum. The modification,
however, will not corrupt any error information the original CRC-4 checksum might contain. In this mode
of operation, TSYNC must be configured to multiframe mode. The data at TSER must be aligned to the
TSYNC signal. If TSYNC is an input then the user must assert TSYNC aligned at the beginning of the
multiframe relative to TSER. If TSYNC is an output, the user must multiframe-align the data presented to
TSER.
Figure 21-1. CRC-4 Recalculate Method
TPOSO/TNEGO
INSERT
NEW CRC-4
CODE
EXTRACT
OLD CRC-4
CODE
TSER
+
CRC-4
CALCULATOR
XOR
MODIFY
Sa BIT
POSITIONS
NEW Sa BIT
DATA
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
22. T1 BIT ORIENTED CODE (BOC) CONTROLLER
The DS21455/DS21458 contain a BOC generator on the transmit side and a BOC detector on the receive
side. The BOC function is available only in T1 mode.
22.1 Transmit BOC
Bits 0 through 5 in the TFDL register contain the BOC message to be transmitted. Setting BOCC.0 = 1
causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit
position. The transmit BOC controller automatically provides the abort sequence. BOC messages will be
transmitted as long as BOCC.0 is set.
To transmit a BOC, use the following:
1) Write 6-bit code into the TFDL register.
2) Set SBOC bit in BOCC register = 1.
22.2 Receive BOC
The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register will now operate as the
receive BOC message and information register. The lower six bits of the RFDL register (BOC message
bits) are preset to all ones. When the BOC bits change state, the BOC change of state indicator, SR8.0
will alert the host. The host will then read the RFDL register to get the BOC message. A change of state
will occur when either a new BOC code has been present for time determined by the receive BOC filter
bits, RBF0 and RBF1, in the BOCC register.
To receive a BOC, use the following:
1)
2)
3)
4)
5)
6)
Set integration time via BOCC.1 and BOCC.2.
Enable the receive BOC function (BOCC.4 = 1).
Enable interrupt (IMR8.0 = 1).
Wait for interrupt to occur.
Read the RFDL register.
The lower six bits of the RFDL register is the message.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
BOCC
BOC Control Register
37h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
RBOCE
0
3
RBR
0
2
RBF1
0
1
RBF0
0
0
SBOC
0
Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register.
Bits 1 to 2/Receive BOC Filter Bits (RBF0, RBF1). The BOC filter sets the number of consecutive patterns that must be
received without error prior to an indication of a valid message.
RBF1
RBF0
0
0
1
1
0
1
0
1
CONSECUTIVE BOC CODES FOR VALID SEQUENCE
IDENTIFICATION
None
3
5
7
Bit 3/Receive BOC Reset (RBR). A 0 to 1 transition will reset the BOC circuitry. Must be cleared and set again for a
subsequent reset.
Bit 4/Receive BOC Enable (RBOCE). Enables the receive BOC function. The RFDL register will report the received BOC
code.
0 = receive BOC function disabled
1 = receive BOC function enabled. The RFDL register will report BOC messages
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
RFDL (RFDL register bit usage when BOCC.4 = 1)
Receive FDL Register
C0h
Bit #
Name
Default
6
—
0
7
—
0
5
RBOC5
0
4
RBOC4
0
3
RBOC3
0
2
RBOC2
0
1
RBOC1
0
0
RBOC0
0
3
RFDLF
0
2
TFDLE
0
1
RMTCH
0
0
RBOC
0
Bit 0/BOC Bit 0 (RBOC0).
Bit 1/BOC Bit 1 (RBOC1).
Bit 2/BOC Bit 2 (RBOC2).
Bit 3/BOC Bit 3 (RBOC3).
Bit 4/BOC Bit 4 (RBOC4).
Bit 5/BOC Bit 5 (RBOC5).
Bit 6/This bit position is unused when BOCC.4 = 1.
Bit 7/This bit position is unused when BOCC.4 = 1.
Register Name:
Register Description:
Register Address:
SR8
Status Register 8
24h
Bit #
Name
Default
6
—
0
7
—
0
5
BOCC
0
4
RFDLAD
0
Bit 0/Receive BOC Detector Change of State Event (RBOC). Set whenever the BOC detector sees a change of state to a
valid BOC. The setting of this bit prompts the user to read the RFDL register.
Bit 1/Receive FDL Match Event (RMTCH). Set whenever the contents of the RFDL register matches RFDLM1 or
RFDLM2.
Bit 2/TFDL Register Empty Event(TFDLE). Set when the transmit FDL buffer (TFDL) empties.
Bit 3/RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (RFDL) fills to capacity.
Bit 4/RFDL Abort Detect Event (RFDLAD). Set when eight consecutive ones are received on the FDL.
Bit 5/BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
IMR8
Interrupt Mask Register 8
25h
Bit #
Name
Default
6
—
0
7
—
0
5
BOCC
0
4
RFDLAD
0
3
RFDLF
0
Bit 0/Receive BOC Detector Change of State Event (RBOC).
0 = interrupt masked
1 = interrupt enabled
Bit 1/Receive FDL Match Event (RMTCH).
0 = interrupt masked
1 = interrupt enabled
Bit 2/TFDL Register Empty Event (TFDLE).
0 = interrupt masked
1 = interrupt enabled
Bit 3/RFDL Register Full Event (RFDLF).
0 = interrupt masked
1 = interrupt enabled
Bit 4/RFDL Abort Detect Event (RFDLAD).
0 = interrupt masked
1 = interrupt enabled
Bit 5/BOC Clear Event (BOCC).
0 = interrupt masked
1 = interrupt enabled
126 of 270
2
TFDLE
0
1
RMTCH
0
0
RBOC
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY)
The DS21455/DS21458, when operated in the E1 mode, provide for access to both the Sa and the Si bits
via three different methods. The first method is via a hardware scheme using the RLINK/RLCLK and
TLINK/TLCLK pins. The second method involves using the internal RAF/RNAF and TAF/TNAF
registers. The third method involves an expanded version of the second method.
23.1 Hardware Scheme (Method 1)
On the receive side, all of the received data is reported at the RLINK pin. Using the E1RCR2 register the
user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create
a clock that can be used to capture the needed Sa bits. If RSYNC is programmed to output a frame
boundary, it will identify the Si bits.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register or
externally from the TLINK pin. Using the E1TCR2 register the framer can be programmed to source any
combination of the Sa bits from the TLINK pin. Si bits can be sampled through the TSER pin if by setting
E1TCR1.4 = 0.
23.2 Internal Register Scheme Based On Double-Frame (Method 2)
On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and
Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the
receive align frame bit in status register 4 (SR4.0) will indicate that the contents of the RAF and RNAF
have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers.
The host has 250ms to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the transmit
align frame bit in status register 4 (SR4.3). The host can use the SR4.3 bit to know when to update the
TAF and TNAF registers. It has 250ms to update the data or else the old data will be retransmitted. If the
TAF an TNAF registers are only being used to source the align frame and nonalign frame-sync
patterns, then the host need only write once to these registers. Data in the Si bit position will be
overwritten if the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC-4
mode, or (3) with automatic E-bit insertion enabled. Data in the Sa bit position will be overwritten if any
of the E1TCR2.3 to E1TCR2.7 bits are set to one.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
RAF
Receive Align Frame Register
C6h
Bit #
Name
Default
6
0
0
7
Si
0
5
0
0
4
1
0
3
1
0
2
0
0
1
1
0
0
1
0
3
Sa5
0
2
Sa6
0
1
Sa7
0
0
Sa8
0
Bit 0/Frame Alignment Signal Bit (1).
Bit 1/Frame Alignment Signal Bit (1).
Bit 2/Frame Alignment Signal Bit (0).
Bit 3/Frame Alignment Signal Bit (1).
Bit 4/Frame Alignment Signal Bit (1).
Bit 5/Frame Alignment Signal Bit (0).
Bit 6/Frame Alignment Signal Bit (0).
Bit 7/International Bit (Si).
Register Name:
Register Description:
Register Address:
RNAF
Receive Nonalign Frame Register
C7h
Bit #
Name
Default
6
1
0
7
Si
0
5
A
0
4
Sa4
0
Bit 0/Additional Bit 8 (Sa8).
Bit 1/Additional Bit 7 (Sa7).
Bit 2/Additional Bit 6 (Sa6).
Bit 3/Additional Bit 5 (Sa5).
Bit 4/Additional Bit 4 (Sa4).
Bit 5 / Remote Alarm (A).
Bit 6/Frame Nonalignment Signal Bit (1).
Bit 7/International Bit (Si).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
TAF
Transmit Align Frame Register
D0h
Bit #
Name
Default
6
0
0
7
Si
0
5
0
0
4
1
1
3
1
1
2
0
0
1
1
1
0
1
1
2
Sa6
0
1
Sa7
0
0
Sa8
0
Bit 0/Frame Alignment Signal Bit (1).
Bit 1/Frame Alignment Signal Bit (1).
Bit 2/Frame Alignment Signal Bit (0).
Bit 3/Frame Alignment Signal Bit (1).
Bit 4/Frame Alignment Signal Bit (1).
Bit 5/Frame Alignment Signal Bit (0).
Bit 6/Frame Alignment Signal Bit (0).
Bit 7/International Bit (Si).
Register Name:
Register Description:
Register Address:
TNAF
Transmit Nonalign Frame Register
D1h
Bit #
Name
Default
6
1
1
7
Si
0
5
A
0
4
Sa4
0
3
Sa5
0
Bit 0/Additional Bit 8 (Sa8).
Bit 1/Additional Bit 7 (Sa7).
Bit 2/Additional Bit 6 (Sa6).
Bit 3/Additional Bit 5 (Sa5).
Bit 4/Additional Bit 4 (Sa4).
Bit 5/Remote Alarm (used to transmit the alarm A).
Bit 6/Frame Nonalignment Signal Bit (1).
Bit 7/International Bit (Si).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
23.3 Internal Register Scheme Based On CRC-4 Multiframe (Method 3)
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4
multiframe bit in status register 2 (SR4.1). The host can use the SR4.1 bit to know when to read these
registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first
received. Please see the following register descriptions for more details.
On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that via
the transmit Sa bit control register (TSaCR), can be programmed to insert both Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in status register 2 (SR4.4).
The host can use the SR4.4 bit to know when to update these registers. It has 2ms to update the data or
else the old data will be retransmitted. The MSB of each register is the first bit transmitted. See the
following register descriptions for details.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SiF0
0
RSiAF
Receive Si Bits of the Align Frame
C8h
6
SiF2
0
5
SiF4
0
4
SiF6
0
3
SiF8
0
Bit 0/Si Bit of Frame 14(SiF14).
Bit 1/Si Bit of Frame 12(SiF12).
Bit 2/Si Bit of Frame 10(SiF10).
Bit 3/Si Bit of Frame 8(SiF8).
Bit 4/Si Bit of Frame 6(SiF6).
Bit 5/Si Bit of Frame 4(SiF4).
Bit 6/Si Bit of Frame 2(SiF2).
Bit 7/Si Bit of Frame 0(SiF0).
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2
SiF10
0
1
SiF12
0
0
SiF14
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SiF1
0
RSiNAF
Receive Si Bits of the Nonalign Frame
C9h
6
SiF3
0
5
SiF5
0
4
SiF7
0
3
SiF9
0
2
SiF11
0
1
SiF13
0
0
SiF15
0
3
RRAF9
0
2
RRAF11
0
1
RRAF13
0
0
RRAF15
0
Bit 0/Si Bit of Frame 15(SiF15).
Bit 1/Si Bit of Frame 13(SiF13).
Bit 2/Si Bit of Frame 11(SiF11).
Bit 3/Si Bit of Frame 9(SiF9).
Bit 4/Si Bit of Frame 7(SiF7).
Bit 5/Si Bit of Frame 5(SiF5).
Bit 6/Si Bit of Frame 3(SiF3).
Bit 7/Si Bit of Frame 1(SiF1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RRAF1
0
RRA
Receive Remote Alarm
CAh
6
RRAF3
0
5
RRAF5
0
4
RRAF7
0
Bit 0/Remote Alarm Bit of Frame 15(RRAF15).
Bit 1/Remote Alarm Bit of Frame 13(RRAF13).
Bit 2/Remote Alarm Bit of Frame 11(RRAF11).
Bit 3/Remote Alarm Bit of Frame 9(RRAF9).
Bit 4/Remote Alarm Bit of Frame 7(RRAF7).
Bit 5/Remote Alarm Bit of Frame 5(RRAF5).
Bit 6/Remote Alarm Bit of Frame 3(RRAF3).
Bit 7/Remote Alarm Bit of Frame 1(RRAF1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa4F1
0
RSa4
Receive Sa4 Bits
CBh
6
RSa4F3
0
5
RSa4F5
0
4
RSa4F7
0
3
RSa4F9
0
2
RSa4F11
0
1
RSa4F13
0
0
RSa4F15
0
4
RSa5F7
0
3
RSa5F9
0
2
RSa5F11
0
1
RSa5F13
0
0
RSa5F15
0
Bit 0/Sa4 Bit of Frame 15(RSa4F15).
Bit 1/Sa4 Bit of Frame 13(RSa4F13).
Bit 2/Sa4 Bit of Frame 11(RSa4F11).
Bit 3/Sa4 Bit of Frame 9(RSa4F9).
Bit 4/Sa4 Bit of Frame 7(RSa4F7).
Bit 5/Sa4 Bit of Frame 5(RSa4F5).
Bit 6/Sa4 Bit of Frame 3(RSa4F3).
Bit 7/Sa4 Bit of Frame 1(RSa4F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa5F1
0
RSa5
Receive Sa5 Bits
CCh
6
RSa5F3
0
5
RSa5F5
0
Bit 0/Sa5 Bit of Frame 15(RSa5F15).
Bit 1/Sa5 Bit of Frame 13(RSa5F13).
Bit 2/Sa5 Bit of Frame 11(RSa5F11).
Bit 3/Sa5 Bit of Frame 9(RSa5F9).
Bit 4/Sa5 Bit of Frame 7(RSa5F7).
Bit 5/Sa5 Bit of Frame 5(RSa5F5).
Bit 6/Sa5 Bit of Frame 3(RSa5F3).
Bit 7/Sa5 Bit of Frame 1(RSa5F1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa6F1
0
RSa6
Receive Sa6 Bits
CDh
6
RSa6F3
0
5
RSa6F5
0
4
RSa6F7
0
3
RSa6F9
0
2
RSa6F11
0
1
RSa6F13
0
0
RSa6F15
0
4
RSa7F7
0
3
RSa7F9
0
2
RSa7F11
0
1
RSa7F13
0
0
RSa7F15
0
Bit 0/Sa6 Bit of Frame 15(RSa6F15).
Bit 1/Sa6 Bit of Frame 13(RSa6F13).
Bit 2/Sa6 Bit of Frame 11(RSa6F11).
Bit 3/Sa6 Bit of Frame 9(RSa6F9).
Bit 4/Sa6 Bit of Frame 7(RSa6F7).
Bit 5/Sa6 Bit of Frame 5(RSa6F5).
Bit 6/Sa6 Bit of Frame 3(RSa6F3).
Bit 7/Sa6 Bit of Frame 1(RSa6F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa7F1
0
RSa7
Receive Sa7 Bits
CEh
6
RSa7F3
0
5
RSa7F5
0
Bit 0/Sa7 Bit of Frame 15(RSa7F15).
Bit 1/Sa7 Bit of Frame 13(RSa7F13).
Bit 2/Sa7 Bit of Frame 11(RSa7F11).
Bit 3/Sa7 Bit of Frame 9(RSa7F9).
Bit 4/Sa7 Bit of Frame 7(RSa7F7).
Bit 5/Sa7 Bit of Frame 5(RSa7F5).
Bit 6/Sa7 Bit of Frame 3(RSa7F3).
Bit 7/Sa7 Bit of Frame 1(RSa4F1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSa8F1
0
RSa8
Receive Sa8 Bits
CFh
6
RSa8F3
0
5
RSa8F5
0
4
RSa8F7
0
3
RSa8F9
0
Bit 0/Sa8 Bit of Frame 15(RSa8F15).
Bit 1/Sa8 Bit of Frame 13(RSa8F13).
Bit 2/Sa8 Bit of Frame 11(RSa8F11).
Bit 3/Sa8 Bit of Frame 9(RSa8F9).
Bit 4/Sa8 Bit of Frame 7(RSa8F7).
Bit 5/Sa8 Bit of Frame 5(RSa8F5).
Bit 6/Sa8 Bit of Frame 3(RSa8F3).
Bit 7/Sa8 Bit of Frame 1(RSa8F1).
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2
RSa8F11
0
1
RSa8F13
0
0
RSa8F15
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TsiF0
0
TSiAF
Transmit Si Bits of the Align Frame
D2h
6
TsiF2
0
5
TsiF4
0
4
TsiF6
0
3
TsiF8
0
Bit 0/Si Bit of Frame 14(TsiF14).
Bit 1/Si Bit of Frame 12(TsiF12).
Bit 2/Si Bit of Frame 10(TsiF10).
Bit 3/Si Bit of Frame 8(TsiF8).
Bit 4/Si Bit of Frame 6(TsiF6).
Bit 5/Si Bit of Frame 4(TsiF4).
Bit 6/Si Bit of Frame 2(TsiF2).
Bit 7/Si Bit of Frame 0(TsiF0).
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2
TsiF10
0
1
TsiF12
0
0
TsiF14
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TsiF1
0
TSiNAF
Transmit Si Bits of the Nonalign Frame
D3h
6
TsiF3
0
5
TsiF5
0
4
TsiF7
0
3
TsiF9
0
2
TsiF11
0
1
TsiF13
0
0
TSiF15
0
3
TRAF9
0
2
TRAF11
0
1
TRAF13
0
0
TRAF15
0
Bit 0/Si Bit of Frame 15(TSiF15).
Bit 1/Si Bit of Frame 13(TsiF13).
Bit 2/Si Bit of Frame 11(TsiF11).
Bit 3/Si Bit of Frame 9(TsiF9).
Bit 4/Si Bit of Frame 7(TsiF7).
Bit 5/Si Bit of Frame 5(TsiF5).
Bit 6/Si Bit of Frame 3(TsiF3).
Bit 7/Si Bit of Frame 1(TsiF1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TRAF1
0
TRA
Transmit Remote Alarm
D4h
6
TRAF3
0
5
TRAF5
0
4
TRAF7
0
Bit 0/Remote Alarm Bit of Frame 15(TRAF15).
Bit 1/Remote Alarm Bit of Frame 13(TRAF13).
Bit 2/Remote Alarm Bit of Frame 11(TRAF11).
Bit 3/Remote Alarm Bit of Frame 9(TRAF9).
Bit 4/Remote Alarm Bit of Frame 7(TRAF7).
Bit 5/Remote Alarm Bit of Frame 5(TRAF5).
Bit 6/Remote Alarm Bit of Frame 3(TRAF3).
Bit 7/Remote Alarm Bit of Frame 1(TRAF1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa4F1
0
TSa4
Transmit Sa4 Bits
D5h
6
TSa4F3
0
5
TSa4F5
0
4
TSa4F7
0
3
TSa4F9
0
2
TSa4F11
0
1
TSa4F13
0
0
TSa4F15
0
4
TSa5F7
0
3
TSa5F9
0
2
TSa5F11
0
1
TSa5F13
0
0
TSa5F15
0
Bit 0/Sa4 Bit of Frame 15(TSa4F15).
Bit 1/Sa4 Bit of Frame 13(TSa4F13).
Bit 2/Sa4 Bit of Frame 11(TSa4F11).
Bit 3/Sa4 Bit of Frame 9(TSa4F9).
Bit 4/Sa4 Bit of Frame 7(TSa4F7).
Bit 5/Sa4 Bit of Frame 5(TSa4F5).
Bit 6/Sa4 Bit of Frame 3(TSa4F3).
Bit 7/Sa4 Bit of Frame 1(TSa4F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa5F1
0
TSa5
Transmit Sa5 Bits
D6h
6
TSa5F3
0
5
TSa5F5
0
Bit 0/Sa5 Bit of Frame 15(TSa5F15).
Bit 1/Sa5 Bit of Frame 13(TSa5F13).
Bit 2/Sa5 Bit of Frame 11(TSa5F11).
Bit 3/Sa5 Bit of Frame 9(TSa5F9).
Bit 4/Sa5 Bit of Frame 7(TSa5F7).
Bit 5/Sa5 Bit of Frame 5(TSa5F5).
Bit 6/Sa5 Bit of Frame 3(TSa5F3).
Bit 7/Sa5 Bit of Frame 1(TSa5F1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa6F1
0
TSa6
Transmit Sa6 Bits
D7h
6
TSa6F3
0
5
TSa6F5
0
4
TSa6F7
0
3
TSa6F9
0
2
TSa6F11
0
1
TSa6F13
0
0
TSa6F15
0
4
TSa7F7
0
3
TSa7F9
0
2
TSa7F11
0
1
TSa7F13
0
0
TSa7F15
0
Bit 0/Sa6 Bit of Frame 15(TSa6F15).
Bit 1/Sa6 Bit of Frame 13(TSa6F13).
Bit 2/Sa6 Bit of Frame 11(TSa6F11).
Bit 3/Sa6 Bit of Frame 9(TSa6F9).
Bit 4/Sa6 Bit of Frame 7(TSa6F7).
Bit 5/Sa6 Bit of Frame 5(TSa6F5).
Bit 6/Sa6 Bit of Frame 3(TSa6F3).
Bit 7/Sa6 Bit of Frame 1(TSa6F1).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa7F1
0
TSa7
Transmit Sa7 Bits
D8h
6
TSa7F3
0
5
TSa7F5
0
Bit 0/Sa7 Bit of Frame 15(TSa7F15).
Bit 1/Sa7 Bit of Frame 13(TSa7F13).
Bit 2/Sa7 Bit of Frame 11(TSa7F11).
Bit 3/Sa7 Bit of Frame 9(TSa7F9).
Bit 4/Sa7 Bit of Frame 7(TSa7F7).
Bit 5/Sa7 Bit of Frame 5(TSa7F5).
Bit 6/Sa7 Bit of Frame 3(TSa7F3).
Bit 7/Sa7 Bit of Frame 1(TSa4F1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TSa8F1
0
TSa8
Transmit Sa8 Bits
D9h
6
TSa8F3
0
5
TSa8F5
0
4
TSa8F7
0
3
TSa8F9
0
Bit 0/Sa8 Bit of Frame 15(TSa8F15).
Bit 1/Sa8 Bit of Frame 13(TSa8F13).
Bit 2/Sa8 Bit of Frame 11(TSa8F11).
Bit 3/Sa8 Bit of Frame 9(TSa8F9).
Bit 4/Sa8 Bit of Frame 7(TSa8F7).
Bit 5/Sa8 Bit of Frame 5(TSa8F5).
Bit 6/Sa8 Bit of Frame 3(TSa8F3).
Bit 7/Sa8 Bit of Frame 1(TSa8F1).
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2
TSa8F11
0
1
TSa8F13
0
0
TSa8F15
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SiAF
0
TSACR
Transmit Sa Bit Control Register
DAh
6
SiNAF
0
5
RA
0
4
Sa4
0
3
Sa5
0
2
Sa6
0
Bit 0/Additional Bit 8 Insertion Control Bit (Sa8).
0 = do not insert data from the TSa8 register into the transmit data stream
1 = insert data from the TSa8 register into the transmit data stream
Bit 1/Additional Bit 7 Insertion Control Bit (Sa7).
0 = do not insert data from the TSa7 register into the transmit data stream
1 = insert data from the TSa7 register into the transmit data stream
Bit 2/Additional Bit 6 Insertion Control Bit (Sa6).
0 = do not insert data from the TSa6 register into the transmit data stream
1 = insert data from the TSa6 register into the transmit data stream
Bit 3/Additional Bit 5 Insertion Control Bit (Sa5).
0 = do not insert data from the TSa5 register into the transmit data stream
1 = insert data from the TSa5 register into the transmit data stream
Bit 4/Additional Bit 4 Insertion Control Bit (Sa4).
0 = do not insert data from the TSa4 register into the transmit data stream
1 = insert data from the TSa4 register into the transmit data stream
Bit 5/Remote Alarm Insertion Control Bit (RA).
0 = do not insert data from the TRA register into the transmit data stream
1 = insert data from the TRA register into the transmit data stream
Bit 6/International Bit in Nonalign Frame Insertion Control Bit (SiNAF).
0 = do not insert data from the TSiNAF register into the transmit data stream
1 = insert data from the TSiNAF register into the transmit data stream
Bit 7/International Bit in Align Frame Insertion Control Bit (SiAF).
0 = do not insert data from the TSiAF register into the transmit data stream
1 = insert data from the TSiAF register into the transmit data stream
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1
Sa7
0
0
Sa8
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
24. HDLC CONTROLLERS
This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is
configurable for use with time slots, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). Each HDLC
controller has 128 byte buffers in both the transmit and receive paths. When used with time slots, the user
can select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits
within the time slot(s) to assign to the HDLC controllers. HxRC.3 (HDLCD) is used to disable the HDLC
controllers. Disabling the HDLC controllers when unused will reduce the power consumption by the
device. Although this bit is in the receive HDLC control register, it disables both the transmit and receive
function.
The user must take care to not map both transmit HDLC controllers to the same Sa bits, time slots or, in
T1 mode, map both controllers to the FDL. HDLC #1 and HDLC #2 are identical in operation and
therefore the following operational description refers only to a singular controller.
The HDLC controller performs all the necessary overhead for generating and receiving Performance
Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream.
The 128-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or
transmitted without host intervention.
24.1 Basic Operation Details
To allow the framer to properly source/receive data from/to the HDLC controllers, the legacy FDL
circuitry (See the Legacy FDL Support (T1 Mode) section.) should be disabled.
The HDLC registers are divided into four groups: control/configuration, status/information, mapping, and
FIFOs. Table 24-1 lists these registers by group.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Table 24-1. HDLC CONTROLLER REGISTERS
NAME
FUNCTION
CONTROL/CONFIGURATION
H1TC, HDLC #1 Transmit Control Register
H2TC, HDLC #2 Transmit Control Register
H1RC, HDLC #1 Receive Control Register
H2RC, HDLC #2 Receive Control Register
H1FC, HDLC #1 FIFO Control Register
H2FC, HDLC #2 FIFO Control Register
General control over the transmit HDLC controllers
General control over the receive HDLC controllers
Sets high watermark for receiver and low watermark for
transmitter
STATUS/INFORMATION
SR6, HDLC #1 Status Register
SR7, HDLC #2 Status Register
IMR6, HDLC #1 Interrupt Mask Register
IMR7, HDLC #2 Interrupt Mask Register
INFO4, HDLC #1 & #2 Information Register
INFO5, HDLC #1 Information Register
INFO6, HDLC #2 Information Register
H1RPBA, HDLC #1 Receive Packet Bytes Available
Register
H2RPBA, HDLC #2 Receive Packet Bytes Available
Register
H1TFBA, HDLC #1 Transmit FIFO Buffer Available
Register
H2TFBA, HDLC #2 Transmit FIFO Buffer Available
Register
Key status information for both transmit and receive
directions
Selects which bits in Status Registers (SR7 and SR8) will
cause interrupts
Information on HDLC controller
Indicates the number of bytes that can be read from the
receive FIFO
Indicates the number of bytes that can be written to the
transmit FIFO
MAPPING
H1RCS1, H1RCS2, H1RCS3, H1RCS4, HDLC #1
Receive Channel Select Registers
H2RCS1, H2RCS2, H2RCS3, H2RCS4, HDLC #2
Receive Channel Select Registers
H1RTSBS, HDLC #1 Receive TS/Sa Bit Select Register
H2RTSBS, HDLC #2 Receive TS/Sa Bit Select Register
H1TCS1, H1TCS2, H1TCS3, H1TCS4, HDLC #1
Transmit Channel Select Registers
H2TCS1, H2TCS2, H2TCS3, H2TCS4, HDLC #2
Transmit Channel Select Registers
H1TTSBS, HDLC # 1 Transmit TS/Sa Bit Select Register
H2TTSBS, HDLC # 2 Transmit TS/Sa Bit Select Register
Selects which channels will be mapped to the receive
HDLC controller
Selects which bits in a channel will be used or which Sa bits
will be used by the receive HDLC controller
Selects which channels will be mapped to the transmit
HDLC controller
Selects which bits in a channel will be used or which Sa bits
will be used by the transmit HDLC controller
FIFOs
H1RF, HDLC #1 Receive FIFO Register
H2RF, HDLC #2 Receive FIFO Register
H1TF, HDLC #1 Transmit FIFO Register
H2TF, HDLC #2 Transmit FIFO Register
Access to 128-byte receive FIFO
Access to 128-byte transmit FIFO
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.2 HDLC Configuration
Basic configuration of the HDLC controllers is accomplished via the HxTC and HxRC registers.
Operating features such as CRC generation, zero stuffer, transmit and receive HDLC mapping options,
and idle flags are selected here. Also, the HDLC controllers are reset via these registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
NOFS
0
H1TC, H2TC
HDLC #1 Transmit Control, HDLC #2 Transmit Control
90h, A0h
6
TEOML
0
5
THR
0
4
THMS
0
3
TFS
0
2
TEOM
0
1
TZSD
0
0
TCRCD
0
Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message. This bit can
be used to disable the CRC function.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
Bit 1/Transmit Zero Stuffer Defeat (TZSD). The zero stuffer function automatically inserts a zero in the message field
(between the flags) after five consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The
receiver automatically removes (de-stuffs) any zero after five ones in the message field.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Bit 2/Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet is written
into the transmit FIFO at HxTF. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to
the end of the message.
Bit 3/Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before the
opening flags (7Eh).
0 = 7Eh
1 = FFh
Bit 4/Transmit HDLC Mapping Select (THMS).
0 = transmit HDLC assigned to channels
1 = transmit HDLC assigned to FDL (T1 mode), Sa Bits (E1 mode)
Bit 5/Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed
by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. Must be cleared
and set again for a subsequent reset.
0 = normal operation
1 = reset transmit HDLC controller and flush the transmit FIFO
Bit 6/Transmit End of Message and Loop (TEOML). To loop on a message, should be set to a one just before the last data
byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new
message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be
transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the
loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the
transmitter will automatically append a 2-byte CRC code to the end of all messages. This is useful for transmitting consecutive
SS7 FISUs without host intervention.
Bit 7/Number Of Flags Select (NOFS).
0 = send one flag between consecutive messages
1 = send two flags between consecutive messages
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RHR
0
H1RC, H2RC
HDLC #1 Receive Control, HDLC #2 Receive Control
31h, 32h
6
RHMS
0
5
—
0
4
—
0
3
HDLCD
0
2
—
0
1
—
0
0
RSFD
0
Bit 0/Receive SS7 Fill In Signal Unit Delete (RSFD).
0 = normal operation. All FISUs are stored in the receive FIFO and reported to the host.
1 = When a consecutive FISU having the same BSN the previous FISU is detected, it is deleted without host
intervention.
Bit 1/Unused, must be set to zero for proper operation.
Bit 2/Unused, must be set to zero for proper operation.
Bit 3/HDLC Disable. (HDLCD) Setting this bit will disable the transmit and receive HDLC function.
0 = transmit and receive HDLC enabled
1 = transmit and receive HDLC disabled
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Receive HDLC Mapping Select (RHMS).
0 = receive HDLC assigned to channels
1 = receive HDLC assigned to FDL (T1 mode), Sa Bits (E1 mode)
Bit 7/Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Must be cleared and
set again for a subsequent reset.
0 = normal operation
1 = reset receive HDLC controller and flush the receive FIFO
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.2.1 FIFO Control
Control of the transmit and receive FIFOs is accomplished via the FIFO control (HxFC). The FIFO
control register sets the watermarks for both the transmit and receive FIFO. Bits 3–5 set the transmit low
watermark and the lower 3 bits set the receive high watermark.
When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC
status register SR6 or SR7 will be set. TLWM is a real-time bit and will remain set as long as the transmit
FIFO’s read pointer is below the watermark. If enabled, this condition can also cause an interrupt via the
INT pin.
When the receive FIFO fills above the high watermark, the RHWM bit in the appropriate HDLC status
register will be set. RHWM is a real-time bit and will remain set as long as the receive FIFO’s write
pointer is above the watermark. If enabled, this condition can also cause an interrupt via the INT pin.
Register Name:
Register Description:
Register Address:
H1FC, H2FC
HDLC # 1 FIFO Control, HDLC # 2 FIFO Control
91h, A1h
Bit #
Name
Default
6
—
0
7
—
0
5
TFLWM2
0
4
TFLWM1
0
3
TFLWM0
0
2
RFHWM2
0
1
RFHWM1
0
Bits 0 to 2/Receive FIFO High Watermark Select (RFHWM0 to RFHWM2).
RFHWM2
0
0
0
0
1
1
1
1
RFHWM1
0
0
1
1
0
0
1
1
RFHWM0
0
1
0
1
0
1
0
1
RECEIVE FIFO WATERMARK (BYTES)
4
16
32
48
64
80
96
112
Bits 3 to 5/Transmit FIFO Low Watermark Select (TFLWM0 to TFLWM2).
TFLWM2
0
0
0
0
1
1
1
1
TFLWM1
0
0
1
1
0
0
1
1
TFLWM0
0
1
0
1
0
1
0
1
TRANSMIT FIFO WATERMARK (BYTES)
4
16
32
48
64
80
96
112
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
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0
RFHWM0
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.3 HDLC Mapping
24.3.1 Receive
The HDLC controllers need to be assigned a space in the T1/E1 bandwidth in which they will transmit
and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1), or to channels. If
mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to
an HDLC controller. When assigned to a channel(s) any combination of bits within the channel(s) can be
avoided.
The HxRCS1–HxRCS4 registers are used to assign the receive controllers to channels 1–24 (T1) or
1–32 (E1) according to the following table.
REGISTER
HxRCS1
HxRCS2
HxRCS3
HxRCS4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RHCS7
0
CHANNELS
1–8
9–16
17–24
25–32
H1RCS1, H1RCS2, H1RCS3, H1RCS4
H2RCS1, H2RCS2, H2RCS3, H2RCS4
HDLC # 1 Receive Channel Select x
HDLC # 2 Receive Channel Select x
92h, 93h, 94h, 95h
A2h, A3h, A4h, A5h
6
RHCS6
0
5
RHCS5
0
4
RHCS4
0
3
RHCS3
0
2
RHCS2
0
1
RHCS1
0
Bit 0/Receive HDLC Channel Select Bit 0 (RHCS0). Select Channel 1, 9, 17, or 25.
Bit 1/Receive HDLC Channel Select Bit 1 (RHCS1). Select Channel 2, 10, 18, or 26.
Bit 2/Receive HDLC Channel Select Bit 2 (RHCS2). Select Channel 3, 11, 19, or 27.
Bit 3/Receive HDLC Channel Select Bit 3 (RHCS3). Select Channel 4, 12, 20, or 28.
Bit 4/Receive HDLC Channel Select Bit 4 (RHCS4). Select Channel 5, 13, 21, or 29.
Bit 5/Receive HDLC Channel Select Bit 5 (RHCS5). Select Channel 6, 14, 22, or 30.
Bit 6/Receive HDLC Channel Select Bit 6 (RHCS6). Select Channel 7, 15, 23, or 31.
Bit 7/Receive HDLC Channel Select Bit 7 (RHCS7). Select Channel 8, 16, 24, or 32.
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0
RHCS0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RCB8SE
0
H1RTSBS, H2RTSBS
HDLC # 1 Receive Time Slot Bits/Sa Bits Select
HDLC # 2 Receive Time Slot Bits/Sa Bits Select
96h, A6h
6
RCB7SE
0
5
RCB6SE
0
4
RCB5SE
0
3
RCB4SE
0
2
RCB3SE
0
1
RCB2SE
0
0
RCB1SE
0
Bit 0/Receive Channel Bit 1 Suppress Enable/Sa8 Bit Enable (RCB1SE ). LSB of the channel. Set to one to stop this bit
from being used when the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa
bits.
Bit 1/Receive Channel Bit 2 Suppress Enable/Sa7 Bit Enable (RCB2SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 2/Receive Channel Bit 3 Suppress Enable/Sa6 Bit Enable (RCB3SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 3/Receive Channel Bit 4 Suppress Enable/Sa5 Bit Enable (RCB4SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 4/Receive Channel Bit 5 Suppress Enable/Sa4 Bit Enable (RCB5SE). Set to one to stop this bit from being used when
the HDLC is mapped to time slots. Set to one to enable the use of Sa8 bit when HDLC mapped is Sa bits.
Bit 5/Receive Channel Bit 6 Suppress Enable (RCB6SE). Set to one to stop this bit from being used.
Bit 6/Receive Channel Bit 7 Suppress Enable (RCB7SE). Set to one to stop this bit from being used.
Bit 7/Receive Channel Bit 8 Suppress Enable (RCB8SE). MSB of the channel. Set to one to stop this bit from being used.
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24.3.2 Transmit
The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or
1–32 (E1), according to the following table.
REGISTER
HxTCS1
HxTCS2
HxTCS3
HxTCS4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
THCS7
0
CHANNELS
1–8
9–16
17–24
25–32
H1TCS1, H1TCS2, H1TCS3, H1TCS4
H2TCS1, H2TCS2, H2TCS3, H2TCS4
HDLC # 1 Transmit Channel Select
HDLC # 2 Transmit Channel Select
97h, 98h, 99h, 9Ah
A7h, A8h, A9h, AAh
6
THCS6
0
5
THCS5
0
4
THCS4
0
3
THCS3
0
2
THCS2
0
1
THCS1
0
Bit 0/Transmit HDLC Channel Select Bit 0 (THCS0). Select Channel 1, 9, 17, or 25.
Bit 1/Transmit HDLC Channel Select Bit 1 (THCS1). Select Channel 2, 10, 18, or 26.
Bit 2/Transmit HDLC Channel Select Bit 2 (THCS2). Select Channel 3, 11, 19, or 27.
Bit 3/Transmit HDLC Channel Select Bit 3 (THCS3). Select Channel 4, 12, 20, or 28.
Bit 4/Transmit HDLC Channel Select Bit 4 (THCS4). Select Channel 5, 13, 21, or 29.
Bit 5/Transmit HDLC Channel Select Bit 5 (THCS5). Select Channel 6, 14, 22, or 30.
Bit 6/Transmit HDLC Channel Select Bit 6 (THCS6). Select Channel 7, 15, 23, or 31.
Bit 7/Transmit HDLC Channel Select Bit 7 (THCS7). Select Channel 8, 16, 24, or 32.
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0
THCS0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TCB8SE
0
H1TTSBS, H2TTSBS
HDLC # 1 Transmit Time Slot Bits/Sa Bits Select
HDLC # 2 Transmit Time Slot Bits/Sa Bits Select
9Bh, Abh
6
TCB7SE
0
5
TCB6SE
0
4
TCB5SE
0
3
TCB4SE
0
2
TCB3SE
0
1
TCB2SE
0
0
TCB1SE
0
Bit 0/Transmit Channel Bit 1 Suppress Enable / Sa8 Bit Enable (TCB1SE). LSB of the channel. Set to one to stop this bit
from being used.
Bit 1/Transmit Channel Bit 2 Suppress Enable/ Sa7 Bit Enable (TCB1SE). Set to one to stop this bit from being used.
Bit 2/Transmit Channel Bit 3 Suppress Enable/Sa6 Bit Enable (TCB1SE). Set to one to stop this bit from being used.
Bit 3/Transmit Channel Bit 4 Suppress Enable/Sa5 Bit Enable (TCB1SE). Set to one to stop this bit from being used.
Bit 4/Transmit Channel Bit 5 Suppress Enable/Sa4 Bit Enable (TCB1SE). Set to one to stop this bit from being used.
Bit 5/Transmit Channel Bit 6 Suppress Enable (TCB1SE). Set to one to stop this bit from being used.
Bit 6/Transmit Channel Bit 7 Suppress Enable (TCB1SE). Set to one to stop this bit from being used.
Bit 7/Transmit Channel Bit 8 Suppress Enable (TCB1SE). MSB of the channel. Set to one to stop this bit from being used.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
SR6, SR7
HDLC #1 Status Register 6
HDLC #2 Status Register 7
20h, 22h
6
TMEND
0
5
RPE
0
4
RPS
0
3
RHWM
0
2
RNE
0
1
TLWM
0
0
TNF
0
Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the transmit 128-byte FIFO has at least one byte available.
Bit 1/Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 128-byte FIFO empties beyond
the low watermark as defined by the Transmit Low Watermark Register (TLWMR).
Bit 2/Receive FIFO Not Empty Condition (RNE). Set when the receive 128-byte FIFO has at least one byte available for a
read.
Bit 3/Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 128-byte FIFO fills beyond the
high watermark as defined by the receive high-watermark register (RHWMR).
Bit 4/Receive Packet Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a latched bit and will
be cleared when read.
Bit 5/Receive Packet End Event (RPE). Set when the HDLC controller detects either the finish of a valid message (i.e., CRC
check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun
condition, or an abort has been seen. This is a latched bit and will be cleared when read.
Bit 6/Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. This
is a latched bit and will be cleared when read.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
IMR6, IMR7
HDLC # 1 Interrupt Mask Register 6
HDLC # 2 Interrupt Mask Register 7
21h, 23h
6
TMEND
0
5
RPE
0
4
RPS
0
3
RHWM
0
Bit 0/Transmit FIFO Not Full Condition (TNF).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 1/Transmit FIFO Below Low Watermark Condition (TLWM).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 2/Receive FIFO Not Empty Condition (RNE).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 3/Receive FIFO Above High Watermark Condition (RHWM).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising edge only
Bit 4/Receive Packet Start Event (RPS).
0 = interrupt masked
1 = interrupt enabled
Bit 5/Receive Packet End Event (RPE).
0 = interrupt masked
1 = interrupt enabled
Bit 6/Transmit Message End Event (TMEND).
0 = interrupt masked
1 = interrupt enabled
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2
RNE
0
1
TLWM
0
0
TNF
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
INFO5, INFO6
HDLC #1 Information Register
HDLC #2 Information Register
2Eh, 2Fh
6
—
0
5
TEMPTY
0
4
TFULL
0
3
REMPTY
0
2
PS2
0
1
PS1
0
0
PS0
0
Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive
FIFO.
PS2
0
0
0
0
1
1
PS1
0
0
1
1
0
0
PS0
0
1
0
1
0
1
PACKET STATUS
In Progress: End of message has not yet been reached.
Packet OK: Packet ended with correct CRC codeword.
CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.
Abort: Packet ended because an abort signal was detected (seven or more ones in a row).
Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
Message Too Short: Three or fewer bytes including CRC.
Bit 3/Receive FIFO Empty (REMPTY). A real-time bit that is set high when the receive FIFO is empty.
Bit 4/Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 5/Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Register Name:
Register Description:
Register Address:
INFO4
HDLC Event Information Register #4
2Dh
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
H2UDR
0
2
H2OBT
0
1
H1UDR
0
0
H1OBT
0
Bit 0/HDLC #1 Opening Byte Event (H1OBT). Set when the next byte available in the receive FIFO is the first byte of a
message.
Bit 1/HDLC #1 Transmit FIFO Underrun Event (H1UDR). Set when the transmit FIFO empties out without having seen
the TMEND bit set. An abort is automatically sent. This bit is latched and will be cleared when read.
Bit 2/HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first byte of a
message.
Bit 3/HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without having seen
the TMEND bit set. An abort is automatically sent. This bit is latched and will be cleared when read.
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24.3.3 FIFO Information
The transmit FIFO buffer-available register indicates the number of bytes that can be written into the
transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TFBA7
0
H1TFBA, H2TFBA
HDLC # 1 Transmit FIFO Buffer Available
HDLC # 2 Transmit FIFO Buffer Available
9Fh, Afh
6
TFBA6
0
5
TFBA5
0
4
TFBA4
0
3
TFBA3
0
2
TFBA2
0
1
TFBA1
0
0
TFBA0
0
Bits 0 to 7/Transmit FIFO Bytes Available (TFBAO to TFBA7). TFBA0 is the LSB.
24.3.4 Receive Packet Bytes Available
The lower 7 bits of the receive packet bytes available register indicate the number of bytes (0 through
127) that can be read from the receive FIFO. The value indicated by this register (lower 7 bits) informs
the host as to how many bytes can be read from the receive FIFO without going past the end of a
message. This value will refer to one of four possibilities: the first part of a packet, the continuation of a
packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this
register, the host then checks the HDLC information register for detailed message status.
If the value in the HxRPBA register refers to the beginning portion of a message or continuation of a
message then the MSB of the HxRPBA register will return a value of 1. This indicates that the host can
safely read the number of bytes returned by the lower 7 bits of the HxRPBA register but there is no need
to check the information register since the packet has not yet terminated (successfully or otherwise).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
MS
0
H1RPBA, H2RPBA
HDLC # 1 Receive Packet Bytes Available
HDLC # 2 Receive Packet Bytes Available
9Ch, Ach
6
RPBA6
0
5
RPBA5
0
4
RPBA4
0
3
RPBA3
0
2
RPBA2
0
1
RPBA1
0
0
RPBA0
0
Bits 0 to 6/Receive FIFO Packet Bytes Available Count (RPBA0 to RPBA6). RPBA0 is the LSB.
Bit 7/Message Status (MS).
0 = bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the INFO5 or INFO6
register for details.
1 = bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not
need to check the INFO5 or INFO6 register.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.3.5 HDLC FIFOS
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
THD7
0
H1TF, H2TF
HDLC # 1 Transmit FIFO, HDLC # 2 Transmit FIFO
9Dh, Adh
6
THD6
0
5
THD5
0
4
THD4
0
3
THD3
0
2
THD2
0
1
THD1
0
0
THD0
0
1
RHD1
0
0
RHD0
0
Bit 0/Transmit HDLC Data Bit 0 (THD0). LSB of a HDLC packet data byte.
Bit 1/Transmit HDLC Data Bit 1 (THD1).
Bit 2/Transmit HDLC Data Bit 2 (THD2).
Bit 3/Transmit HDLC Data Bit 3 (THD3).
Bit 4/Transmit HDLC Data Bit 4 (THD4).
Bit 5/Transmit HDLC Data Bit 5 (THD5).
Bit 6/Transmit HDLC Data Bit 6 (THD6).
Bit 7/Transmit HDLC Data Bit 7 (THD7). MSB of a HDLC packet data byte.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RHD7
0
H1RF, H2RF
HDLC # 1 Receive FIFO, HDLC # 2 Receive FIFO
9Eh, Aeh
6
RHD6
0
5
RHD5
0
4
RHD4
0
3
RHD3
0
2
RHD2
0
Bit 0/Receive HDLC Data Bit 0 (RHD0). LSB of a HDLC packet data byte.
Bit 1/Receive HDLC Data Bit 1 (RHD1).
Bit 2/Receive HDLC Data Bit 2 (RHD2).
Bit 3/Receive HDLC Data Bit 3 (RHD3).
Bit 4/Receive HDLC Data Bit 4 (RHD4).
Bit 5/Receive HDLC Data Bit 5 (RHD5).
Bit 6/Receive HDLC Data Bit 6 (RHD6).
Bit 7/Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.4 Receive HDLC Code Example
Below is an example of a receive HDLC routine for controller #1.
1) Reset receive HDLC controller.
2) Set HDLC mode, mapping, and high watermark.
3) Start new message buffer.
4) Enable RPE and RHWM interrupts.
5) Wait for interrupt.
6) Disable RPE and RHWM interrupts.
7) Read HxRPBA register. N = HxRPBA (lower 7 bits are byte count, MSB is status).
8) Read (N AND 7Fh) bytes from receive FIFO and store in message buffer.
9) Read INFO5 register.
10) If PS2, PS1, PS0 = 000, then go to step 4.
11) If PS2, PS1, PS0 = 001, then packet terminated OK, save present message buffer.
12) If PS2, PS1, PS0 = 010, then packet terminated with CRC error.
13) If PS2, PS1, PS0 = 011, then packet aborted.
14) If PS2, PS1, PS0 = 100, then FIFO overflowed.
15) Go to step 3.
24.5 Legacy FDL Support (T1 Mode)
To provide backward compatibility to the older DS21x52 T1 device, the DS21455/DS21458 maintain the
circuitry that existed in the previous generation of the T1 framer. In new applications, it is recommended
that the HDLC controllers and BOC controller are used.
24.5.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2ms (8 x 250ms). The framer will
signal an external microcontroller that the buffer has filled via the SR8.3 bit. If enabled via IMR8.3, the
INT pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2ms to
read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the
RFDLM1 or RFDLM2 registers, then the SR8.1 bit will be set to a one and the INT pin will toggled low
if enabled via IMR8.1. This feature allows an external microcontroller to ignore the FDL or Fs pattern
until an important event occurs.
The framer also contains a zero destuffer, which is controlled via the T1RCR2.3 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than five ones should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via T1RCR2.3, the device
will automatically look for five ones in a row, followed by a zero. If it finds such a pattern, it will
automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a zero, the
zero is not removed. The T1RCR2.3 bit should always be set to a one when the device is extracting the
FDL. More on how to use the DS21455/DS21458 in FDL applications in this legacy support mode is
covered in a separate application note.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RFDL7
0
RFDL
Receive FDL Register
C0h
6
RFDL6
0
5
RFDL5
0
4
RFDL4
0
3
RFDL3
0
2
RFDL2
0
1
RFDL1
0
0
RFDL0
0
Bit 0/Receive FDL Bit 0 (RFDL0). LSB of the Received FDL Code.
Bit 1/Receive FDL Bit 1 (RFDL1).
Bit 2/Receive FDL Bit 2 (RFDL2).
Bit 3/Receive FDL Bit 3 (RFDL3).
Bit 4/Receive FDL Bit 4 (RFDL4).
Bit 5/Receive FDL Bit 5 (RFDL5).
Bit 6/Receive FDL Bit 6 (RFDL6).
Bit 7/Receive FDL Bit 7 (RFDL7). MSB of the Received FDL Code.
The receive FDL register (RFDL) reports the incoming facility data link (FDL) or the incoming Fs bits. The LSB is received
first.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RFDLM7
0
RFDLM1, RFDLM2
Receive FDL Match Register 1
Receive FDL Match Register 2
C2h, C3h
6
RFDLM6
0
5
RFDLM5
0
4
RFDLM4
0
3
RFDLM3
0
2
RFDLM2
0
Bit 0/Receive FDL Match Bit 0 (RFDLM0). LSB of the FDL Match Code.
Bit 1/Receive FDL Match Bit 1 (RFDLM1).
Bit 2/Receive FDL Match Bit 2 (RFDLM2).
Bit 3/Receive FDL Match Bit 3 (RFDLM3).
Bit 4/Receive FDL Match Bit 4 (RFDLM4).
Bit 5/Receive FDL Match Bit 5 (RFDLM5).
Bit 6/Receive FDL Match Bit 6 (RFDLM6).
Bit 7/Receive FDL Match Bit 7 (RFDLM7). MSB of the FDL Match Code.
156 of 270
1
RFDLM1
0
0
RFDLM0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.5.2 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new value is
written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1
data stream. After the full eight bits has been shifted out, the framer will signal the host microcontroller
that the buffer is empty and that more data is needed by setting the SR8.2 bit to a one. The INT will also
toggle low if enabled via IMR8.2. The user has 2ms to update the TFDL with a new value. If the TFDL is
not updated, the old value in the TFDL will be transmitted once again. The framer also contains a zero
stuffer which is controlled via the T1TCR2.5 bit. In both ANSI T1.403 and TR54016, communications on
the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five ones
should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110)
or an abort signal (11111111). If enabled via T1TCR2.5, the framer will automatically look for 5 ones in
a row. If it finds such a pattern, it will automatically insert a zero after the five ones. The T1TCR2.5 bit
should always be set to a one when the framer is inserting the FDL.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TFDL7
0
TFDL
Transmit FDL Register
C1h
6
TFDL6
0
5
TFDL5
0
4
TFDL4
0
3
TFDL3
0
2
TFDL2
0
1
TFDL1
0
0
TFDL0
0
(Note: Also used to insert Fs framing pattern in D4 framing mode.)
Bit 0/Transmit FDL Bit 0 (TFDL0). LSB of the Transmit FDL Code.
Bit 1/Transmit FDL Bit 1 (TFDL1).
Bit 2/Transmit FDL Bit 2 (TFDL2).
Bit 3/Transmit FDL Bit 3 (TFDL3).
Bit 4/Transmit FDL Bit 4 (TFDL4).
Bit 5/Transmit FDL Bit 5 (TFDL5).
Bit 6/Transmit FDL Bit 6 (TFDL6).
Bit 7/Transmit FDL Bit 7 (TFDL7). MSB of the Transmit FDL Code.
The transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into
the outgoing T1 data stream. The LSB is transmitted first.
24.6 D4/SLC-96 Operation
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the
device to properly insert the Fs framing pattern, the TFDL register at address C1h must be programmed
to 1Ch and the following bits must be programmed as shown: T1TCR1.2 = 0 (source Fs data from the
TFDL register) T1TCR2.6 = 1 (allow the TFDL register to load on multiframe boundaries).
Since the SLC-96 message fields share the Fs-bit position, the user can access these message fields via
the TFDL and RFDL registers. Please see the separate application note for a detailed description of how
to implement a SLC-96 function.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
25. LINE INTERFACE UNIT (LIU)
The LIU in the DS21455/DS21458 contains three sections: the receiver, which handles clock and data
recovery; the transmitter, which wave-shapes and drives the network line; and the jitter attenuator. These
three sections are controlled by the line interface control registers (LIC1–LIC4), which are described
below. The LIU has its own T1/E1 mode select bit and can operate independently of the framer function.
The DS21455/DS21458 can switch between T1 or E1 networks without changing any external
components on either the transmit or receive side. Figure 25-1 and Figure 25-2 show basic balanced and
unbalanced network connections using minimal components. In this configuration the device can connect
to T1, J1, or E1 (75Ω or 120Ω) without any component change. The receiver can adjust the 120Ω
termination to 100Ω or 75Ω. The transmitter can adjust its output impedance to provide high return loss
characteristics for 120Ω, 100Ω, and 75Ω lines. Other components may be added to this configuration in
order to meet safety and network protection requirements. This is covered in Section 25.8 (Recommended
Circuits).
Figure 25-1. Basic Balanced Network Connections
TTIP
0.047mF
Tx
TRING
RTIP
DS21455/
DS21458
Rx
RRING
60W*
60W*
0.01mF
*USE 60W WHEN USING INTERNAL TERMINATION FEATURE.
158 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 25-2. Basic Unbalanced Network Connections
TTIP
0.047mF
Tx
TRING
RTIP
DS21455/
DS21458
Rx
RRING
60W*
60W*
0.01mF
*USE 60W WHEN USING INTERNAL TERMINATION FEATURE.
25.1 LIU Operation
The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RTIP and RRING pins of the DS21455/DS21458. The user has the option to
use internal termination, software selectable for 75Ω/100Ω/120Ω applications, or external termination.
The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation MUX
outputting the received line clock at RCLKO and bipolar or NRZ data at RPOSO and RNEGO. The
DS21455/DS21458 contain an active filter that reconstructs the analog received signal for the nonlinear
losses that occur in transmission. The receive circuitry also is configurable for various monitor
applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1,
which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in
length. Data input at TPOSI and TNEGI is sent via the jitter attenuation MUX to the wave shaping
circuitry and line driver. The DS21455/DS21458 will drive the E1 or T1 line from the TTIP and TRING
pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and
long-haul (CSU) or short-haul (DSX-1) lines for T1.
25.2 LIU Receiver
The DS21455/DS21458 contain a digital clock recovery system. The device couples to the receive E1 or
T1 twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 transformer. See Table 25-6 for
transformer details. The DS21455/DS21458 have the option of using software-selectable termination
requiring only a single, fixed pair of termination resistors.
The DS21455/DS21458’s LIU is designed to be fully software selectable for E1 and T1 without the need
to change any external resistors for the receive-side. The receive-side will allow the user to configure the
device for 75Ω, 100Ω, or 120Ω receive termination by setting the RT1 (LIC4.1) and RT0 (LIC4.0) bits.
When using the internal termination feature, the resistors labeled R in Table 25-5 should be 60Ω each. If
external termination is required, the resistors labeled R in Figure 25-5 will need to be 37.5Ω, 50Ω, or 60Ω
each, depending on the line impedance.
159 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
There are two ranges of receive sensitivity for both T1 and E1, which is selectable by the user. The EGL
bit of LIC1 (LIC1.4) selects the full or limited sensitivity.
The resultant E1 or T1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the
clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times
over-sampler, which is used to recover the clock and data. This oversampling technique offers
outstanding performance to meet jitter tolerance specifications shown in Figure 25-9.
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the
receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an
approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLK output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-sampled
digital clock recovery circuitry. See the Receive AC Timing Characteristics section for more details.
When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition will occur and the
RCLK will be derived from the JACLK source.
25.2.1 Receive Level Indicator
The DS21455/DS21458 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3RL0 located in the Information Register 2 (INFO2). This feature is helpful when trouble shooting line
performance problems.
25.2.2 Receive G.703 Section 10 Synchronization Signal
The DS21455/DS21458 can receive a 2.048MHz square-wave synchronization clock as specified in
Section 10 of ITU G.703. To use this mode, set the receive synchronization clock enable (LIC3.2) = 1.
25.2.3 Monitor Mode
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS21455/DS21458 can be programmed to support these applications via the monitor mode control
bits MM1 and MM0 in the LIC3 register. Figure 25-3 depicts a typical monitor-mode application.
Figure 25-3. Typical Monitor Application
PRIMARY T1/E1
TERMINATING
DEVICE
T1/E1 LINE
Rm
Rm
X
F
M
R
MONITOR
PORT JACK
Rt
DS21455/
DS21458
SECONDARY T1/E1
TERMINATING DEVICE
160 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
25.3 LIU Transmitter
The DS21455/DS21458 use a phase-lock loop along with a precision digital-to-analog converter (DAC)
to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the
transmitter meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which
waveform is to be generated by setting the ETS bit (LIC2.7) for E1 or T1 operation, then programming
the L2/L1/L0 bits in register LIC1 for the appropriate application.
A 2.048MHz or 1.544MHz clock is required at TCLKI for transmitting data presented at TPOSI and
TNEGI. Normally these pins are connected to TCLKO, TPOSO and TNEGO. However, the LIU may
operate in an independent fashion. ITU specification G.703 requires an accuracy of ±50ppm for both T1
and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. The clock can be
sourced internally from RCLK or JACLK. See LIC2.3, LIC4.4 and LIC4.5 for details. Due to the nature
of the design of the transmitter, very little jitter (less than 0.005 UIP-P broadband from 10Hz to 100kHz) is
added to the jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of
TCLK. The transmitter couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1
applications) via a 1:2 step-up transformer. In order for the device to create the proper waveforms, the
transformer used must meet the specifications listed in Table 25-6. The DS21455/DS21458 have the
option of using software-selectable transmit termination.
The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode,
the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the
automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the
network load. Automatic Gain Control is enabled by default. See the Transmit Line Build-Out Control
(TLBC) register for details.
25.3.1 Transmit Short-Circuit Detector/Limiter
The DS21455/DS21458 have automatic short-circuit limiters that limit the source current to 50mA
(RMS) into a 1W load. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE
(INFO2.5) provides a real-time indication of when the current limiter is activated. If the current limiter is
disabled, TCLE will indicate that a short-circuit condition exist. Status Register SR1.2 provides a latched
version of the information, which can be used to activate an interrupt when enable via the IMR1 register.
When set low, the TPD bit (LIC1.0) will power-down the transmit line driver and tri-state the TTIP and
TRING pins.
25.3.2 Transmit Open-Circuit Detector
The DS21455/DS21458 can also detect when the TTIP or TRING outputs are open circuited. TOCD
(INFO2.4) will provide a real-time indication of when an open circuit is detected. SR1 provides a latched
version of the information (SR1.1), which can be used to activate an interrupt when enable via the IMR1
register.
161 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
25.3.3 Transmit BPV Error Insertion
When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion.
25.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
The DS21455/DS21458 can transmit the 2.048MHz square-wave synchronization clock. When in E1
mode, to transmit the 2.048MHz clock, set the transmit synchronization clock enable (LIC3.1) = 1.
25.4 MCLK Prescaler
A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at the MCLK pin.
ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs
require an accuracy of ±32ppm for T1 interfaces. A prescaler will divide the 16MHz, 8MHz, or 4MHz clock
down to 2.048MHz. There is an onboard PLL for the jitter attenuator that will convert the 2.048MHz clock to
a 1.544MHz rate for T1 applications. Setting JAMUX (LIC2.3) to a logic 0 bypasses this PLL.
25.5 Jitter Attenuator
The DS21455/DS21458 contain an on-board jitter attenuator that can be set to a depth of either 32 bits or
128 bits via the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of
wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the
attenuation are shown in Figure 25-10 and Figure 25-11. The jitter attenuator can be placed in either the
receive path or the transmit path by appropriately setting or clearing the JAS bit (LIC1.3). Also, the jitter
attenuator can be disabled (in effect, removed) by setting the DJA bit (LIC1.1). Onboard circuitry adjusts
either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to
create a smooth jitter free clock, which is used to clock data out of the jitter attenuator FIFO. It is
acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the
transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer
depth is 32 bits), then the jitter attenuator will divide the internal nominal 32.768MHz (E1) or
24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing.
When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in
Status Register 1 (SR1.4).
162 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
25.6 CMI (Code Mark Inversion) Option
The DS21455/DS21458 provide a CMI interface for connection to optical transports. This interface is a
unipolar 1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration
of the clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period.
Figure 25-4. CMI Coding
CLOCK
DATA
1
1
0
1
0
0
1
CMI
Transmit and receive CMI is enabled via LIC4.7. When this register bit is set, the TTIP pin will output
CMI-coded data at normal levels. This signal can be used to directly drive an optical interface. When
CMI is enabled, the user can also use HDB3/B8ZS coding. When this register bit is set, the RTIP pin will
become a unipolar CMI input. The CMI signal will be processed to extract and align the clock with data.
163 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
25.7 LIU Control Registers
Register Name:
Register Description:
Register Address:
LIC1
Line Interface Control 1
78h
Bit #
Name
Default
6
L1
0
7
L2
0
5
L0
0
4
EGL
0
3
JAS
0
2
JABDS
0
1
DJA
0
0
TPD
0
Bit 0/Transmit Power-Down (TPD). This bit along with the LIUC/TPD pin and the LTS (LBCR.7) bit controls the transmit
power-down function.
0 = powers down the transmitter and tri-states the TTIP and TRING pins
1 = normal transmitter operation
Table 25-1. TPD CONTROL
LBCR.7
(LTS)
0
0
1
1
1
1
LIUC/TPD
PIN
X
X
0
0
1
1
LIC1.0
(TPD)
0
1
0
1
0
1
FUNCTION
Transmitter in power-down mode, TTIP and TRING tri-stated
Transmitter enabled
Transmitter in power-down mode, TTIP and TRING tri-stated
Transmitter enabled
Transmitter in power-down mode, TTIP and TRING tri-stated
Transmitter in power-down mode, TTIP and TRING tri-stated
Bit 1/Disable Jitter Attenuator (DJA).
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Bit 2/Jitter Attenuator Buffer Depth Select (JABDS).
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Bit 3/Jitter Attenuator Select (JAS).
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Bit 4/Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer.
T1 Mode: 0 = -36dB (long haul)
1 = -15dB (limited long haul)
E1 Mode: 0 = -12dB (short haul)
1 = -43dB (long haul)
Bits 5 to 7/Line Build-Out Select (L0 to L2). These bits select the output waveshape. See Table 25-2, Table 25-3, Table
25-4, and Table 25-5 for the correct register settings for specific applications. In E1 mode, when using the internal termination,
the user needs only to select 000 for 75Ω operation or 001 for 120Ω operation. Using TT0 and TT1 of the LICR4 register,
users can then select the proper internal source termination. Line build-outs 100 and 101 are provided for backward
compatibility with older products only.
164 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Table 25-2. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0)
APPLICATION
75W Normal
120W Normal
75W with High Return Loss*
120W with High Return Loss*
LIC1.7
(L2)
0
0
1
1
LIC1.6
(L1)
0
0
0
0
LIC1.5
(L0)
0
1
0
1
PSA1
(F1h)
20h
20h
00h
20h
PSA2
(F2h)
08h
00h
00h
00h
RETURN
LOSS
N.M.**
N.M.
21dB
21dB
Rt (1)
0
0
6.2Ω
11.6Ω
Table 25-3. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1)
APPLICATION
75W Normal
120W Normal
75W with High Return Loss*
120W with High Return Loss*
LIC1.7
(L2)
0
0
1
1
LIC1.6
(L1)
0
0
0
0
LIC1.5
(L0)
0
1
0
1
PSA1
(F1h)
20h
00h
00h
00h
PSA2
(F2h)
08h
00h
00h
00h
RETURN
LOSS
N.M.
N.M.
21dB
21dB
Rt (1)
0
0
6.2Ω
11.6Ω
Table 25-4. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0)
APPLICATION
0dB CSU
DSX-1 (0 to 133 feet)/0dB CSU
DSX-1 (133 to 266 feet)
DSX-1 (266 to 399 feet)
DSX-1 (399 to 533 feet)
DSX-1 (533 to 655 feet)
-7.5dB CSU
-15dB CSU
-22.5dB CSU
LIC1.7
(L2)
0
0
0
0
0
1
1
1
1
LIC1.6
(L1)
0
0
0
1
1
0
0
1
1
LIC1.5
(L0)
0
0
1
0
1
0
1
0
1
PSA1
(F1h)
00h
00h
0Ah
0Ah
00h
0Ah
00h
00h
00h
PSA2
(F2h)
00h
00h
00h
00h
00h
00h
00h
00h
00h
RETURN
LOSS
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
Rt (1)
0
0
0
0
0
0
0
0
0
Table 25-5. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1)
APPLICATION
0dB CSU
DSX-1 (0 to 133 feet)/0dB CSU
DSX-1 (133 to 266 feet)
DSX-1 (266 to 399 feet)
DSX-1 (399 to 533 feet)
DSX-1 (533 to 655 feet)
-7.5dB CSU
-15dB CSU
-22.5dB CSU
LIC1.7
(L2)
0
0
0
0
0
1
1
1
1
LIC1.6
(L1)
0
0
0
1
1
0
0
1
1
LIC1.5
(L0)
0
0
1
0
1
0
1
0
1
*TT0 and TT1 of the LIC4 register must be set to zero in this configuration.
**N.M. = not meaningful.
165 of 270
PSA1
(F1h)
00h
00h
00h
00h
00h
00h
00h
00h
00h
PSA2
(F2h)
00h
00h
00h
00h
00h
00h
00h
00h
00h
RETURN
LOSS
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
Rt (1)
0
0
0
0
0
0
0
0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
TLBC
Transmit Line Build-Out Control
7Dh
6
AGCD
0
5
GC5
0
4
GC4
0
3
GC3
0
2
GC2
0
1
GC1
0
0
GC0
0
Bit 0–5/Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting automatic gain control is
disabled. Use the tables below for setting the recommended values. The LB (line build-out) column refers to the value in the
L0–L2 bits in LIC1 (Line Interface Control 1) register.
NETWORK MODE
T1, Impedance Match Off
T1, Impedance Match On
E1, Impedance Match Off
E1, Impedance Match On
LB
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
4
5
1
2
GC5
1
0
0
1
1
1
0
1
0
0
0
0
1
1
0
1
1
1
1
1
0
0
GC4
0
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
GC3
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
1
GC2
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
Bit 6/Automatic Gain Control Disable (AGCD).
0 = use Transmit AGC, TLBC bits 0–5 are “don’t care”
1 = do not use Transmit AGC, TLBC bits 0–5 set nominal level
Bit 7/Unused, must be set to zero for proper operation.
166 of 270
GC1
1
1
1
0
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
GC0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
0
0
0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ETS
0
LIC2
Line Interface Control 2
79h
6
LIRST
0
5
IBPV
0
4
TUA1
0
3
JAMUX
0
2
—
0
1
SCLD
0
0
CLDS
0
Bit 0/Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver.
When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 = 0, then the device will generate a square wave at the TTIP and
TRING outputs instead of a normal waveform. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 ¹ 0, then the device
will force TTIP and TRING outputs to become open-drain drivers instead of their normal push-pull operation. This bit should
be set to zero for normal operation of the device.
Bit 1/Short Circuit Limit Disable (ETS = 1) (SCLD). Controls the 50mA (RMS) current limiter.
0 = enable 50mA current limiter
1 = disable 50mA current limiter
Bit 2/Unused, must be set to zero for proper operation.
Bit 3/Jitter Attenuator MUX (JAMUX). Controls the source for JACLK.
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
Bit 4/Transmit Unframed All Ones (TUA1). The polarity of this bit is set such that the device will transmit an all ones
pattern on power-up or device reset. This bit must be set to a one to allow the device to transmit data. The transmission of this
data pattern is always timed off of the JACLK.
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
Bit 5/Insert BPV (IBPV). A zero-to-one transition on this bit will cause a single BPV to be inserted into the transmit data
stream. Once this bit has been toggled from a zero to a one, the device waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted.
Bit 6/Line Interface Reset (LIRST). Setting this bit from a zero to a one will initiate an internal reset that resets the clock
recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and
set again for a subsequent reset.
Bit 7/E1/T1 Select (ETS).
0 = T1 Mode Selected
1 = E1 Mode Selected
167 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
LIC3
Line Interface Control 3
7Ah
6
TCES
0
5
RCES
0
4
MM1
0
3
MM0
0
2
RSCLKE
0
1
TSCLKE
0
0
TAOZ
0
Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (Customer Disconnect Indication
Signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLK.
0 = disabled
1 = enabled
Bit 1/Transmit Synchronization G.703 Clock Enable (TSCLKE).
0 = disable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
1 = enable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
Bit 2/Receive Synchronization G.703 Clock Enable (RSCLKE).
0 = disable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
1 = enable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
Bits 3 to 4/Monitor Mode (MM0 to MM1).
MM1
MM0
0
0
1
1
0
1
0
1
INTERNAL LINEAR
GAIN BOOST (dB)
Normal operation (no boost)
20
26
32
Bit 5/Receive Clock Edge Select (RCES). Selects which RCLKO edge to update RPOSO and RNEGO.
0 = update RPOSO and RNEGO on rising edge of RCLKO
1 = update RPOSO and RNEGO on falling edge of RCLKO
Bit 6/Transmit Clock Edge Select (TCES). Selects which TCLKI edge to sample TPOSI and TNEGI.
0 = sample TPOSI and TNEGI on falling edge of TCLKI
1 = sample TPOSI and TNEGI on rising edge of TCLKI
Bit 7/Unused, must be set to zero for proper operation.
168 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LIC4
Line Interface Control 4
7Bh
7
CMIE
0
6
CMII
0
5
MPS1
0
4
MPS0
0
3
TT1
0
Bits 0 to 1/Receive Termination Select (RT0 to RT1).
RT1
RT0
0
0
1
1
0
1
0
1
INTERNAL RECEIVE TERMINATION
CONFIGURATION
Internal Receive-Side Termination Disabled
Internal Receive-Side 75Ω Enabled
Internal Receive-Side 100Ω Enabled
Internal Receive-Side 120Ω Enabled
Bits 2 to 3/Transmit Termination Select (TT0 to TT1).
TT1
TT0
0
0
1
1
0
1
0
1
INTERNAL TRANSMIT
TERMINATION CONFIGURATION
Internal Transmit-Side Termination Disabled
Internal Transmit-Side 75Ω Enabled
Internal Transmit-Side 100Ω Enabled
Internal Transmit-Side 120Ω Enabled
Bits 4 and 5/MCLK Prescaler for T1 Mode.
MCLK
(MHz)
1.544
3.088
6.176
12.352
2.048
4.096
8.192
16.384
MPS1
MPS0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
JAMUX
(LIC2.3)
0
0
0
0
1
1
1
1
Bits 4 and 5/MCLK Prescaler for E1 Mode.
MCLK
(MHz)
2.048
4.096
8.192
16.384
MPS1
MPS0
0
0
1
1
0
1
0
1
JAMUX
(LIC2.3)
0
0
0
0
Bit 6/CMI Invert (CMII).
0 = CMI normal at TTIP and RTIP
1 = invert CMI signal at TTIP and RTIP
Bit 7/CMI Enable (CMIE).
0 = disable CMI mode
1 = enable CMI mode
169 of 270
2
TT0
0
1
RT1
0
0
RT0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
INFO2
Information Register 2
11h
Bit #
Name
Default
6
BD
0
7
BSYNC
0
5
TCLE
0
4
TOCD
0
3
RL3
0
2
RL2
0
1
RL1
0
0
RL0
0
Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits.
RL3
RL2
RL1
RL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RECEIVE LEVEL
(dB)
Greater than -2.5
-2.5 to -5.0
-5.0 to -7.5
-7.5 to -10.0
-10.0 to -12.5
-12.5 to -15.0
-15.0 to -17.5
-17.5 to -20.0
-20.0 to -22.5
-22.5 to -25.0
-25.0 to -27.5
-27.5 to -30.0
-30.0 to –32.5
-32.5 to -35.0
-35.0 to -37.5
Less than -37.5
Bit 4/Transmit Open-Circuit Detect (TOCD). A real-time bit set when the device detects that the TTIP and TRING outputs
are open-circuited.
Bit 5/Transmit Current Limit Exceeded (TCLE). A real-time bit set when the 50mA (RMS) current limiter is activated,
whether the current limiter is enabled or not.
Bit 6/BOC Detected (BD). A real-time bit that is set high when the BOC detector is presently seeing a valid sequence and set
low when no BOC is currently being detected.
Bit 7/BERT Real-Time Synchronization Status (BSYNC). Real-time status of the synchronizer (this bit is not latched). Will
be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared when six or more bits out of 64 are
received in error. Refer to BSYNC in the BERT status register, SR9, for an interrupt-generating version of this signal.
170 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ILUT
0
SR1
Status Register 1
16h
6
TIMER
0
5
RSCOS
0
4
JALT
0
3
LRCL
0
2
TCLE
0
1
TOCD
0
0
LOLITC
0
Bit 0/Loss of Line Interface Transmit Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel
time.
Bit 1/Transmit Open-Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are
open-circuited.
Bit 2/Transmit Current Limit Exceeded Condition (TCLE). Set when the 50mA (RMS) current limiter is activated whether
the current limiter is enabled or not.
Bit 3/Line Interface Receive Carrier Loss Condition (LRCL). Set when the carrier signal is lost.
Bit 4/Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its useful
limit. Will be cleared when read. Useful for debugging jitter-attenuation operation.
Bit 5/Receive Signaling Change Of State Event (RSCOS). Set when any channel selected by the receive-signaling changeof-state interrupt-enable registers (RSCSE1 through RSCSE4) changes signaling state.
Bit 6/Timer Event (TIMER). Follows the error counter update interval as determined by the ECUS bit in the Error Counter
Configuration Register (ERCNT).
T1 Mode: Set on increments of one second or 42ms based on RCLK.
E1 Mode: Set on increments of one second or 62.5ms based on RCLK.
Bit 7/Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls below the
threshold set by the value in CCR4.4 through CCR4.7. The level must remain below the programmed threshold for
approximately 50ms for this bit to be set. This is a double interrupt bit (See Section 8.3).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ILUT
0
IMR1
Interrupt Mask Register 1
17h
6
TIMER
0
5
RSCOS
0
4
JALT
0
3
LRCL
0
2
TCLE
0
Bit 0/Loss of Transmit Clock Condition (LOLITC).
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
Bit 1/Transmit Open Circuit Detect Condition (TOCD).
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
Bit 2/Transmit Current Limit Exceeded Condition (TCLE).
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
Bit 3/Line Interface Receive Carrier Loss Condition (LRCL).
0 = interrupt masked
1 = interrupt enabled–generates interrupts on rising and falling edges
Bit 4/Jitter Attenuator Limit Trip Event (JALT).
0 = interrupt masked
1 = interrupt enabled
Bit 5/Receive Signaling Change-of-State Event (RSCOS).
0 = interrupt masked
1 = interrupt enabled
Bit 6/Timer Event (TIMER).
0 = interrupt masked
1 = interrupt enabled
Bit 7/Input Level Under Threshold (ILUT)
0 = interrupt masked
1 = interrupt enabled
172 of 270
1
TOCD
0
0
LOLITC
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
25.8 Recommended Circuits
Figure 25-5. Basic Interface
VDD
DS21455/458
2:1
TTIP
TRANSMIT
LINE
C
DVDD
0.1mF
0.01mF
0.1mF
10mF
+
0.1mF
10mF
DVSS
TRING
TVDD
TVSS
RVDD
1:1
RTIP
+
RVSS
RECEIVE
LINE
RRING
R
R
0.1mF
NOTES:
1) All resistor values are ±1%.
2) Resistors R should be set to 60Ω each if the internal receive-side termination feature is enabled. When
this feature is disabled, R = 37.5Ω for 75Ω coaxial E1 lines, 60Ω for 120Ω twisted pair E1 lines, or
50Ω for 100Ω twisted pair T1 lines.
3) C = 1µF ceramic.
173 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 25-6. Protected Interface Using Internal Receive Termination
VDD
D1
D2
2:1
TRANSMIT
LINE
TTIP
F1
S1
C1
DVDD
0.1mF 0.01mF
DVSS
0.1mF
F2
VDD
DS21455/458
X2
D4
D3
TRING
TVDD
0.1mF
10mF
+
0.1mF
10mF
TVSS
VDD
D5
RVDD
D6
1:1
RECEIVE
LINE
RTIP
S2
F3
0.1mF
D8
F4
RVSS
X1
RRING
D7
60W
60W
0.1mF
NOTES:
1)
2)
3)
4)
5)
6)
All resistor values are ±1%.
X1 and X2 are very low DCR transformers
C1 = 1µF ceramic.
S1 and S2 are 6V transient suppressers.
D1 to D8 are Schottky diodes.
The fuses, F1–F4, are optional to prevent AC power-line crosses from compromising the
transformers.
7) The 68mF is used to keep the local power-plane potential within tolerance during a surge.
174 of 270
+
68mF
+
DS21455/DS21458 Quad T1/E1/J1 Transceivers
25.9 Component Specifications
Table 25-6. TRANSFORMER SPECIFICATIONS
SPECIFICATION
Turns Ratio (3.3V Applications)
Primary Inductance
Leakage Inductance
Intertwining Capacitance
Transmit Transformer DC Resistance
Primary (Device Side)
Secondary
Receive Transformer DC Resistance
Primary (Device Side)
Secondary
RECOMMENDED VALUE
1:1 (receive) and 1:2 (transmit) ±2%
600mH minimum
1.0mH maximum
40pF maximum
1.0Ω maximum
2.0Ω maximum
1.2Ω maximum
1.2Ω maximum
175 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 25-7. E1 Transmit Pulse Template
1.2
1.1
269ns
SCALED AMPLITUDE
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak
in 120 ohm systems, 1.0 on the scale = 3.00Vpeak)
1.0
0.9
0.8
0.7
G.703
Template
194ns
0.6
0.5
219ns
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-250
-200
-150
-100
-50
0
50
100
150
200
250
TIME (ns)
Figure 25-8. T1 Transmit Pulse Template
1.2
1.0
-0.77
-0.39
-0.27
-0.27
-0.12
0.00
0.27
0.35
0.93
1.16
0.9
0.8
0.7
NORMALIZED AMPLITUDE
MINIMUM CURVE
UI
Time Amp.
MAXIMUM CURVE
UI
Time Amp.
1.1
0.6
-500
-255
-175
-175
-75
0
175
225
600
750
0.05
0.05
0.80
1.15
1.15
1.05
1.05
-0.07
0.05
0.05
0.5
-0.77
-0.23
-0.23
-0.15
0.00
0.15
0.23
0.23
0.46
0.66
0.93
1.16
-500
-150
-150
-100
0
100
150
150
300
430
600
750
-0.05
-0.05
0.50
0.95
0.95
0.90
0.50
-0.45
-0.45
-0.20
-0.05
-0.05
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
T1.102/87, T1.403,
CB 119 (Oct. 79), &
I.431 Template
-0.4
-0.5
-500 -400 -300
-200 -100
0
100
200
TIME (ns)
176 of 270
300
400
500
600
700
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 25-9. Jitter Tolerance
UNIT INTERVALS (UIpp)
1K
DS21458 /455
Tolerance
100
TR 62411 (Dec. 90)
10
ITU-T G.823
1
0.1
10
1
100
1K
FREQUENCY (Hz)
10K
100K
Figure 25-10. Jitter Attenuation (T1 Mode)
-20dB
e
rv
Cu
A
TR 62411 (Dec. 90)
Prohibited Area
-40dB
rve
Cu
JITTER ATTENUATION (dB)
0dB
B
DS21458/455
T1 MODE
-60dB
1
10
100
1K
FREQUENCY (Hz)
177 of 270
10K
100K
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 25-11. Jitter Attenuation (E1 Mode)
JITTER ATTENUATION (dB)
0dB
TBR12
Prohibited
Area
ITU G.7XX
Prohibited Area
-20dB
DS21458/455
E1 MODE
-40dB
-60dB
1
10
100
1K
FREQUENCY (Hz)
178 of 270
10K
100K
DS21455/DS21458 Quad T1/E1/J1 Transceivers
26. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND
DETECTION
The DS21455/DS21458 can generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in
length. This function is available only in T1 mode. To transmit a pattern, the user will load the pattern
to be sent into the transmit code definition registers (TCD1 and TCD2) and select the proper length of the
pattern by setting the TC0 and TC1 bits in the in-band code-control (IBCC) register. When generating a
1-, 2-, 4-, 8-, or 16-bit pattern both transmit code-definition registers (TCD1 and TCD2) must be filled
with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires TCD1 to be filled. Once
this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (T1CCR1.0) is
enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the
framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent.
An example: to transmit the standard loop-up code for channel service units (CSUs), which is a repeating
pattern of ...10000100001..., set TCD1 = 80h, IBCC = 0 and T1CCR1.0 = 1.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for loop-up
and loop-down code detection. The user will program the codes to be detected in the receive-up codedefinition (RUPCD1 and RUPCD2) registers and the receive-down code-definition (RDNCD1 and
RDNCD2) registers and the length of each pattern will be selected via the IBCC register. A third detector
(spare) is defined and controlled via the RSCD1/RSCD2 and RSCC registers. Both receive codedefinition registers are used together to form a 16-bit register when detecting a 16-bit pattern. Both
receive code-definition registers will be filled with the same value for 8-bit patterns. Detection of a 1-, 2-,
3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code-definition register to be filled. The
framer will detect repeating pattern codes in both framed and unframed circumstances with bit error rates
as high as 10E-2. The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns.
Writing the least significant byte of the receive code-definition register resets the integration period for
that detector. The code detector has a nominal integration period of 36ms. Hence, after about 36ms of
receiving a valid code, the proper status bit (LUP at SR3.5, LDN at SR3.6, and LSPARE at SR3.7 ) will
be set to a one. Normally codes are sent for a period of five seconds. It is recommended that the software
poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure that the code is
continuously present.
179 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TC1
0
IBCC
In-Band Code Control Register
B6h
6
TC0
0
5
RUP2
0
4
RUP1
0
3
RUP0
0
2
RDN2
0
Bits 0 to 2/Receive-Down Code Length Definition Bits (RDN0 to RDN2).
RDN2
0
0
0
0
1
1
1
1
RDN1
0
0
1
1
0
0
1
1
RDN0
0
1
0
1
0
1
0
1
LENGTH SELECTED (Bits)
1
2
3
4
5
6
7
8/16
Bits 3 to 5/Receive-Up Code Length Definition Bits (RUP0 to RUP2).
RUP2
0
0
0
0
1
1
1
1
RUP1
0
0
1
1
0
0
1
1
RUP0
0
1
0
1
0
1
0
1
LENGTH SELECTED (Bits)
1
2
3
4
5
6
7
8/16
Bits 6 to 7/Transmit Code Length Definition Bits (TC0 to TC1).
TC1
0
0
1
1
TC0
0
1
0
1
LENGTH SELECTED (Bits)
5
6/3
7
16/8/4/2/1
180 of 270
1
RDN1
0
0
RDN0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
TCD1
Transmit Code Definition Register 1
B7h
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bit 0/Transmit Code Definition Bit 0 (C0). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 1/Transmit Code Definition Bit 1 (C1). A “don’t care” if a 5-bit or 6-bit length is selected.
Bit 2/Transmit Code Definition Bit 2 (C2). A “don’t care” if a 5-bit length is selected.
Bit 3/Transmit Code Definition Bit 3 (C3).
Bit 4/Transmit Code Definition Bit 4 (C4).
Bit 5/Transmit Code Definition Bit 5 (C5).
Bit 6/Transmit Code Definition Bit 6 (C6).
Bit 7/Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern.
Register Name:
Register Description:
Register Address:
TCD2
Transmit Code Definition Register 2
B8h
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
Note: Least significant byte of 16-bit codes.
Bit 0/Transmit Code Definition Bit 0 (C0). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 1/Transmit Code Definition Bit 1 (C1). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 2/Transmit Code Definition Bit 2 (C2). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 3/Transmit Code Definition Bit 3 (C3). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 4/Transmit Code Definition Bit 4 (C4). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 5/Transmit Code Definition Bit 5 (C5). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 6/Transmit Code Definition Bit 6 (C6). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
Bit 7/Transmit Code Definition Bit 7 (C7). A “don’t care” if a 5-, 6-, or 7-bit length is selected.
181 of 270
0
C0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
RUPCD1
Receive-Up Code Definition Register 1
B9h
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Note: Writing this register resets the detector’s integration period.
Bit 0/Receive-Up Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 1/Receive-Up Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
Bit 2/Receive-Up Code Definition Bit 2 (C2). A “don’t care” if a 1-bit to 5-bit length is selected.
Bit 3/Receive-Up Code Definition Bit 3 (C3). A “don’t care” if a 1-bit to 4 bit length is selected.
Bit 4/Receive-Up Code Definition Bit 4 (C4). A “don’t care” if a 1-bit to 3-bit length is selected.
Bit 5/Receive-Up Code Definition Bit 5 (C5). A “don’t care” if a 1-bit or 2-bit length is selected.
Bit 6/Receive-Up Code Definition Bit 6 (C6). A “don’t care if a 1-bit length is selected.
Bit 7/Receive-Up Code Definition Bit 7 (C7). First bit of the repeating pattern.
Register Name:
Register Description:
Register Address:
RUPCD2
Receive-Up Code Definition Register 2
Bah
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
Bit 0/Receive-Up Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 1/Receive-Up Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 2/Receive-Up Code Definition Bit 2 (C2). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 3/Receive-Up Code Definition Bit 3 (C3). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 4/Receive-Up Code Definition Bit 4 (C4). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 5/Receive-Up Code Definition Bit 5 (C5). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 6/Receive-Up Code Definition Bit 6 (C6). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 7/Receive-Up Code Definition Bit 7 (C7). A “don’t care” if a 1-bit to 7-bit length is selected.
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0
C0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
RDNCD1
Receive-Down Code Definition Register 1
BBh
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
Note: Writing this register resets the detector’s integration period.
Bit 0/Receive-Down Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 1/Receive-Down Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
Bit 2/Receive-Down Code Definition Bit 2 (C2). A “don’t care” if a 1-bit to 5-bit length is selected.
Bit 3/Receive-Down Code Definition Bit 3 (C3). A “don’t care” if a 1-bit to 4-bit length is selected.
Bit 4/Receive-Down Code Definition Bit 4 (C4). A “don’t care” if a 1-bit to 3-bit length is selected.
Bit 5/Receive-Down Code Definition Bit 5 (C5). A “don’t care” if a 1-bit or 2-bit length is selected.
Bit 6/Receive-Down Code Definition Bit 6 (C6). A “don’t care” if a 1-bit length is selected.
Bit 7/Receive-Down Code Definition Bit 7 (C7). First bit of the repeating pattern.
183 of 270
0
C0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
RDNCD2
Receive-Down Code Definition Register 2
BCh
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bit 0/Receive-Down Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 1/Receive-Down Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 2/Receive-Down Code Definition Bit 2 (C2). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 3/Receive-Down Code Definition Bit 3 (C3). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 4/Receive-Down Code Definition Bit 4 (C4). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 5/Receive-Down Code Definition Bit 5 (C5). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 6/Receive-Down Code Definition Bit 6 (C6). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 7/Receive-Down Code Definition Bit 7 (C7). A “don’t care” if a 1-bit to 7-bit length is selected.
Register Name:
Register Description:
Register Address:
RSCC
In-Band Receive Spare Control Register
BDh
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
—
0
2
RSC2
0
Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2).
RSC2
0
0
0
0
1
1
1
1
RSC1
0
0
1
1
0
0
1
1
RSC0
0
1
0
1
0
1
0
1
LENGTH SELECTED (Bits)
1
2
3
4
5
6
7
8/16
Bit 3/Unused, must be set to zero for proper operation.
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
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1
RSC1
0
0
RSC0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
RSCD1
Receive-Spare Code Definition Register 1
BEh
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Note: Writing this register resets the detector’s integration period.
Bit 0/Receive-Spare Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 1/Receive-Spare Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
Bit 2/Receive-Spare Code Definition Bit 2 (C2). A “don’t care” if a 1-bit to 5-bit length is selected.
Bit 3/Receive-Spare Code Definition Bit 3 (C3). A “don’t care” if a 1-bit to 4-bit length is selected
Bit 4/Receive-Spare Code Definition Bit 4 (C4). A “don’t care” if a 1-bit to 3-bit length is selected.
Bit 5/Receive-Spare Code Definition Bit 5 (C5). A “don’t care” if a 1-bit or 2-bit length is selected.
Bit 6/Receive-Spare Code Definition Bit 6 (C6). A “don’t care” if a 1-bit length is selected.
Bit 7/Receive-Spare Code Definition Bit 7 (C7). First bit of the repeating pattern.
Register Name:
Register Description:
Register Address:
RSCD2
Receive-Spare Code Definition Register 2
BFh
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
Bit 0/Receive-Spare Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 1/Receive-Spare Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 2/Receive-Spare Code Definition Bit 2 (C2). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 3/Receive-Spare Code Definition Bit 3 (C3). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 4/Receive-Spare Code Definition Bit 4 (C4). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 5/Receive-Spare Code Definition Bit 5 (C5). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 6/Receive-Spare Code Definition Bit 6 (C6). A “don’t care” if a 1-bit to 7-bit length is selected.
Bit 7/Receive-Spare Code Definition Bit 7 (C7). A “don’t care” if a 1-bit to 7-bit length is selected.
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0
C0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
27. BERT FUNCTION
The BERT (Bit Error-Rate Tester) block can generate and detect both pseudorandom and repeating-bit
patterns. It is used to test and stress data-communication links.
The BERT block can generate and detect the following patterns:
§
§
§
§
The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words that flip every 1 to 256 words
Daly pattern
The BERT function is assigned on a per-channel basis for both the transmitter and receiver. This is
accomplished by using the special per-channel function. Using this function, the BERT pattern can be
transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive
bandwidth assignments are independent of each other.
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver will report
three events: a change in receive-synchronizer status, a bit error detection, and if either the bit counter or
the error counter overflows. Each of these events can be masked within the BERT function via the BERT
control register 1 (BC1). If the software detects that the BERT has reported an event, then the software
must read the BERT information register (BIR) to determine which event(s) has occurred. To activate the
BERT block, the host must configure the BERT multiplexer via the BIC register.
SR9 contains the status information on the BERT function. The host can be alerted when there is a
change of state of the BERT via this register. A major change of state is defined as either a change in the
receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has
been detected, or an overflow has occurred in either the bit counter or the error counter. The host must
read SR9 to determine the change of state.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
27.1 BERT Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TC
0
BC1
BERT Control Register 1
E0h
6
TINV
0
5
RINV
0
4
PS2
0
3
PS1
0
2
PS0
0
1
LC
0
0
RESYNC
0
Bit 0/Force Resynchronization (RESYNC). A low-to-high transition will force the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire
synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into the registers
BBC1/BBC2/BBC3/BBC4 and BEC1/BEC2/BEC3 and clears the internal count. This bit should be toggled from low to high
whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a subsequent loads.
Bits 2 to 4/Pattern Select Bits (PS0 to PS2)
PS2
0
0
0
PS1
0
0
1
PS0
0
1
0
0
1
1
1
1
0
0
0
1
1
1
0
1
1
1
PATTERN DEFINITION
Pseudorandom 2E7–1
Pseudorandom 2E11–1
Pseudorandom 2E15–1
Pseudorandom Pattern QRSS. A 220 - 1 pattern with 14 consecutive
zero restriction.
Repetitive Pattern
Alternating Word Pattern
Modified 55 Octet (Daly) Pattern The Daly pattern is a repeating 55
octet pattern that is byte-aligned into the active DS0 time slots. The
pattern is defined in an ATIS (Alliance for Telecommunications
Industry Solutions) Committee T1 Technical Report Number 25
(November 1993).
Pseudorandom 2E9 - 1
Bit 5/Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 6/Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Bit 7/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be
generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set
again for a subsequent loads.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EIB2
0
BC2
BERT Control Register 2
E1h
6
EIB1
0
5
EIB0
0
4
SBE
0
3
RPL3
0
2
RPL2
0
1
RPL1
0
0
RPL0
0
Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that
describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive
BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the
length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user
can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).
Length
(Bits)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RPL3
RPL2
RPL1
RPL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit 4/Single Bit Error Insert (SBE). A low-to-high transition will create a single bit error. Must be cleared and set again for a
subsequent bit error to be inserted.
Bits 5 to 7/Error Insert Bits 0 to 2 (EIB0 to EIB2). Will automatically insert bit errors at the prescribed rate into the
generated data pattern. Can be used for verifying error detection features.
EIB2
0
0
0
0
1
1
1
1
EIB1
0
0
1
1
0
0
1
1
EIB0
0
1
0
1
0
1
0
1
ERROR RATE INSERTED
No errors automatically inserted
10E-1
10E-2
10E-3
10E-4
10E-5
10E-6
10E-7
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
BIC
BERT Interface Control Register
EAh
6
RFUS
0
5
—
0
4
TBAT
0
3
TFUS
0
2
—
0
1
BERTDIR
0
0
BERTEN
0
Bit 0/BERT Enable (BERTEN).
0 = BERT disabled
1 = BERT enabled
Bit 1/BERT Direction (BERTDIR).
0 = network: BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and
RRING). The BERT pattern can be looped back to the receiver internally by using the Framer Loopback function.
1 = system: BERT transmits toward the system backplane (RSER) and receives from the system backplane (TSER)
Bit 2/Unused, must be set to zero for proper operation.
Bit 3/Transmit Framed/Unframed Select (TFUS). For T1 mode only.
0 = BERT will not source data into the F-bit position (framed)
1 = BERT will source data into the F-bit position (unframed)
Bit 4/Transmit Byte Align Toggle (TBAT). A zero-to-one transition will force the BERT to byte align its pattern with the
transmit formatter. This bit must be transitioned in order to byte-align the Daly Pattern.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Receive Framed/Unframed Select (RFUS). For T1 mode only.
0 = BERT will not sample data from the F-bit position (framed)
1 = BERT will sample data from the F-bit position (unframed)
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
SR9
Status Register 9
26h
6
BBED
0
5
BBCO
0
4
BEC0
0
3
BRA1
0
2
BRA0
0
1
BRLOS
0
0
BSYNC
0
Bit 0/BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32 consecutive bit
positions. Refer to BSYNC in INFO2 register for a real-time version of this bit.
Bit 1/BERT Receive Loss Of Synchronization Condition (BRLOS). A latched bit that is set whenever the receive BERT
begins searching for a pattern. The BERT will lose sync after receiving six errored bits out of 63 bits. Synchronization is lost
when six errors are received in 63 bits. Once synchronization is achieved, this bit will remain set until read.
Bit 2/BERT Receive All Zeros Condition (BRA0). A latched bit that is set when 32 consecutive zeros are received. Allowed
to be cleared once a one is received.
Bit 3/BERT Receive All Ones Condition (BRA1). A latched bit that is set when 32 consecutive ones are received. Allowed
to be cleared once a zero is received.
Bit 4/BERT Error Counter Overflow (BECO) Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows. Cleared when read and will not be set again until another overflow occurs.
Bit 5/BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC)
overflows. Cleared when read and will not be set again until another overflow occurs.
Bit 6/BERT Bit Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it detect bit errors. Cleared when read.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
IMR9
Interrupt Mask Register 9
27h
6
BBED
0
5
BBCO
0
4
BEC0
0
3
BRA1
0
2
BRA0
0
1
BRLOS
0
0
BSYNC
0
Bit 0/BERT in Synchronization Condition (BSYNC).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
Bit 1/Receive Loss Of Synchronization Condition (BRLOS).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
Bit 2/Receive All Zeros Condition (BRA0).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
Bit 3/Receive All Ones Condition (BRA1).
0 = interrupt masked
1 = interrupt enabled–interrupts on rising and falling edges
Bit 4/BERT Error Counter Overflow Event (BECO).
0 = interrupt masked
1 = interrupt enabled
Bit 5/BERT Bit Counter Overflow Event (BBCO).
0 = interrupt masked
1 = interrupt enabled
Bit 6/Bit Error Detected Event (BBED).
0 = interrupt masked
1 = interrupt enabled
BERT Alternating Word Count Rate. When the BERT is programmed in the alternating word mode, the words will repeat
for the count loaded into this register then flip to the other word and again repeat for the number of times loaded into this
register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ACNT7
0
BAWC
BERT Alternating Word Count Rate
DBh
6
ACNT6
0
5
ACNT5
0
4
ACNT4
0
3
ACNT3
0
2
ACNT2
0
1
ACNT1
0
0
ACNT0
0
Bits 0 to 7/Alternating Word Count Rate Bits 0 to 7 (ACNT0 to ACNT7). ACNT0 is the LSB of the 8-bit alternating word
count rate counter.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
27.2 BERT Repetitive Pattern Set
These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern,
a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is less
than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For
example, if the pattern was the repeating 5-bit pattern …01101… (where the right-most bit is the one sent
first and received first) then BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and
BRP4 should be loaded with 5Ah. For a pseudorandom pattern, all four registers should be loaded with
all ones (i.e., FFh). For an alternating word pattern, one word should be placed into BRP1 and BRP2 and
the other word should be placed into BRP3 and BRP4. For example, if the DDS stress pattern “7E” is to
be described, the user would place 00h in BRP1, 00h in BRP2, 7Eh in BRP3, and 7Eh in BRP4, and the
alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of
7Eh to be sent and received.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPAT7
0
BRP1
BERT Repetitive Pattern Set Register 1
DCh
6
RPAT6
0
5
RPAT5
0
4
RPAT4
0
3
RPAT3
0
2
RPAT2
0
1
RPAT1
0
0
RPAT0
0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 0 to 7 (RPAT0 to RPAT7). RPAT0 is the LSB of the 32-bit repetitive pattern
set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPAT15
0
BRP2
BERT Repetitive Pattern Set Register 2
DDh
6
RPAT14
0
5
RPAT13
0
4
RPAT12
0
3
RPAT11
0
2
RPAT10
0
1
RPAT9
0
0
RPAT8
0
1
RPAT17
0
0
RPAT16
0
1
RPAT25
0
0
RPAT24
0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 8 to 15 (RPAT8 to RPAT15).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPAT23
0
BRP3
BERT Repetitive Pattern Set Register 3
DEh
6
RPAT22
0
5
RPAT21
0
4
RPAT20
0
3
RPAT19
0
2
RPAT18
0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 16 to 23 (RPAT16 to RPAT23).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPAT31
0
BRP4
BERT Repetitive Pattern Set Register 4
DFh
6
RPAT30
0
5
RPAT29
0
4
RPAT28
0
3
RPAT27
0
2
RPAT26
0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 24 to 31 (RPAT24 to RPAT31). RPAT31 is the LSB of the 32-bit repetitive
pattern set.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
27.3 BERT Bit Counter
Once the BERT has achieved synchronization, this 32-bit counter will increment for each data bit (i.e.,
clock) received. Toggling the LC control bit in BC1 can clear this counter, which saturates when full and
will set the BBCO status bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BBC7
0
BBC1
BERT Bit Count Register 1
E3h
6
BBC6
0
5
BBC5
0
4
BBC4
0
3
BBC3
0
2
BBC2
0
1
BBC1
0
0
BBC0
0
Bits 0 to 7/BERT Bit Counter Bits 0 to 7 (BBC0 to BBC7). BBC0 is the LSB of the 32-bit counter.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BBC15
0
BBC2
BERT Bit Count Register 2
E4h
6
BBC14
0
5
BBC13
0
4
BBC12
0
3
BBC11
0
2
BBC10
0
1
BBC9
0
0
BBC8
0
2
BBC18
0
1
BBC17
0
0
BBC16
0
2
BBC26
0
1
BBC25
0
0
BBC24
0
Bits 0 to 7/BERT Bit Counter Bits 8 to 15 (BBC8 to BBC15).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BBC23
0
BBC3
BERT Bit Count Register 3
E5h
6
BBC22
0
5
BBC21
0
4
BBC20
0
3
BBC19
0
Bits 0 to 7/BERT Bit Counter Bits 16 to 23 (BBC16 to BBC23).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BBC31
0
BBC4
BERT Bit Count Register 4
E6h
6
BBC30
0
5
BBC29
0
4
BBC28
0
3
BBC27
0
Bits 0 to 7/BERT Bit Counter Bits 24 to 31 (BBC24 to BBC31). BBC31 is the MSB of the 32-bit counter.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
27.4 BERT Error Counter
Once the BERT has achieved synchronization, this 24-bit counter will increment for each data bit
received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when
full and will set the BECO status bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EC7
0
BEC1
BERT Error Count Register 1
E7h
6
EC6
0
5
EC5
0
4
EC4
0
3
EC3
0
2
EC2
0
1
EC1
0
0
EC0
0
Bits 0 to 7/Error Counter Bits 0 to 7 (EC0 to EC7). EC0 is the LSB of the 24-bit counter.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EC15
0
BEC2
BERT Error Count Register 2
E8h
6
EC14
0
5
EC13
0
4
EC12
0
3
EC11
0
2
EC10
0
1
EC9
0
0
EC8
0
3
EC19
0
2
EC18
0
1
EC17
0
0
EC16
0
Bits 0 to 7/Error Counter Bits 8 to 15 (EC8 to EC15).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EC23
0
BEC3
BERT Error Count Register 3
E9h
6
EC22
0
5
EC21
0
4
EC20
0
Bits 0 to 7/Error Counter Bits 16 to 23 (EC16 to EC23). EC23 is the MSB of the 24-bit counter.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
28. PAYLOAD ERROR INSERTION FUNCTION
An error-insertion function is available in the DS21455/DS21458 and is used to create errors in the
payload portion of the T1 frame in the transmit path. Errors can be inserted over the entire frame or on a
per-channel basis. The user can select all DS0s or any combination of DS0s. See the Special Per-Channel
Registration Operation section for information on using the per-channel function. Errors are created by
inverting the last bit in the count sequence. For example, if the error rate 1 in 16 is selected, the 16th bit is
inverted. F-bits are excluded from the count and are never corrupted. Error-rate changes occur on frame
boundaries. Error-insertion options include continuous and absolute number with both options supporting
selectable-insertion rates.
Table 28-1. TRANSMIT ERROR INSERTION SETUP SEQUENCE
STEP
1
2A
or
2B
ACTION
Enter desired error rate in the ERC register. Note: If ER3 through ER0 = 0,
no errors will be generated even if the constant error insertion feature is
enabled.
For constant error insertion set CE = 1 (ERC.4).
For a defined number of errors:
- Set CE = 0 (ERC.4)
- Load NOE1 and NOE2 with the number of errors to be inserted
- Toggle WNOE (ERC.7) from 0 to 1, to begin error insertion
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
ERC
Error Rate Control Register
EBh
Bit #
Name
Default
6
—
0
7
WNOE
0
5
—
0
4
CE
0
3
ER3
0
2
ER2
0
1
ER1
0
0
ER0
0
Bits 0 to 3/Error Insertion Rate Select Bits (ER0 to ER3).
ER3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ER2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ER1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ER0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ERROR RATE
No errors inserted
1 in 16
1 in 32
1 in 64
1 in 128
1 in 256
1 in 512
1 in 1024
1 in 2048
1 in 4096
1 in 8192
1 in 16,384
1 in 32,768
1 in 65,536
1 in 131,072
1 in 262,144
Bit 4/Constant Errors (CE). When this bit is set high (and the ER0 to ER3 bits are not set to 0000), the error insertion logic
will ignore the number of error registers (NOE1, NOE2) and generate errors constantly at the selected insertion rate. When CE
is set to zero, the NOEx registers determine how many errors are to be inserted.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Write NOE Registers (WNOE). If the host wishes to update to the NOEx registers, this bit must be toggled from a zero
to a one after the host has already loaded the prescribed error count into the NOEx registers. The toggling of this bit causes the
error count loaded into the NOEx registers to be loaded into the error insertion circuitry on the next clock cycle. Subsequent
updates require that the WNOE bit be set to zero and then one once again.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
28.1 Number of Error Registers
The number of error registers determines how many errors will be generated. Up to 1023 errors can be
generated. The host will load the number of errors to be generated into the NOE1 and NOE2 registers.
The host can also update the number of errors to be created by first loading the prescribed value into the
NOE registers and then toggling the WNOE bit in the error rate control registers.
Table 28-2. ERROR INSERTION EXAMPLES
VALUE
000h
001h
002h
3FFh
WRITE
Do not create any errors
Create a single error
Create two errors
Create 1023 errors
Register Name:
Register Description:
Register Address:
NOE1
Number Of Errors 1
ECh
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
READ
No errors left to be inserted
One error left to be inserted
Two errors left to be inserted
1023 errors left to be inserted
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bits 0 to 7/Number of Errors Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter.
Register Name:
Register Description:
Register Address:
NOE2
Number Of Errors 2
EDh
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
C9
0
0
C8
0
Bits 0 to 1/Number of Errors Counter Bits 8 to 9 (C8 to C9). Bit C9 is the MSB of the 10-bit counter.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
28.1.1 Number of Errors Left Register
The host can read the NOELx registers at any time to determine how many errors are left to be inserted.
Register Name:
Register Description:
Register Address:
NOEL1
Number of Errors Left 1
EEh
Bit #
Name
Default
6
C6
0
7
C7
0
5
C5
0
4
C4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Bits 0 to 7/Number of Errors Left Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter.
Register Name:
Register Description:
Register Address:
NOEL2
Number Of Errors Left 2
EFh
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
C9
0
0
C8
0
Bits 0 to 1/Number of Errors Left Counter Bits 8 to 9 (C8 to C9). Bit C9 is the MSB of the 10-bit counter.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
29. INTERLEAVED PCM BUS OPERATION
In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses
to simplify transport across the system backplane. The DS21455/DS21458 can be configured to allow
PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space
and cost. The DS21455/DS21458 can be configured for channel or frame interleave.
The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096MHz bus speed allows two
PCM data streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to
share a common bus. The 16.384MHz bus speed allows eight PCM data streams to share a common bus.
See Figure 30-1 for an example of four transceivers sharing a common 8.192MHz PCM bus. The receive
elastic stores of each transceiver must be enabled. Via the IBO register the user can configure each
transceiver for a specific bus position. For all IBO bus configurations each transceiver is assigned an
exclusive position in the high-speed PCM bus. The 8kHz frame sync can be generated from the system
backplane or from the first device on the bus. All other devices on the bus must have their frame syncs
configured as inputs. Relative to this common frame sync, the devices will await their turn to drive or
sample the bus according to the settings of the DA0, DA1, and DA2 bits of the IBOC register.
29.1 Channel Interleave Mode
In channel interleave mode, data is output to the PCM data-out bus one channel at a time from each of the
connected devices until all channels of frame n from each device has been placed on the bus. This mode
can be used even when the DS21455/DS21458s are operating asynchronous to each other. The elastic
stores will manage slip conditions.
29.2 Frame Interleave Mode
In frame interleave mode, data is output to the PCM data-out bus one frame at a time from each of the
devices. This mode is used only when all connected devices are operating in a synchronous fashion (all
inbound T1 or E1 lines are synchronous) and are synchronous with the system clock (system clock
derived from T1 or E1 line). In this mode, slip conditions are not allowed.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
IBOC
Interleave Bus Operation Control Register
C5h
7
—
0
6
IBS1
0
5
IBS0
0
4
IBOSEL
0
3
IBOEN
0
2
DA2
0
1
DA1
0
0
DA0
0
Bits 0 to 2/Device Assignment bits (DA0 to DA2).
DA2
DA1
DA0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DEVICE
POSITION
1st device on bus
2nd device on bus
3rd device on bus
4th device on bus
5th device on bus
6th device on bus
7th device on bus
8th device on bus
Bit 3/Interleave Bus Operation Enable (IBOEN).
0 = Interleave Bus Operation disabled
1 = Interleave Bus Operation enabled
Bit 4/Interleave Bus Operation Select (IBOSEL). This bit selects channel- or frame-interleave mode.
0 = Channel Interleave
1 = Frame Interleave
Bits 5 to 6/IBO Bus Size bit 1 (IBS0 to IBS1). Indicates how many devices on the bus.
IBS1
0
0
1
1
IBS0
0
1
0
1
BUS SIZE
Two Devices on Bus
Four Devices on Bus
Eight Devices on Bus
Reserved for Future Use
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 29-1. IBO Example
DS21455 or DS21458
RSYSCLK1
TSYSCLK1
RSYNC1
TSSYNC1
RSIG1
TSIG1
SCT #1
TSER1
RSER1
8.192MHz System Clock In
RSYSCLK2
TSYSCLK2
RSYNC2
TSSYNC2
RSIG2
System 8kHz Frame Sync In
PCM Signaling Out
PCM Signaling In
TSIG2
SCT #2
TSER2
PCM Data In
RSER2
PCM Data Out
RSYSCLK3
TSYSCLK3
RSYNC3
TSSYNC3
RSIG3
TSIG3
SCT #3
TSER3
RSER3
RSYSCLK4
TSYSCLK4
RSYNC4
TSSYNC4
RSIG4
TSIG4
SCT #4
TSER4
RSER4
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
30. EXTENDED SYSTEM INFORMATION BUS (ESIB)
The ESIB function is carried forward from the previous generation of single port transceiver devices such
as the DS2155 and DS2156. This function allows the host to read interrupt and alarm status of multiple
ports, up to 8, with a single read of any one of the devices in the ESIB group. Each device is programmed
to drive a single bit on the CPU bus (leaving the other bits in high-Z) when one of the four ESIB registers
(ESIB1–ESIB4) is accessed on any device in the group. Three signals were used to allow the separate
devices to communicate with each other in order to respond to an ESIB register access on any device in
the group. These signals are ESIBS0, ESIBS1, and ESIBRD. Since the DS21458 and DS21455 are quad
monolithic devices, the ESIB function can be used to arrange two devices (eight transceivers) in an ESIB
group. Primarily, this is used to quickly sort out interrupts since the host can determine which port or
ports are causing and interrupt with a single CPU read cycle. The user can also read various alarm
indicators on all members. There are two control registers, ESIBCR1 and ESIBCR2, and four information
registers, ESIB1, ESIB2, ESIB3, and ESIB4, in each transceiver. Reading register ESIB1 of any member
of the group, the host can read the interrupt status on all members. Via ESIB2 the host can gather
synchronization status on all members of the group. ESIB3 and ESIB4 can be programmed to report
various alarms on a device-by-device basis.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 30-1. DS21455 ESIB Group
DS21455 #2
DS21455 #1
PORT # 1
PORT #5
ESIBS0_1
ESIBS0_1
ESIBS1_1
ESIBS1_1
ESIBRD_1
ESIBRD_1
PORT # 6
PORT # 2
ESIBS0_2
ESIBS0_2
ESIBS1_2
ESIBS1_2
ESIBRD_2
ESIBRD_2
PORT # 7
PORT # 3
ESIBS0_3
ESIBS0_3
ESIBS1_3
ESIBS1_3
ESIBRD_3
ESIBRD_3
PORT # 8
PORT # 4
ESIBS0_4
ESIBS0_4
ESIBS1_4
ESIBS1_4
ESIBRD_4
ESIBRD_4
CPU I/F
CPU I/F
NOTE: UP TO 8 PORTS (TWO DS21455s) CAN BE ARRANGED INTO AN ESIB GROUP. ON THE DS21455, ESIB
SIGNALS ARE BROUGHT OUT FOR EACH TRANSCEIVER.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 30-2. DS21458 ESIB Group
DS21458 #1
DS21458 #2
PORT # 1
PORT # 5
ESIBS0
ESIBS1
ESIBRD
PORT # 2
PORT #6
PORT # 3
PORT # 7
PORT # 4
PORT # 8
CPU I/F
CPU I/F
NOTE: UP TO 8 PORTS (TWO DS21458s) CAN BE ARRANGED INTO AN ESIB GROUP. ON THE DS21458, THE ESIB
IS INTERNALLY CONNECTED FOR EACH OF THE FOUR TRANSCEIVERS.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
ESIBCR1
Extended System Information Bus Control Register 1
B0h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
ESIBSEL2
0
2
ESIBSEL1
0
1
ESIBSEL0
0
0
ESIEN
0
Bit 0/Extended System Information Bus Enable (ESIEN).
0 = disabled
1 = enabled
Bits 1 to 3/Output Data Bus Line Select (ESIBSEL0 to ESIBSEL2). These bits tell the device which data bus bit to output
the ESIB data on when one of the ESIB information registers is accessed. Each member of the ESIB group must have a unique
bit selected.
ESIBSEL2
0
0
0
0
1
1
1
1
ESIBSEL1
0
0
1
1
0
0
1
1
ESIBSEL0
0
1
0
1
0
1
0
1
BUS BIT DRIVEN
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
ESIBCR2
Extended System Information Bus Control Register 2
B1h
7
—
0
6
ESI4SEL2
0
5
ESI4SEL1
0
4
ESI4SEL0
0
3
—
0
2
ESI3SEL2
0
1
ESI3SEL1
0
0
ESI3SEL0
0
Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be output when
the device decodes an ESI3 address during a bus read operation.
ESI3SEL2
ESI3SEL1
ESI3SEL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
STATUS OUTPUT
T1 MODE
E1 MODE
RBL
RUA1
RYEL
RRA
LUP
RDMA
LDN
V52LNK
SIGCHG
SIGCHG
ESSLIP
ESSLIP
—
—
—
—
Bit 3/Unused, must be set to zero for proper operation.
Bits 4 to 6/Address ESI4 Data Output Select (ESI4SEL0 to ESI4SEL2). These bits select what status is to be output when
the device decodes an ESI4 address during a bus-read operation.
ESI4SEL2
ESI4SEL1
ESI4SEL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
STATUS OUTPUT
T1 MODE
E1 MODE
RBL
RUA1
RYEL
RRA
LUP
RDMA
LDN
V52LNK
SIGCHG
SIGCHG
ESSLIP
ESSLIP
—
—
—
—
Bit 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
ESIB1
Extended System Information Bus Register 1
B2h
Bit #
Name
Default
6
DISn
0
7
DISn
0
5
DISn
0
4
DISn
0
3
DISn
0
2
DISn
0
1
DISn
0
0
DISn
0
Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to output their interrupt status
on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
DRLOSn
0
ESIB2
Extended System Information Bus Register 2
B3h
6
DRLOSn
0
5
DRLOSn
0
4
DRLOSn
0
3
DRLOSn
0
2
DRLOSn
0
1
DRLOSn
0
0
DRLOSn
0
Bits 0 to 7/Device Receive Loss of Sync (DRLOSn). Causes all devices participating in the ESIB group to output their frame
synchronization status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
UST1n
0
ESIB3
Extended System Information Bus Register 3
B4h
6
UST1n
0
5
UST1n
0
4
UST1n
0
3
UST1n
0
2
UST1n
0
1
UST1n
0
0
UST1n
0
Bits 0 to 7/User-Selected Status 1 (UST1n). Causes all devices participating in the ESIB group to output status or alarms as
selected by the ESI3SEL0 to ESI3SEL2 bits in the ESIBCR2 configuration register on the appropriate data bus line selected by
the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
UST2n
0
ESIB4
Extended System Information Bus Register 4
B5h
6
UST2n
0
5
UST2n
0
4
UST2n
0
3
UST2n
0
2
UST2n
0
1
UST2n
0
0
UST2n
0
Bits 0 to 7/User-Selected Status 2 (UST2n). Causes all devices participating in the ESIB group to output status or alarms as
selected by the ESI4SEL0 to ESI4SEL2 bits in the ESIBCR2 configuration register on the appropriate data bus line selected by
the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
31. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER
The DS21455/DS21458 contain an on-chip clock synthesizer that generates a user-selectable clock
referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate
low-jitter clocks. Common applications include generation of port and backplane system clocks.
Register Name:
Register Description:
Register Address:
CCR2
Common Control Register 2
71h
Bit #
Name
Default
6
—
0
7
—
0
5
—
0
4
—
0
3
—
0
Bit 0/Backplane Clock Enable (BPEN).
0 = disable BPCLK pin (Pin held at logic 0)
1 = enable BPCLK pin
Bits 1 to 2/Backplane Clock Selects (BPCS0, BPCS1).
BPCS1
0
0
1
1
BPCS0
0
1
0
1
BPCLK FREQUENCY (MHz)
16.384
8.192
4.096
2.048
Bit 3/Unused, must be set to zero for proper operation.
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
208 of 270
2
BPCS1
0
1
BPCS0
0
0
BPEN
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
32. FRACTIONAL T1/E1 SUPPORT
The DS21455/DS21458 can be programmed to output gapped clocks for selected channels in the receive
and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or
ISDN-PRI applications. This is accomplished by assigning an alternate function to the RCHCLK and
TCHCLK pins. When the gapped clock feature is enabled, a gated clock is output on the RCHCLK and/or
TCHCLK pins. The channel selection is controlled via the special per-channel control registers. No clock
is generated at the F-bit position. The receive and transmit paths have independent enables. Channel
formats supported include 56kbps and 64kbps.
When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted.
Only the seven most significant bits of the channel have clocks.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
CCR3
Common Control Register 3
72h
6
—
0
5
—
0
4
—
0
3
TDATFMT
0
Bit 0/Receive Gapped-Clock Enable (RGPCKEN).
0 = RCHCLK functions normally
1 = enable gapped-bit clock output on RCHCLK
Bit 1/Receive Channel-Data Format (RDATFMT).
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in 7 out of the 8 bits)
Bit 2/Transmit Gapped-Clock Enable (TGPCKEN).
0 = TCHCLK functions normally
1 = enable gapped-bit clock output on TCHCLK
Bit 3/Transmit Channel-Data Format (TDATFMT).
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in 7 out of the 8 bits)
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
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2
TGPCKEN
0
1
RDATFMT
0
0
RGPCKEN
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
33. USER-PROGRAMMABLE OUTPUT PINS
The DS21455/DS21458 provide four user-programmable output pins. The pins are automatically cleared
to zero at power-up or as a reset of a hardware- or software-issued reset.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
CCR4
Common Control Register 4
73h
7
RLT3
0
6
RLT2
0
5
RLT1
0
4
RLT0
0
3
UOP3
0
Bit 0/User-Defined Output 0 (UOP0).
0 = logic 0 level at pin
1 = logic 1 level at pin
Bit 1/User-Defined Output 1 (UOP1).
0 = logic 0 level at pin
1 = logic 1 level at pin
Bit 2/User-Defined Output 2 (UOP2).
0 = logic 0 level at pin
1 = logic 1 level at pin
Bit 3/User-Defined Output 3 (UOP3).
0 = logic 0 level at pin
1 = logic 1 level at pin
Bits 4 to 7/Receive Level Threshold Bits (RLT0 to RLT3).
RLT3
RLT2
RLT1
RLT0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Receive Level
(dB)
Greater than -2.5
-2.5
-5.0
-7.5
-10.0
-12.5
-15.0
-17.5
-20.0
-22.5
-25.0
-27.5
-30.0
-32.5
-35.0
Less than -37.5
210 of 270
2
UOP2
0
1
UOP1
0
0
UOP0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
34. TRANSMIT FLOW DIAGRAMS
Figure 34-1. T1 Transmit Data Flow
TSIG
TSER
T1 TRANSMIT
FLOW
DIAGRAM
Hardware
Signaling
HSIE1-3
through
PCPR
TX
ESTORE
KEY
- PIN
Estore Mux
ESCR.4 TESE
- SELECTOR
RDATA
From
T1_rcv_logic
LBCR1.1 PLB
Payload
Loopback
HDLC
Engine
#1
TLINK
H1TC.4
THMS1
HDLC FDL #1
HDLC Mux #1
HDLC
Engine
#2
H2TC.4
THMS2
THMS1 H1TC.4
H1TCS1-3
H1TTSBS
THMS2 H2TC.4
H2TCS1-3
HDLC Mux #2
HDLC FDL #2
TFDL
T1TCR2.5
TZSE
- REGISTER
H2TTSBS
Idle
Code
Array
Tx FDL
Zero
Stuffer
TCICE1-3
Idle Code Mux
T1TCR1.2
TFDLS
FDL Mux
TFDL
Loop
Code
Gen
BOC
Engine
BOCC.0 SBOC
Loop Code
BOC Mux
T1CCR1.2 TFM
T1TCR2.2 TD4YM
T1TCR1.0 TYEL
D4 12th Fs
Yellow
alarm
ESF Yellow
Alarm
FPS or
Ft/Fs
insertion
Per-Channel
Loopback
To ESF Yellow
Mux
211 of 270
PCLR1-3
Software
Sig
Registers
Software Sig
F-bit Mux
To FDL Mux
TLOOP T1CCR1.0
To FDL Mux
SSIE1-3
TFPT T1TCR1.5
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 34-2. T1 Transmit Data Flow (continued)
From ESF
Yellow Alarm
From BOC Mux
From F-bit Mux
TFPT T1TCR1.5
FDL Mux
TFM T1CCR1.2
ESF Yellow
TYEL T1TCR1.0
CRC Mux
TCPT T1TCR1.5
D4 bit 2
Yellow
Alm
BERT
Engine
TFM T1CCR1.2
TD4YM T1TCR2.2
TYEL T1TCR1.0
TFUS BIC.3
F-bit
BERT Mux
T1TCR2.3 FBCT1
T1TCR2.4 FBCT2
F-bit
Corruption
BTCS1-3
Payload
error
insertion
NOEL != 0
ERC.4 CE
BERTEN
BIC.0
PEICS1-3
SSIE1-3
Bit 7
stuffing
T1CCR1.1 PDE
GB7S T1TCR1.3
B7SE T1TCR2.0
Pulse
Density
Enforcer
TPDV INFO1.6
DS0
Monitor
CRC
Calculation
B8ZS
Encoding
T1TCR2.7 B8ZSE
T1TCR1.1 TBL
Blue
Alarm
IOCR1.0 ODF
Bipolar/
NRZ
coding
1/2 CLK/
FULL CLK
CCR1.4 ODM
TPOS
from PCPR
TNEG
212 of 270
TCM0-4 TDS0SEL.0 - .3
TDSOM
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 34-3. E1 Transmit Data Flow
TSER
HSIE1-4
through
PCPR
E1 TRANSMIT
FLOW
DIAGRAM
TSIG
Hardware
Signaling
tx_hsig_buf
KEY
TX
ESTORE
- PIN
ESCR.4 TESE
Estore Mux
- SELECTOR
RDATA
From
E1_rcv_logic
LBCR1.1 PLB
Payload
Loopback Mux
- REGISTER
HDLC
Engine
#1
THMS1 H1TC.4
HDLC DS0
Mux #1
H1TCS1-4
H1TTSBS
THMS1 H1TC.4
HDLC Sa-bit
Mux #1
T1SaBE4T1SaBE8
H1TTSBS.4 - H1TTSBS.0
HDLC
Engine #2
THMS2 H2TC.4
H2TCS1-4
H2TTSBS
HDLC DS0
Mux #2
THMS2 H2TC.4
HDLC Sa-bit
Mux #2
T2SaBE4-T2SaBE8
H2TTSBS.4 H2TTSBS.0
BERT
Engine
BERTEN (BIC.0)
BERT Mux
BTCS1-4
Idle Code
Array
Idle Code MUX
TCICE1-4
To Per-Channel Mux
213 of 270
from PCPR
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 34-4. E1 Transmit Data Flow (continued)
From Idle
Code Mux
RDATA
From E1_rcv_logic
Per-Channel
Loopback
E1 TRANSMIT
FLOW
DIAGRAM
PCLR1-4
TNAF
THMS1
Sa-bit Mux
THMS2 H2TC.4
TAF/TNAF(non Sa)
TS0 Mux
E1TCR1.4 TSIS
H1TC.4
TFPT E1TCR1.7
Si-bit Mux
Si = CRC4 MF Align Word
(Does not overwrite E-bits)
E1TCR1.0 TCRC4
E1TCR2.2 AEBE
Sa4S - Sa8S
E1TCR2.5 - E1TCR2.7
E1TCR2.8 ARA
TSaCR
Si/CRC4 Mux
TLINK
Auto Ebit Gen
TLINK Mux
TSiAF
TSiNAF
TRA
TSa4
Auto
RA Gen
TSa5
TSa6
TSa7
TSa8
TSaCR Mux
TSA1 E1TCR1.3
SSIE1-4
E1TCR1.0 T16S
Software Sig
E1TCR1.0 TCRC4
CRC
Calculate
CCR1.6 CRC4R
CRC Recalculate
E1TCR2.1 AAIS
Auto
AIS
Gen
E1TCR1.5 TUA1
UA1
Gen
E1TCR1.2 THDB3
TS1-16
TDS0SEL.0 - TDS0SEL.4
TCM0-TCM4
DS0
Monitor
HDB3
Encoding
To Bipolar/NRZ
coding Mux
214 of 270
TDSOM
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 34-5. E1 Transmit Data Flow (continued)
From HDB3
Encoding Mux
IOCR1.0 ODF
Bipolar/
NRZ
coding
E1 TRANSMIT
FLOW
DIAGRAM
FLB LBCR1.0
FLB
Select
RPOS
TO RECEIVER
RNEG
RLB Mux
RLB Mux
RLB
LBCR1.2
1/2 CLK/
FULL CLK
CCR1.4 ODM
TPOS
TNEG
215 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT
The DS21455/DS21458 IEEE 1149.1 design supports the standard instruction codes
SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z,
CLAMP, and IDCODE. The DS21455/DS21458 contain the following as required by IEEE 1149.1
Standard Test-Access Port and Boundary-Scan Architecture:
§
§
§
§
§
§
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 35-1. JTAG Functional Block Diagram
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
BYPASS
REGISTER
MUX
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
VDD
10kW
VDD
10kW
JTDI
SELECT
OUTPUT ENABLE
VDD
10kW
JTMS
JTCLK
JTRST
216 of 270
JTDO
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK (Figure 35-2).
Test-Logic-Reset
Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will
contain the IDCODE instruction. All system logic of the device will operate normally.
Run-Test-Idle
The run-test-idle is used between scan operations or during specific tests. The instruction register and test
registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge
on JTCLK moves the controller to the select-IR-scan state.
Capture-DR
Data can be parallel-loaded into the test-data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the shiftDR state if JTMS is LOW or it will go to the exit1-DR state if JTMS is HIGH.
Shift-DR
The test-data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected
by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the update-DR state, which
terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put
the controller in the pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A
rising edge on JTCLK with JTMS HIGH will put the controller in the exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the shiftDR state.
Update-DR
A falling edge on JTCLK while in the update-DR state will latch the data from the shift register path of
the test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register.
217 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this
state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will
initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the
controller back into the test-logic-reset state.
Capture-IR
The capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the
controller will enter the exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will
enter the shift-IR state.
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel register as well as
all test registers remain at their previous states. A rising edge on JTCLK with JTMS HIGH will move the
controller to the exit1-IR state. A rising edge on JTCLK with JTMS LOW will keep the controller in the
shift-IR state while moving data one stage thorough the instruction shift register.
Exit1-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the pause-IR state. If JTMS is HIGH
on the rising edge of JTCLK, the controller will enter the update-IR state and terminate the scanning
process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK
will put the controller in the exit2-IR state. The controller will remain in the pause-IR state if JTMS is
LOW during a rising edge on JTCLK.
Exit2-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the update-IR state. The controller
will loop back to shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.
Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the
falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the
current instruction. A rising edge on JTCLK with JTMS LOW, will put the controller in the run-test-idle
state. With JTMS HIGH, the controller will enter the select-DR-scan state.
218 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 35-2. TAP Controller State Diagram
1
Test Logic
Reset
0
0
Run Test/
Idle
1
Select
DR-Scan
1
Select
IR-Scan
0
1
0
1
Capture DR
Capture IR
0
Shift DR
0
Shift IR
0
1
Exit IR
Pause IR
0
1
0
1
0
0
Pause DR
0
1
1
Exit DR
1
Exit2 DR
1
0
Exit2 IR
1
1
Update DR
Update IR
1
1
0
219 of 270
0
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
35.1 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data
one stage towards the serial output at JTDO. A rising edge on JTCLK in the exit1-IR state or the exit2-IR
state with JTMS HIGH will move the controller to the update-IR state. The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS21455/DS21458 and their respective operational binary codes are shown in
Table 35-1.
Table 35-1. INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGH-Z
IDCODE
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
010
111
000
011
100
001
220 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital
I/Os of the device can be sampled at the boundary scan register without interfering with the normal
operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to
shift data into the boundary scan register via JTDI using the shift-DR state.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting
the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
HIGH-Z
All digital outputs of the device will be placed in a high-impedance state. The BYPASS register will be
connected between JTDI and JTDO.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code will be loaded into the identification register on the
rising edge of JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During test-logic-reset, the identification code is forced into the
instruction register’s parallel output. The ID code will always have a 1 in the LSB position. The next 11
bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for
the device and 4 bits for the version (Table 35-2). Table 35-3 lists the device ID codes for the DS21455
and DS21458.
Table 35-2. ID CODE STRUCTURE
MSB
Version
Contact Factory
4 bits
LSB
Device ID
JEDEC
1
16 bits
00010100001
1
Table 35-3. DEVICE ID CODES
DEVICE
DS21455
DS21458
16-BIT ID
0021h
0022h
221 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
35.2 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register.
An optional test register has been included with the DS21455/DS21458 design. This test register is the
identification register and is used with the IDCODE instruction and the test-logic-reset state of the TAP
controller.
35.3 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See Table 35-4 for the cell bit locations and definitions.
35.4 Bypass Register
This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGH-Z instructions that
provides a short path between JTDI and JTDO.
35.5 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state.
See Table 35-2 and Table 35-3 for more information about bit usage.
222 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Table 35-4. BOUNDARY SCAN CONTROL BITS
CELL #
NAME
TYPE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RCLKO3
RLINK3
TSYNC3
TSYNC3_CTL
TSSYNC3
TLCLK3
TCHCLK3
TCHBLK3
RSYNC3
RSYNC3_CTL
RSIGF3
RMSYNC3
RLOS/LOTC3
RLCLK3
RFSYNC3
RCHCLK3
RCHBLK3
ESIBS1_3
ESIBS1_3_CTL
ESIBS0_3
ESIBS0_3_CTL
ESIBRD3
ESIBRD3_CTL
RSIG3
RNEGI3
RPOSI3
RNEGO3
RPOSO3
BPCLK3
RSER3
RSYSCLK3
TSYSCLK3
CS3/NC
LIUC
WR (R/W)
A5
A1
D1/AD1
RD (DS)
BTS
RCLKI2
RCLK2
TSIG2
TSER2
TLINK2
TCLKI2
TCLK2
TNEGI2
TPOSI2
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
output3
controlr
output3
controlr
output3
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
output3
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
CONTROL
CELL
3
9
18
20
22
133
223 of 270
NOTES
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CELL #
NAME
TYPE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TCLKO2
TPOSO2
TNEGO2
RCLKO2
RLINK2
TSYNC2
TSYNC2_CTL
TSSYNC2
TLCLK2
TCHCLK2
TCHBLK2
RSYNC2
RSYNC2_CTL
RSIGF2
RMSYNC2
RLOS/LOTC2
RLCLK2
RFSYNC2
RCHCLK2
RCHBLK2
observe_only
observe_only
observe_only
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
69
ESIBS1_2
output3
70
ESIBS1_2_CTL
controlr
71
ESIBS0_2
output3
72
ESIBS0_2_CTL
controlr
73
ESIBRD2
output3
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
ESIBRD2_CTL
RSIG2
RNEGI2
RPOSI2
RNEGO2
RPOSO2
BPCLK2
RSER2
RSYSCLK2
TSYSCLK2
CS2/A9
TSTRST
RCLKI4
RCLK4
TSIG4
TSER4
TLINK4
TCLKI4
TCLK4
TNEGI4
TPOSI4
TCLKO4
TPOSO4
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
CONTROL
CELL
NOTES
55
61
70
Internally bonded to ESIBS1_1, ESIBS1_3,
ESIBS1_4 on DS21458
72
Internally bonded to ESIBS0_1, ESIBS0_3,
ESIBS0_4 on DS21458
74
Internally bonded to ESIBRD1, ESIBRD3,
ESIBRD4 on DS21458
224 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CELL #
NAME
TYPE
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
TNEGO4
RCLKO4
RLINK4
TSYNC4
TSYNC4_CTL
TSSYNC4
TLCLK4
TCHCLK4
TCHBLK4
RSYNC4
RSYNC4_CTL
RSIGF4
RMSYNC4
RLOS/LOTC4
RLCLK4
RFSYNC4
RCHCLK4
RCHBLK4
observe_only
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
115
ESIBS1_4
output3
116
ESIBS1_4_CTL
controlr
117
ESIBS0_4
output3
118
ESIBS0_4_CTL
controlr
119
ESIBRD4
output3
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
ESIBRD4_CTL
RSIG4
RNEGI4
RPOSI4
RNEGO4
RPOSO4
BPCLK4
RSER4
RSYSCLK4
TSYSCLK4
CS4/CS
D2/AD2
D0/AD0
AD_BUS_CTL
MUX
D4/AD4
A4
A6
D3/AD3
D5/AD5
RCLKI1
RCLK1
TSIG1
TSER1
TLINK1
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
output3
output3
controlr
observe_only
output3
observe_only
observe_only
output3
output3
observe_only
observe_only
observe_only
observe_only
observe_only
CONTROL
CELL
NOTES
101
107
116
Internally bonded to ESIBS1_1, ESIBS1_2,
ESIBS1_3 on DS21458
118
Internally bonded to ESIBS0_1, ESIBS0_2,
ESIBS0_3 on DS21458
120
Internally bonded to ESIBRD1, ESIBRD2,
ESIBRD3 on DS21458
133
133
133
133
133
225 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CELL #
NAME
TYPE
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
TCLKI1
TCLK1
TNEGI1
TPOSI1
TCLKO1
TPOSO1
TNEGO1
RCLKO1
RLINK1
TSYNC1
TSYNC1_CTL
TSSYNC1
TLCLK1
TCHCLK1
TCHBLK1
RSYNC1
RSYNC1_CTL
RSIGF1
RMSYNC1
RLOS/LOTC1
RLCLK1
RFSYNC1
RCHCLK1
RCHBLK1
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
output3
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
169
ESIBS1_1
output3
170
ESIBS1_1_CTL
controlr
171
ESIBS0_1
output3
172
ESIBS0_1_CTL
controlr
173
ESIBRD1
output3
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
ESIBRD1_CTL
RSIG1
RNEGI1
RPOSI1
RNEGO1
RPOSO1
BPCLK1
RSER1
RSYSCLK1
TSYSCLK1
CS1/A8
INT
A2
A0
A3
D7/AD7
D6/AD6
A7/ALE
RCLKI3
controlr
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
output3
output3
observe_only
observe_only
CONTROL
CELL
NOTES
155
161
170
Internally bonded to ESIBS1_2, ESIBS1_3,
ESIBS1_4 on DS21458
172
Internally bonded to ESIBS0_2, ESIBS0_3,
ESIBS0_4 on DS21458
174
Internally bonded to ESIBRD2, ESIBRD3,
ESIBRD4 on DS21458
133
133
226 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CELL #
NAME
TYPE
193
194
195
196
197
198
199
200
201
202
203
RCLK3
TSIG3
TSER3
TLINK3
TCLKI3
TCLK3
TNEGI3
TPOSI3
TCLKO3
TPOSO3
TNEGO3
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
observe_only
CONTROL
CELL
227 of 270
NOTES
DS21455/DS21458 Quad T1/E1/J1 Transceivers
36. FUNCTIONAL TIMING DIAGRAMS
36.1 T1 Mode
Figure 36-1. Receive Side D4 Timing
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
RFSYNC
RSYNC 1
RSYNC 2
3
RSYNC
RLCLK
RLINK
4
NOTES:
1)
2)
3)
4)
RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0).
RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1).
RSYNC in the multiframe mode (IOCR1.5 = 1).
RLINK data (Fs-bits) is updated one bit prior to even frames and held for two frames.
228 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-2. Receive Side ESF Timing
FRAME#
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1
2
3
4
5
1
RSYNC
RFSYNC
RSYNC
2
RSYNC
3
RLCLK
4
5
RLINK
TLCLK 6
TLINK 7
NOTES:
1)
2)
3)
4)
5)
6)
7)
RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0).
RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1).
RSYNC in multiframe mode (IOCR1.4 = 1).
ZBTSI mode disabled (T1RCR2.2 = 0).
RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames.
ZBTSI mode is enabled (T1RCR2.2 = 1).
RLINK data (Z bits) is updated one bit time before odd frames and held for four frames.
229 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-3. Receive Side Boundary Timing (With Elastic Store Disabled)
RCLK
CHANNEL 23
RSER
CHANNEL 24
CHANNEL 1
LSB
LSB MSB
F
MSB
RSYNC
RFSYNC
RSIG
CHANNEL 23
A
B C/A D/B
CHANNEL 24
A
B C/A D/B
RCHCLK
RCHBLK1
RLCLK
RLINK 2
NOTES:
1) RCHBLK is programmed to block channel 24.
2) Shown is RLINK/RLCLK in the ESF framing mode.
230 of 270
CHANNEL 1
A
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-4. Receive Side 1.544MHz Boundary Timing (With Elastic Store
Enabled)
RSYSCLK
CHANNEL 23
RSER
CHANNEL 24
CHANNEL 1
LSB
LSB MSB
F
MSB
RSYNC1
RMSYNC
RSYNC2
RSIG
CHANNEL 23
A
B C/A D/B
CHANNEL 24
A
B C/A D/B
RCHCLK
RCHBLK
3
NOTES:
1) RSYNC is in the output mode (IOCR1.4 = 0).
2) RSYNC is in the input mode (IOCR1.4 = 1).
3) RCHBLK is programmed to block channel 24.
231 of 270
CHANNEL 1
A
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store
Enabled)
RSYSCLK
RSER
RSYNC
1
CHANNEL 31
CHANNEL 32
CHANNEL 1
LSB
LSB MSB
2
RMSYNC
3
RSYNC
RSIG
A
CHANNEL 31
B C/A D/B
A
CHANNEL 32
B C/A D/B
RCHCLK
RCHBLK
4
NOTES:
1)
2)
3)
4)
5)
RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one.
RSYNC is in the output mode (IOCR1.4 = 0).
RSYNC is in the input mode (IOCR1.4 = 1).
RCHBLK is forced to one in the same channels as RSER (Note 1).
The F-bit position is passed through the receive-side elastic store.
232 of 270
CHANNEL 1
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-6. Transmit Side D4 Timing
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
1
TSYNC
TSSYNC
2
TSYNC
3
TSYNC
TLCLK
TLINK
4
NOTES:
1)
2)
3)
4)
TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0).
TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.1 = 1).
TSYNC in the multiframe mode (IOCR1.2 = 1).
TLINK data (Fs-bits) is sampled during the F-bit position of even frames for insertion into the
outgoing T1 stream when enabled via T1TCR1.2.
233 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-7. Transmit Side ESF Timing
FRAME#
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1
2
3
4
5
TSYNC1
TSSYNC
TSYNC
2
3
TSYNC
TLCLK
4
TLINK
TLCLK 5
TLINK
6
NOTES:
1)
2)
3)
4)
TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.3 = 0).
TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.3 = 1).
TSYNC in multiframe mode (IOCR1.2 = 1).
TLINK data (FDL bits) sampled during the F-bit time of odd frame and inserted into the outgoing T1
stream if enabled via TCR1.2.
5) ZBTSI mode is enabled (T1TCR2.1 = 1).
6) TLINK data (Z bits) sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into
the outgoing stream if enabled via T1TCR1.2.
234 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled)
TCLK
CHANNEL 1
LSB
TSER
F
CHANNEL 2
MSB
LSB MSB
LSB MSB
TSYNC1
TSYNC2
CHANNEL 1
TSIG
D/B
A
B
CHANNEL 2
C/A
D/B
TCHCLK
TCHBLK 3
TLCLK
TLINK
4
DON'T CARE
NOTES:
1)
2)
3)
4)
TSYNC is in the output mode (IOCR1.1 = 1).
TSYNC is in the input mode (IOCR1.1 = 0).
TCHBLK is programmed to block channel 2.
Shown is TLINK/TLCLK in the ESF framing mode.
235 of 270
A
B
C/A
D/B
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-9. Transmit Side 1.544MHz Boundary Timing (With Elastic Store
Enabled)
TSYSCLK
CHANNEL 23
CHANNEL 24
LSB MSB
TSER
CHANNEL 1
LSB
F
MSB
TSSYNC
CHANNEL 23
TSIG
A
B
CHANNEL 24
C/A D/B
A
B
CHANNEL 1
C/A D/B
A
TCHCLK
TCHBLK 1
NOTE:
1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored during channel 24).
236 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-10. Transmit Side 2.048MHz Boundary Timing (With Elastic Store
Enabled)
TSYSCLK
CHANNEL 31
TSER
1
CHANNEL 32
LSB MSB
CHANNEL 1
LSB
F
4
TSSYNC
CHANNEL 31
TSIG
A
B
CHANNEL 32
C/A D/B
A
B
CHANNEL 1
C/A D/B
A
TCHCLK
TCHBLK 2,3
NOTES:
1) TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored.
2) TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored).
3) TCHBLK is forced to one in the same channels as TSER is ignored (Note 1).
4) The F-bit position for the T1 frame is sampled and passed through the transmit side elastic store into
the MSB bit position of channel 1. (Normally the transmit side formatter overwrites the F-bit position
unless the formatter is programmed to pass-through the F-bit position).
237 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
36.2 E1 Mode
Figure 36-11. Receive Side Timing
FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RFSYNC
RSYNC
1
RSYNC 2
RLCLK
RLINK
3
4
NOTES:
1)
2)
3)
4)
5)
RSYNC in frame mode (IOCR1.5 = 0).
RSYNC in multiframe mode (IOCR1.5 = 1).
RLCLK is programmed to output just the Sa bits.
RLINK will always output all five Sa bits as well as the rest of the receive data stream.
This diagram assumes the CAS MF begins in the RAF frame.
238 of 270
1
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-12. Receive Side Boundary Timing (With Elastic Store Disabled)
RCLK
CHANNEL 32
CHANNEL 1
RSER
LSB
Si
1
A
CHANNEL 2
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
RSYNC
RFSYNC
CHANNEL 32
RSIG
A
B
CHANNEL 1
C
D
CHANNEL 2
A
B
Note 4
RCHCLK
RCHBLK
1
RLCLK
RLINK
2
Sa4 Sa5 Sa6 Sa7 Sa8
NOTES:
1)
2)
3)
4)
RCHBLK is programmed to block channel 1.
RLCLK is programmed to mark the Sa4 bit in RLINK.
Shown is a RNAF frame boundary.
RSIG normally contains the CAS multiframe-alignment nibble (0000) in channel 1.
239 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-13. Receive Side Boundary Timing, RSYSCLK = 1.544MHz
(With Elastic Store Enabled)
RSYSCLK
CHANNEL 23/31
1
RSER
CHANNEL 24/32
CHANNEL 1/2
LSB
LSB MSB
F
MSB
RSYNC2
RMSYNC
3
RSYNC
RCHCLK
RCHBLK
4
NOTES:
1) Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is
mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one).
2) RSYNC in the output mode (IOCR1.4 = 0).
3) RSYNC in the input mode (IOCR1.4 = 1).
4) RCHBLK is programmed to block channel 24.
240 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-14. Receive Side Boundary Timing, RSYSCLK = 2.048MHz
(With Elastic Store Enabled)
RSYSCLK
CHANNEL 31
RSER
CHANNEL 32
LSB MSB
CHANNEL 1
LSB MSB
RSYNC1
RMSYNC
RSYNC
2
RSIG
A
CHANNEL 31
C
B
D
A
CHANNEL 32
C
B
D
CHANNEL 1
Note 4
RCHCLK
RCHBLK
3
NOTES:
1)
2)
3)
4)
RSYNC is in the output mode (IOCR1.4 = 0).
RSYNC is in the input mode (IOCR1.4 = 1).
RCHBLK is programmed to block channel 1.
RSIG normally contains the CAS multiframe-alignment nibble (0000) in channel 1.
241 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-15. Receive IBO Channel Interleave Mode Timing
RSYNC
1
RSER
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
RSIG1
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
RSER2
FR2 CH32 FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
RSIG2
FR2 CH32 FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
RSYSCLK
3
RSYNC
FRAMER 3, CHANNEL 32
RSER
FRAMER 3, CHANNEL 32
RSIG
FRAMER 1, CHANNEL 1
FRAMER 0, CHANNEL 1
LSB MSB
LSB MSB
A
B
C
FRAMER 1, CHANNEL 1
FRAMER 0, CHANNEL 1
D
A
B
NOTES:
1) 4.096MHz bus configuration.
2) 8.192MHz bus configuration.
3) RSYNC is in the input mode (IOCR1.4 = 0).
242 of 270
C
LSB
D
A
B
C
D
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-16. Receive IBO Frame Interleave Mode Timing
RSYNC
1
RSER
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
RSIG1
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
RSER2
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
RSIG2
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
BIT DETAIL
RSYSCLK
3
RSYNC
FRAMER 3, CHANNEL 32
RSER
FRAMER 3, CHANNEL 32
RSIG
FRAMER 0, CHANNEL 1
A
B
FRAMER 0, CHANNEL 2
LSB MSB
LSB MSB
FRAMER 0, CHANNEL 1
C/A D/B
A
NOTES:
1) 4.096MHz bus configuration.
2) 8.192MHz bus configuration.
3) RSYNC is in the input mode (IOCR1.4 = 0).
243 of 270
B
C/A D/B
LSB
FRAMER 0, CHANNEL 2
A
B
C/A D/B
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-17. G.802 Timing, E1 Mode Only
TS #
31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2
RSYNC
TSYNC
RCHCLK
TCHCLK
RCHBLK
TCHBLK
RCLK / RSYSCLK
TCLK / TSYSCLK
CHANNEL 25
RSER / TSER
CHANNEL 26
LSB MSB
RCHCLK / TCHCLK
RCHBLK / TCHBLK
NOTE:
1) RCHBLK or TCHBLK programmed to pulse high during time slots 1 through 15, 17 through 25, and
bit 1 of time slot 26.
244 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-18. Transmit Side Timing
FRAME#
14 15 16 1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
1
TSYNC
TSSYNC
TSYNC
TLCLK
TLINK
2
3
3
NOTES:
1)
2)
3)
4)
5)
TSYNC in frame mode (IOCR1.2 = 0).
TSYNC in multiframe mode (IOCR1.2 = 1).
TLINK is programmed to source just the Sa4 bit.
This diagram assumes both the CAS MF and the CRC-4 MF begin with the TAF frame.
TLINK and TLCLK are not synchronous with TSSYNC.
245 of 270
9 10
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-19. Transmit Side Boundary Timing (With Elastic Store Disabled)
TCLK
CHANNEL 1
LSB
TSER
Si
1
A
CHANNEL 2
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
LSB MSB
TSYNC1
TSYNC2
CHANNEL 1
TSIG
CHANNEL 2
D
A
B
C
D
TCHCLK
TCHBLK 3
TLCLK
TLINK
4
4
DON'T CARE
DON'T CARE
NOTES:
1)
2)
3)
4)
5)
TSYNC is in the output mode (IOCR1.1 = 1.)
TSYNC is in the input mode (IOCR1.1 = 0).
TCHBLK is programmed to block channel 2.
TLINK is programmed to source the Sa4 bit.
The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the
CAS multiframe-alignment nibble (0000).
6) Shown is a TNAF frame boundary.
246 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-20. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz
(With Elastic Store Enabled)
TSYSCLK
CHANNEL 23
1
TSER
CHANNEL 24
LSB MSB
LSB
TSSYNC
TCHCLK
TCHBLK
CHANNEL 1
2
NOTES:
1) The F-bit position in the TSER data is ignored.
2) TCHBLK is programmed to block channel 24.
247 of 270
F
MSB
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-21. Transmit Side Boundary Timing, TSYSCLK = 2.048MHz
(With Elastic Store Enabled)
TSYSCLK
CHANNEL 31
CHANNEL 32
TSER1
CHANNEL 1
LSB MSB
LSB
F
4
TSSYNC
CHANNEL 31
TSIG
A
B
CHANNEL 32
C
D
A
TCHCLK
TCHBLK 2,3
NOTE:
1) TCHBLK is programmed to block channel 31.
248 of 270
B
CHANNEL 1
C
D
A
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-22. Transmit IBO Channel Interleave Mode Timing
TSSYNC
1
TSER
TSIG1
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
TSER2
FR2 CH32 FR3 CH32 FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
TSIG2
FR2 CH32 FR3 CH32 FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
TSYSCLK
TSSYNC
FRAMER 3, CHANNEL 32
TSER
LSB MSB
LSB MSB
FRAMER 3, CHANNEL 32
TSIG
A
B
C/A D/B
FRAMER 1, CHANNEL 1
FRAMER 0, CHANNEL 1
FRAMER 0, CHANNEL 1
A
NOTES:
1) 4.096MHz bus configuration.
2) 8.192MHz bus configuration.
249 of 270
B
C/A D/B
LSB
FRAMER 1, CHANNEL 1
A
B
C/A D/B
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-23. Transmit IBO Frame Interleave Mode Timing
TSSYNC
1
TSER
TSIG1
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
TSER2
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
TSIG2
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
BIT DETAIL
TSYSCLK
TSSYNC
FRAMER 3, CHANNEL 32
TSER
FRAMER 3, CHANNEL 32
TSIG
FRAMER 0, CHANNEL 1
A
B
C/A D/B
FRAMER 0, CHANNEL 2
LSB MSB
LSB MSB
FRAMER 0, CHANNEL 1
A
NOTES:
1) 4.096MHz bus configuration.
2) 8.192MHz bus configuration.
250 of 270
B
C/A D/B
LSB
FRAMER 0, CHANNEL 2
A
B
C/A D/B
DS21455/DS21458 Quad T1/E1/J1 Transceivers
37. OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +6.0V
Operating Temperature Range for DS21455/DS21458………………………………………0°C to +70°C
Operating Temperature Range for DS21455N/DS21458N………………………………...-40°C to +85°C
Storage Temperature Range……………………………………………………………….-55°C to +125°C
Soldering Temperature ………………………………………………………..See IPC/JEDEC J-STD-20A
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
THERMAL CHARACTERISTICS
PARAMETER
Ambient Temperature
Junction Temperature
Theta-JA (qJA) in Still Air for 100-pin LQFP
Theta-JA (qJA) in Still Air for 10mm
CSBGA pin LQFP
MIN
-40°C
—
—
—
TYP
—
—
MAX
+85°C
+125°C
—
NOTES
1
—
2
2
NOTES:
1) The package is mounted on a four-layer JEDEC standard test board.
2) Theta-JA (qJA) is the junction-to-ambient thermal resistance, when the package is mounted on a fourlayer JEDEC standard test board.
THETA-JA (qJA) vs. AIRFLOW
FORCED AIR
(meters per second)
0
1
2.5
THETA-JA (qJA)
100-PIN LQFP
251 of 270
THETA-JA (qJA)
10mm CSBGA
DS21455/DS21458 Quad T1/E1/J1 Transceivers
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to +70°C for DS21455/DS21458; TA = -40°C to +85°C for DS21455N/DS21458N.)
PARAMETER
Logic 1
Logic 0
Supply
SYMBOL
VIH
VIL
VDD
MIN
2.0
-0.3
3.135
TYP
SYMBOL
CIN
COUT
MIN
TYP
5
7
3.3
MAX
5.5
+0.8
3.465
UNITS
V
V
V
NOTES
MAX
UNITS
pF
pF
NOTES
MAX
UNITS
mA
mA
mA
mA
mA
NOTES
2
3
4
1
CAPACITANCE
(TA = +25°C)
PARAMETER
Input Capacitance
Output Capacitance
DC CHARACTERISTICS
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS21458;
VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21455N/DS21458N.)
PARAMETER
Supply Current
Input Leakage
Output Leakage
Output Current (2.4V)
Output Current (0.4V)
SYMBOL
IDD
IIL
ILO
IOH
IOL
MIN
TYP
75
-1.0
-1.0
+4.0
+1.0
1.0
NOTES:
1)
2)
3)
4)
Applies to RVDD, TVDD, and DVDD.
TCLK = TCLKI = RCLKI = TSYSCLK = RSYSCLK = MCLK = 1.544MHz; outputs open circuited.
0.0V < VIN < VDD.
Applied to INT when tri-stated.
252 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
38. AC TIMING PARAMETERS AND DIAGRAMS
Capacitive test loads are 40pF for bus signals, 20pF for all others.
38.1 Multiplexed Bus AC Characteristics
AC CHARACTERISTICS–MULTIPLEXED PARALLEL PORT (MUX = 1)
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS21458;
VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21455N/DS21458N.) (See Figure 38-1 to Figure 38-3.)
PARAMETER
Cycle Time
Pulse Width, DS Low or RD High
Pulse Width, DS High or RD Low
Input Rise/Fall Times
R/W Hold Time
R/W Setup Time Before DS High
CS Setup Time Before DS, WR, or
RD Active
CS Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid to AS or ALE
Fall
Muxed Address Hold Time
Delay Time DS, WR, or RD to AS
or ALE Rise
Pulse Width AS or ALE High
Delay Time, AS or ALE to DS, WR,
or RD
Output Data Delay Time from DS or
RD
Data Setup Time
SYMBOL
tCYC
PWEL
PWEH
tR , tF
tRWH
tRWS
MIN
200
100
100
10
50
UNITS
ns
ns
ns
ns
ns
ns
tCS
20
ns
tCH
tDHR
tDHW
0
10
5
ns
ns
ns
tASL
15
ns
tAHL
10
ns
tASD
20
ns
PWASH
30
ns
tASED
10
ns
MAX
20
50
80
tDDR
tDSW
TYP
50
253 of 270
ns
ns
NOTES
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-1. Intel Bus Read Timing (BTS = 0 / MUX = 1)
t CYC
ALE
WR
PWASH
t ASD
t ASD
t ASED
PWEH
RD
t CH
t CS
PWEL
CS
t ASL
t DHR
t DDR
AD0-AD7
t AHL
A8 & A9
Figure 38-2. Intel Bus Write Timing (BTS = 0 / MUX = 1)
t CYC
ALE
RD
PWASH
t ASD
t ASED
t ASD
WR
PWEL
PWEH
t CH
t CS
CS
t ASL
t DHW
AD0-AD7
t AHL
A8 & A9
254 of 270
t DSW
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-3. Motorola Bus Timing (BTS = 1 / MUX = 1)
PWASH
AS
DS
PWEH
t ASED
t ASD
PWEL
t CYC
t RWS
t RWH
R/W
AD0-AD7
(read)
t DDR
t ASL
t AHL
t DHR
t CH
t CS
CS
AD0-AD7
(write)
t DSW
t ASL
t AHL
A8 & A9
255 of 270
t DHW
DS21455/DS21458 Quad T1/E1/J1 Transceivers
38.2 Nonmultiplexed Bus AC Characteristics
AC CHARACTERISTICS–NONMULTIPLEXED PARALLEL PORT (MUX = 0)
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS21458;
VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21455N/DS21458N.) (See Figure 38-4 to Figure 38-7.)
PARAMETER
SYMBOL
Setup Time for A0 to A7, Valid to
t1
CS Active
Setup Time for CS Active to Either
t2
RD, WR, or DS Active
Delay Time from Either RD or DS
t3
Active to Data Valid
Hold Time from Either RD, WR,
t4
or DS Inactive to CS Inactive
Hold Time from CS Inactive to
t5
Data Bus Tri-State
Wait Time from Either WR or DS
t6
Activate to Latch Data
Data Setup Time to Either WR or
t7
DS Inactive
Data Hold Time from Either WR
t8
or DS Inactive
Address Hold from Either WR or
t9
DS Inactive
MIN
TYP
MAX
UNITS
0
ns
0
ns
75
0
5
ns
ns
20
ns
75
ns
10
ns
10
ns
10
ns
256 of 270
NOTES
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-4. Intel Bus Read Timing (BTS = 0 / MUX = 0)
A0 to A9
Address Valid
D0 to D7
Data Valid
t5
WR
t1
CS
t2
t3
t4
RD*
Figure 38-5. Intel Bus Write Timing (BTS = 0 / MUX = 0)
A0 to A9
Address Valid
D0 to D7
t7
t8
RD
t1
CS
t2
t6
WR
257 of 270
t4
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-6. Motorola Bus Read Timing (BTS = 1 / MUX = 0)
A0 to A9
Address Valid
D0 to D7
Data Valid
t5
R/W
t1
CS
t2
t3
t4
DS
Figure 38-7. Motorola Bus Write Timing (BTS = 1 / MUX = 0)
A0 to A9
Address Valid
D0 to D7
t7 t8
R/W
t1
CS
t2
t6
DS
258 of 270
t4
DS21455/DS21458 Quad T1/E1/J1 Transceivers
38.3 Receive Side AC Characteristics
AC CHARACTERISTICS–RECEIVE SIDE
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS21458;
VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21455N/DS21458N.) (See Figure 38-8 to Figure 38-12.)
PARAMETER
RCLKO Period
RCLKO Pulse Width
RCLKO Pulse Width
RCLKI Period
RCLKI Pulse Width
RSYSCLK Period
RSYSCLK Pulse Width
RSYNC Setup to RSYSCLK Falling
RSYNC Pulse Width
RPOSI/RNEGI Setup to RCLKI Falling
RPOSI/RNEGI Hold from RCLKI
Falling
RSYSCLK, RCLKI Rise and Fall Times
Delay RCLKO to RPOSO, RNEGO
Valid
Delay RCLK to RSER, RDATA, RSIG,
RLINK Valid
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC, RLCLK
Delay RSYSCLK to RSER, RSIG Valid
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC
SYMBOL
MIN
tLP
tLH
tLL
tLH
tLL
200
200
150
150
tCP
tCH
tCL
tSP
tSP
tSP
tSP
tSP
tSH
tSL
tSU
tPW
tSU
20
20
tHD
20
20
20
20
50
20
TYP
488
(E1)
648
(T1)
0.5 tLP
0.5 tLP
0.5 tLP
0.5 tLP
488
(E1)
648
(T1)
0.5 tCP
0.5 tCP
648
488
244
122
61
0.5 tSP
0.5 tSP
MAX
UNITS
ns
ns
ns
ns
ns
ns
1
1
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t R , tF
22
ns
tDD
50
ns
tD1
50
ns
tD2
50
ns
tD3
22
ns
tD4
22
ns
259 of 270
NOTES
3
4
5
6
7
DS21455/DS21458 Quad T1/E1/J1 Transceivers
AC CHARACTERISTICS–RECEIVE SIDE (continued)
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS21458;
VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21455N/DS21458N.) (See Figure 38-8 to Figure 38-12.)
NOTES:
1)
2)
3)
4)
5)
6)
7)
Jitter attenuator enabled in the receive path.
Jitter attenuator disabled or enabled in the transmit path.
RSYSCLK = 1.544MHz.
RSYSCLK = 2.048MHz.
RSYSCLK = 4.096MHz.
RSYSCLK = 8.192MHz.
RSYSCLK = 16.384MHz.
Figure 38-8. Receive Side Timing, Elastic Store Disabled (T1 Mode)
RCLK
t D1
F Bit
RSER / RDATA / RSIG
t D2
RCHCLK
t D2
RCHBLK
t D2
RFSYNC / RMSYNC
t D2
RSYNC 1
RLCLK
t D2
2
t D1
RLINK
NOTES:
1) RSYNC is in the output mode.
2) Shown is RLINK/RLCLK in the ESF framing mode.
3) No relationship between RCHCLK and RCHBLK and other signals is implied.
260 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-9. Receive Side Timing, Elastic Store Disabled (E1 Mode)
RCLK
t D1
MSB of
Channel 1
RSER / RDATA / RSIG
t D2
RCHCLK
t D2
RCHBLK
t
D2
RFSYNC / RMSYNC
t D2
RSYNC1
t D2
2
RLCLK
t D1
RLINK
Sa4 to Sa8
Bit Position
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0).
2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship
between RLCLK and RSYNC or RFSYNC is implied.
261 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-10. Receive Side Timing, Elastic Store Enabled (T1 Mode)
t SL
tF
tR
RSYSCLK
t SP
t D3
F-BIT
RSER / RSIG
t D4
RCHCLK
t D4
RCHBLK
t
D4
RMSYNC
RSYNC
RSYNC
1
t D4
t HD
2
t SH
t SU
NOTES:
1) RSYNC is in the output mode.
2) RSYNC is in the input mode.
262 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-11. Receive Side Timing, Elastic Store Enabled (E1 Mode)
t SL
tF
tR
RSYSCLK
t SH
t SP
t D3
MSB of
Channel 1
RSER / RSIG
t D4
RCHCLK
t D4
RCHBLK
t
D4
RMSYNC / CO
t D4
RSYNC1
t HD
t SU
2
RSYNC
t SC
t WC
CI
NOTES:
1) RSYNC is in the output mode.
2) RSYNC is in the input mode.
263 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-12. Receive Line Interface Timing
t LL
RCLKO
t LH
t LP
t DD
RPOSO, RNEGO
tR
t CL
tF
RCLKI
t CP
t SU
RPOSI, RNEGI
t HD
264 of 270
t CH
DS21455/DS21458 Quad T1/E1/J1 Transceivers
38.4 Transmit AC Characteristics
AC CHARACTERISTICS–TRANSMIT SIDE
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS21458;
VDD = 3.3V ±5%, TA = -40°C to +85°C; for DS21455N/DS21458N.) (See Figure 38-13 to Figure 38-15.)
PARAMETER
SYMBOL
TCLK Period
tCP
TCLK Pulse Width
tCH
tCL
TCLKI Period
tLP
TCLKI Pulse Width
tLH
tLL
MIN
20
20
20
20
TYP (E1)
488 (E1)
648 (T1)
0.5 tCP
0.5 tCP
488 (E1)
648 (T1)
0.5 tLP
0.5 tLP
648
448
244
122
61
0.5 tSP
0.5 tSP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSYSCLK Period
tSP
TSYSCLK Pulse Width
tSP
20
20
tSU
20
ns
tPW
50
ns
tSU
20
ns
tHD
20
ns
tHD
20
ns
TSYNC or TSSYNC Setup to TCLK
or TSYSCLK Falling
TSYNC or TSSYNC Pulse Width
TSER, TSIG, TDATA, TLINK,
TPOSI, TNEGI Setup to TCLK,
TSYSCLK, TCLKI Falling
TSER, TSIG, TDATA, TLINK Hold
from TCLK or TSYSCLK, Falling
TPOSI, TNEGI Hold from TCLKI
Falling
TCLK, TCLKI, or TSYSCLK Rise
and Fall Times
Delay TCLKO to TPOSO, TNEGO
Valid
Delay TCLK to TESO Valid
Delay TCLK to TCHBLK, TCHCLK,
TSYNC, TLCLK
Delay TSYSCLK to TCHCLK,
TCHBLK
tR , tF
25
ns
tDD
50
ns
tD1
50
ns
tD2
50
ns
tD3
22
ns
NOTES:
1)
2)
3)
4)
5)
TSYSCLK = 1.544MHz.
TSYSCLK = 2.048MHz.
TSYSCLK = 4.096MHz.
TSYSCLK = 8.192MHz.
TSYSCLK = 16.384MHz.
265 of 270
NOTES
1
2
3
4
5
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-13. Transmit Side Timing
t CP
t CL
tF
tR
t CH
TCLK
t D1
TESO
t SU
TSER / TSIG /
TDATA
t HD
t D2
TCHCLK
t D2
TCHBLK
t D2
TSYNC1
t SU
t HD
TSYNC2
5
TLCLK
t D2
t HD
TLINK
t SU
NOTES:
1) TSYNC is in the output mode (TCR2.2 = 1).
2) TSYNC is in the input mode (TCR2.2 = 0).
3) TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
4) TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.
5) TLINK is only sampled during F-bit locations.
6) No relationship between TCHCLK and TCHBLK and the other signals is implied.
266 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-14. Transmit Side Timing, Elastic Store Enabled
t SP
t SL
tF
tR
t SH
TSYSCLK
t SU
TSER
t D3
t HD
TCHCLK
t D3
TCHBLK
t SU
t HD
TSSYNC
NOTES:
1) TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is
enabled.
2) TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is
enabled.
267 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-15. Transmit Line Interface Timing
TCLKO
TPOSO, TNEGO
t DD
tR
t LP
t LL
tF
t LH
TCLKI
t SU
TPOSI, TNEGI
t HD
NOTES:
1) TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is
enabled.
2) TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is
enabled.
268 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
39. PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
Figure 39-1. DS21458 (17mm CSBGA)
269 of 270
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 39-2. DS21455 (27mm BGA)
270 of 270
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
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