TI ONET2511PARGTR

SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
features
D Multi-Rate Operation from 155 Mbps Up To
D
D
D
D
D
D
2.5 Gbps
Ultralow Power Consumption
Input Offset Cancellation
High Input Dynamic Range
Output Disable
Output Polarity Select
CML Data Outputs
D Single 3.3-V Supply
D Surface Mount Small Footprint 3 mm ×
3 mm 16-Pin QFN Package
applications
D SONET/SDH Transmission Systems at OC3,
D
D
OC12, OC24, OC48
1.0625-Gbps and 2.125-Gbps Fibre Channel
Receivers
Gigabit Ethernet Receivers
description
The ONET2511PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates
up to 2.5 Gbps.
This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as
low as 3 mVp−p.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1800 mVp−p.
The ONET2511PA is available in a small footprint 3 mm × 3 mm 16-pin QFN package. The circuit requires a
single 3.3-V supply.
This power efficient limiting amplifier is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
!"# "$! %#
%"! ! #!! # &# # #' "#
%% () %"! !#* %# #!#$) !$"%#
#* $$ ##
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
block diagram
A simplified block diagram of the ONET2511PA is shown in Figure 1.
This compact, low power 2.5-Gbps limiting amplifier consists of a high-speed data path with offset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
COC2
COC1
Bandgap Voltage
Reference and
Bias Current
Generation
Offset
Cancellation
VCC
GND
OUTPOL
VCCO
DIN+
+
DIN−
−
+
+
+
Gain Stage
Gain Stage
+
DOUT+
−
Input Buffer
Gain Stage
DOUT−
CML
Output
Buffer
DISABLE
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages which provide
the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even
for small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
bandgap voltage and bias generation
The ONET2511PA limiting amplifier is supplied by a single 3.3-V ±10% supply voltage connected to the VCC
and VCCO pins. This voltage is referred to ground (GND).
An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.
2
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package
N.C.
COC1
GND
COC2
For the ONET2511PA a small footprint 3 mm × 3 mm 16-pin QFN package is used, with a lead pitch of 0,5 mm.
The pinout is shown in Figure 2.
16 15 14 13
12 VCCO
VCC 1
9
5
6
7
8
N.C.
VCC 4
GND
DIN− 3
DISABLE
11 DOUT+
10 DOUT−
N.C.
DIN+ 2
OUTPOL
Figure 2. Pinout of ONET2511PA in a 3 mm y 3 mm 16-Pin QFN Package (Top View)
terminal functions
The following table shows a pin description for the ONET2511PA in a 3 mm x 3 mm 16-pin QFN package.
TERMINAL
TYPE
NAME
NO.
VCC
1, 4
Supply
DESCRIPTION
3.3-V ±10% supply voltage
DIN+
2
Analog in
Noninverted data input. On-chip 50-Ω terminated to VCC
DIN–
3
Analog in
Inverted data input. On-chip 50-Ω terminated to VCC
N.C.
5, 7, 13
DISABLE
6
Not connected
CMOS in
Disables CML output stage when set to high level
GND
8, 16, EP
Supply
OUTPOL
9
CMOS in
Circuit ground. Exposed die pad (EP) must be grounded.
Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects
normal polarity. Low level selects inverted polarity.
DOUT–
10
CML out
Inverted data output. On-chip 50-Ω back-terminated to VCCO
DOUT+
11
CML out
Noninverted data output. On-chip 50-Ω back-terminated to VCCO
VCCO
12
Supply
3.3-V ±10% supply voltage for output stage
COC1
14
Analog
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin
and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
COC2
15
Analog
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin
and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
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3
SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
absolute maximum ratings
over operating free-air temperature range unless otherwise noted†
VCC, VCCO
VDIN+, VDIN−
Supply voltage, See Note 1
VDISABLE, VOUTPOL, VDOUT+,VDOUT−,
VCOC1, VCOC2
Voltage at TH, DISABLE, OUTPOL, DOUT+, DOUT–, COC1, and
COC2, See Note 1
VCOC_DIFF
VDIN_DIFF
Differential voltage between COC1 and COC2
IDIN+, IDIN−, IDOUT+, IDOUT–
Continuous current at inputs and outputs
Voltage at DIN+, DIN–, See Note 1
Differential voltage between DIN+ and DIN–
ESD rating at all pins except VCCO
ESD
VALUE
UNIT
–0.3 to 4
V
0.5 to 4
V
–0.3 to 4
V
±1
V
±2.5
V
–25 to 25
mA
3
ESD rating at VCCO
kV (HBM)
1.1
TJ(max)
Tstg
Maximum junction temperature
125
°C
Storage temperature range
−65 to 85
°C
TA
TL
Characterized free-air operating temperature range
−40 to 85
°C
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions
Supply voltage, VCC, VCCO
Operating free-air temperature, TA
MIN
TYP
MAX
3
3.3
3.6
V
85
°C
−40
UNIT
dc electrical characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC,VCCO
IVCC
Supply voltage
VOD
Differential data output voltage swing
RIN, ROUT
Data input/output resistance
VIN,MIN
VIN,MAX
Data input sensitivity
Supply current
MIN
TYP
MAX
3
3.3
3.6
V
22
28
mA
0.25
10
780
1200
mVp−p
mVp−p
DISABLE = low (excludes CML output current)
DISABLE = high
DISABLE = low
Ω
50
3
Data input overload
5
1800
CMOS input high voltage
2.1
CMOS input low voltage
4
600
Single ended
BER < 10–10
• DALLAS, TEXAS 75265
mVp−p
mVp−p
V
0.6
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UNIT
V
SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
ac electrical characteristics
over recommended operating conditions (unless otherwise noted), typical operating condition is at VCC = 3.3 V and
TA = 25°C
PARAMETER
TEST CONDITIONS
Low frequency −3-dB bandwidth
MIN
MAX
45
70
COC = open
COC = 100 nF
2.5
Gb/s
Input referred noise
DJ
300
Deterministic jitter, See Note 2
K28.5 pattern at 2.5 Gbps
223−1 PRBS equivalent pattern at 2.5 Gbps
8.5
25
9.3
30
223−1 PRBS equivalent pattern at 155 Mbps
25
50
Input = 5 mVpp
6.5
RJ
Random jitter
tr
tf
Output rise time
20% to 80%
Output fall time
20% to 80%
PSNR
Power supply noise rejection
f < 2 MHz
UNIT
kHz
0.8
Data rate
vNI
TYP
Input = 10 mVpp
psp−p
psRMS
3
60
85
60
85
26
µVRMS
ps
ps
dB
tDIS
Disable response time
NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage.
20
ns
APPLICATION INFORMATION
Figure 3 shows the ONET2511PA connected with an ac-coupled interface to the data signal source as well as
to the output load.
The ac-coupling capacitors C1 through C4 in the input and output data signal lines are the only required external
components. In addition, an optional external filter capacitor (COC) may be used if a lower cutoff frequency is
desired.
NC
COC1
COC2
GND
COC
Optional
VCC
DIN−
DOUT+
ONET2511PA
16-Pin QFN
NC
VCC
DOUT−
VCC
C3
C4
OUTPOL
DOUT+
DOUT−
OUTPOL
GND
DIN+
NC
DIN−
C2
VCCO
DISABLE
DIN+
C1
DISABLE
Figure 3. Basic Application Circuit With AC-Coupled I/Os
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SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = VCCO = +3.3 V and TA = 25°C (unless otherwise noted)
RANDOM JITTER
vs
DIFFERENTIAL INPUT VOLTAGE
900
10
800
9
8
700
Random Jitter − psRMS
VOD − Differential Output Voltage − mVP-P
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
600
500
400
300
200
7
6
5
4
3
2
100
1
0
0
1
2
3
4
5
6
0
VID − Differential Input Voltage − mVP-P
5
10
15
Figure 5
Figure 4
BIT ERROR RATIO
vs
DIFFERENTIAL INPUT VOLTAGE
100
10-2
10-4
Bit Error Ratio
10-6
10-8
10-10
10-12
10-14
10-16
10-18
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VID − Differential Input Voltage − mVP-P
Figure 6
6
20
25
30
35
VID − Differential Input Voltage − mVP-P
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5.0
40
SLLS604C − MARCH 2004 − REVISED OCTOBER 2005
OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
MINIMUM INPUT VOLTAGE (5 mVp−p)
VOD − Differential Output Voltage − 100 mV/Div
VOD − Differential Output Voltage − 100 mV/Div
OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
MAXIMUM INPUT VOLTAGE (1800 mVp−p)
t − Time − 100 ps/Div
t − Time − 100 ps/Div
Figure 7
Figure 8
DIFFERENTIAL OUTPUT RETURN GAIN
vs
FREQUENCY
DIFFERENTIAL INPUT RETURN GAIN
vs
FREQUENCY
0
SDD22 − Differential Output Return Gain − dB
SDD11 − Differential Input Return Gain − dB
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
0.1
1
5
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
0.1
1
5
f − Frequency − GHz
f − Frequency − GHz
Figure 9
Figure 10
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7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ONET2511PARGTR
NRND
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ONET2511PARGTRG4
NRND
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ONET2511PARGTT
NRND
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ONET2511PARGTTG4
NRND
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ONET2511PARGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ONET2511PARGTT
QFN
RGT
16
250
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ONET2511PARGTR
QFN
RGT
16
3000
340.5
333.0
20.6
ONET2511PARGTT
QFN
RGT
16
250
340.5
333.0
20.6
Pack Materials-Page 2
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