EL4584C EL4584C Horizontal Genlock, 4 FSC Features General Description # 36 MHz, general purpose PLL # 4 FSC based timing (use the EL4585 for 8 FSC) # Compatible w/EL4583 Sync Separator # VCXO, Xtal, or LC tank oscillator # k 2 ns jitter (VCXO) # User controlled PLL capture and lock # Compatible with NTSC and PAL TV formats # 8 pre-programmed TV scan rate clock divisors # Selectable external divide for custom ratios # Single 5V, low current operation The EL4584C is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it. Applications # Pixel Clock regeneration # Video compression engine (MPEG) clock generator # Video capture or digitization # PIP (Picture in Picture) timing generator # Text or graphics overlay timing Ordering Information Part No. Temp. Range Package Outline Ý EL4584CN -40§ C to a 85§ C 16-Pin DIP MDP0031 EL4584CS -40§ C to a 85§ C 16-Lead SO MDP0027 For 6Fsc and 8Fsc clock frequencies, see EL4585 datasheet. The divider ratio is four ratios for NTSC and four similar ratios for the PAL video timing standards, by external selection of three control pins. These four ratios have been selected for common video applications including 4 FSC, 3 FSC, 13.5 MHz (CCIR 601 format) and square picture elements used in some workstation graphics. To generate 8 FSC, 6 FSC, 27 MHz (CCIR 601 format) etc. use the EL4585, which includes an additional divide by 2 stage. For applications where these frequencies are inappropriate or for general purpose PLL applications the internal divider can be bypassed and an external divider chain used. FREQUENCIES and DIVISORS Function 3Fsc CCIR 601 Square 4Fsc Divisor PAL Fosc (MHz) 851 13.301 864 13.5 944 14.75 1135 17.734 Divisor NTSC Fosc (MHz) 682 10.738 858 13.5 780 12.273 910 14.318 CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL. Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion. 3Fsc numbers do not yield integer divisors. Connection Diagram EL4584 SO, P-DIP Packages A demo PCB is available for this product. Request ‘‘EL4584/5 Demo Board’’. 4584 – 17 Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these Ý4584C specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. © 1994 Elantec, Inc. February 1995 Rev B Demo Board The reference signal is a horizontal sync signal, TTL/CMOS format, which can be easily derived from an analog composite video signal with the EL4583 Sync Separator. An input signal to ‘‘coast’’ is provided for applications were periodic disturbances are present in the reference video timing such as VTR head switching. The Lock detector output indicates correct lock. EL4584C Horizontal Genlock, 4 FSC Absolute Maximum Ratings (TA e 25§ C) VCC Supply Storage Temperature Lead Temperature Pin Voltages Operating Ambient Temperature Range 7V 125§ C 400 mW 36 MHz Operating Junction Temp Power Dissipation Oscillator Frequency b 65§ C to a 150§ C 260§ C b 0.5V to VCC a 0.5V b 40§ C to a 85§ C Important Note: All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore TJ e TC e TA. Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002. 100% production tested at TA e 25§ C and QA sample tested at TA e 25§ C , TMAX and TMIN per QA test plan QCX0002. QA sample tested per QA test plan QCX0002. Parameter is guaranteed (but not tested) by Design and Characterization Data. Parameter is typical value at TA e 25§ C for information purposes only. Parameter IDD Conditions Temp Min 25§ C VDD e 5V (Note 1) VIL Input Low Voltage 25§ C VIH Input High Voltage 25§ C 3.5 IIL Input Low Current All inputs except COAST, VIN e 1.5V 25§ C b 100 IIH Input High Current All inputs except COAST, VIN e 3.5V 25§ C IIL Input Low Current COAST pin, VIN e 1.5V 25§ C IIH Input High Current COAST pin, VIN e 3.5V 25§ C VOL Output Low Voltage Lock Det, IOL e 1.6mA 25§ C VOH Output High Voltage Lock Det, IOH e b1.6mA 25§ C VOL Output Low Voltage CLK, IOL e 3.2mA 25§ C VOH Output High Voltage CLK, IOH e b3.2mA 25§ C VOL Output Low Voltage OSC Out, IOL e 200mA 25§ C VOH Output High Voltage OSC Out, IOH e b200mA 25§ C 2.4 IOL Output Low Current Filter Out, VOUT e 2.5V 25§ C 200 IOH Output High Current Filter Out, VOUT e 2.5V 25§ C IOL/IOH Current Ratio Filter Out, VOUT e 2.5V 25§ C ILEAK Filter Out Coast Mode, VDDlVOUTl0V 25§ C Note 1: All inputs to 0V, COAST floating. 2 Typ Max Test Level Units 2 4 I mA 1.5 I V I V I nA I nA I mA 100 I mA 0.4 I V I V I V 100 b 100 b 60 60 2.4 0.4 2.4 0.4 300 I V I V I V I mA mA b 300 b 200 I 1.05 1.0 0.95 I b 100 g1 100 I nA TD is 3.5in DC Electrical Characteristics (VDD e 5V, TA e 25§ C unless otherwise noted) TD is 3.5in EL4584C Horizontal Genlock, 4 FSC AC Electrical Characteristics (VDD e 5V, TA e 25§ C unless otherwise noted) Conditions Temp Min Typ Max Test Level Units Test Circuit 1 25§ C H-sync S/N Ratio VDD e 5V (Note 2) 25§ C Jitter VCXO Oscillator 25§ C 1 V ns Jitter LC Oscillator (Typ) 25§ C 10 V ns @ 20 MHz 15.5 35 V dB V dB Note 2: Noisy video signal input to EL4583C, H-sync input to EL4584C. Test for positive signal lock. Pin Description Pin No. Pin Name Function 16,1,2 Prog A,B,C Digital inputs to select d N value for internal counter. See table below for values. 3 Osc/VCO Out Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit. 4 VDD (A) Analog positive supply for oscillator, PLL circuits. 5 Osc/VCO In Input from external VCO. 6 VSS (A) Analog ground for oscillator, PLL circuits. 7 Charge Pump Out Connect to loop filter. If the H-sync phase is leading or H-sync frequency l CLK d N, current is pumped into the filter capacitor to increase VCO frequency. If H-sync phase is lagging or frequency k CLK d N, current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when locked, charge pump goes to a high impedance state. 8 Div Select Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting CLK d N. When low, the internal divider is disabled and EXT DIV is an input from an external d N. 9 Coast Tri-state logic input. Low(k(/3*VCC) e normal mode, Hi Z(or (/3 to )/3*VCC) e fast lock mode, High(l)/3*VCC) e coast mode. 10 H-sync In Horizontal sync pulse (CMOS level) input. 11 VDD (D) Positive supply for digital, I/O circuits. 12 Lock Det Lock Detect output. Low level when PLL is locked. Pulses high when out of lock. 13 Ext Div External Divide input when DIV SEL is low, internal d N output when DIV SEL is high. 14 VSS (D) Ground for digital, I/O circuits. 15 CLK Out Buffered output of the VCO. VCO Divisors Table 1 Prog A Pin 16 Prog B Pin 1 Prog C Pin 2 Div Value N 0 0 0 851 0 0 1 864 0 1 0 944 0 1 1 1135 1 0 0 682 1 0 1 858 1 1 0 780 1 1 1 910 3 TD is 3.5in VCO Gain TAB WIDE Parameter EL4584C Horizontal Genlock, 4 FSC Timing Diagrams PLL Locked Condition (Phase Error e 0) 4584 – 2 Falling edge of H-sync a 110 ns locks to rising edge of Ext Div signal. Out of Lock Condition Ti c 360§ TH TH e H-sync period Ti e phase error period iE e 4584 – 3 Test Circuit 1 4584 – 5 4 EL4584C Horizontal Genlock, 4 FSC Typical Performance Curves Idd vs Fosc 4584 OSC Gain @ 20 MHz vs Temp 4584 – 6 4584 – 4 Typical Varactor OSC Gain vs Fosc 4584 – 7 4584 – 8 Charge Pump Duty Cycle vs iE 4584 – 9 5 EL4584C Horizontal Genlock, 4 FSC Block Diagram 4584 – 1 6 EL4584C Horizontal Genlock, 4 FSC can source or sink a maximum of about 300 mA, so all frequency control must be accomplished with variable capacitance from the varactor within this range. Crystal oscillators are more stable than LC oscillators, which translates into lower jitter, but LC oscillators can be pulled from their mid-point values further, resulting in a greater capture and locking range. If the incoming horizontal sync signal is known to be very stable, then a crystal oscillator circuit can be used. If the h-sync signal experiences frequency variations of greater than about 300 ppm, an LC oscillator should be considered, as crystal oscillators are very difficult to pull this far. When H-SYNC input frequency is greater than CLK frequency d N, charge pump output (pin 7) sources current into the filter capacitor, increasing the voltage across the varactor, which lowers its capacitance, thus tending to increase VCO frequency. Conversely, filter output pulls current from the filter capacitor when H-SYNC frequency is less than CLK d N, forcing the VCO frequency lower. Description Of Operation The horizontal sync signal (CMOS level, falling leading edge) is input to H-sync input (pin 10). This signal is delayed about 110 ns, the falling edge of which becomes the reference to which the clock output will be locked. (See timing diagrams.) The clock is generated by the signal on pin 5, OSC in. There are 2 general types of VCO that can be used with the EL4584C, LC and crystal controlled. Additionally, each type can be either built up using discrete components, including a varactor as the frequency controlling element, or complete, self contained modules can be purchased with everything inside a metal can. The modules are very forgiving of PCB layout, but cost more than discrete solutions. The VCO or VCXO is used to generate the clock. An LC tank resonator has greater ‘‘pull’’ than a crystal controlled circuit, but will also be more likely to drift over time, and thus will generate more jitter. The ‘‘pullability’’ of the circuit refers to the ability to ‘‘pull’’ the frequency of oscillation away from its center frequency by modulating the voltage on the control pin of a VCO module or varactor, and is a function of the slope and range of the capacitance-voltage curve of the varactor or VCO module used. The VCO signal is sent to a divide by N counter, and to the CLK out pin. The divisor N is determined by the state of pins 1,2, and 16 and is described in table 1 above. The divided signal is sent, along with the delayed H-sync input, to the phase/frequency detector, which compares the two signals for phase and frequency differences. Any phase difference is converted to a current at the charge pump output FILTER (pin 7). A VCO with positive frequency deviation with control voltage must be used. Varactors have negative capacitance slope with voltage, resulting in positive frequency deviation with control voltage for the oscillators in figures 10 and 11 below. Loop Filter The loop filter controls how fast the VCO will respond to a change in filter output stimulus. Its components should be chosen so that fast lock can be achieved, yet with a minimum of VCO ‘‘hunting’’, preferably in one to two oscillations of charge pump output, assuming the VCO frequency starts within capture range. If the filter is under-damped, the VCO will over and undershoot the desired operating point many times before a stable lock takes place. It is possible to under-damp the filter so much that the loop itself oscillates, and VCO lock is never achieved. If the filter is over-damped, the VCO response time will be excessive and many cycles will be required for a lock condition. Over-damping is also characterized by an easily unlocked system because the filter can’t respond fast enough to perturbations in VCO frequency. A severely over damped system will seem to endlessly oscillate, like a very large mass at the end of a long pendulum. Due to parasitic effects of PCB traces and component variables, it will take some trial and error experimentation to determine the best values to use for any given situation. Use the component tables as a starting point, but be aware that deviation from these values is not out of the ordinary. VCO The VCO should be tuned so its frequency of oscillation is very close to the required clock output frequency when the voltage on the varactor is 2.5 volts. VCXO and VCO modules are already tuned to the desired frequency, so this step is not necessary if using one of these units. The range of the charge pump output (pin 7) is 0 to 5 volts and it 7 EL4584C Horizontal Genlock, 4 FSC Forcing the clock to be synchronized to the Hsync input this way allows a lock in approximately 2 H-cycles, but the clock spacing will not be regular during this time. Once the near lock condition is attained, charge pump output should be very close to its lock-on value and placing the device into normal mode should result in a normal lock very quickly. Fast Lock mode is intended to be used where H-sync becomes irregular, until a stable signal is again obtained. Description of Operation Ð Contd. External Divide DIV SEL (pin 8) controls the use of the internal divider. When high, the internal divider is enabled and EXT DIV (pin 13) outputs the CLK out divided by N. This is the signal to which the horizontal sync input will lock. When divide select is low, the internal divider output is disabled, and external divide becomes an input from an external divider, so that a divisor other than one of the 8 pre-programmed internal divisors can be used. Coast Mode Coast mode is enabled by pulling COAST (pin 9) high (above )/3*VCC). In coast mode the internal phase detector is disabled and filter out remains in high impedance mode to keep filter out voltage and VCO frequency as constant a possible. VCO frequency will drift as charge leaks from the filter capacitor, and the voltage changes the VCO operating point. Coast mode is intended to be used when noise or signal degradation result in loss of horizontal sync for many cycles. The phase detector will not attempt to adjust to the resultant loss of signal so that when horizontal sync returns, sync lock can be re-established quickly. However, if much VCO drift has occurred, it may take as long to re-lock as when restarting. Normal Mode Normal mode is enabled by pulling COAST (pin 9) low (below (/3*VCC). If H-sync and CLK d N have any phase or frequency difference, an error signal is generated and sent to the charge pump. The charge pump will either force current into or out of the filter capacitor in an attempt to modulate the VCO frequency. Modulation will continue until the phase and frequency of CLK d N exactly match the H-sync input. When the phase and frequency match (with some offset in phase that is a function of the VCO characteristics), the error signal goes to zero, lock detect no longer pulses high, and the charge pump enters a high impedance state. The clock is now locked to the H-sync input. As long as phase and frequency differences remain small, the PLL can adjust the VCO to remain locked and lock detect remains low. Lock Detect Lock detect (pin 12) will go low when lock is established. Any DC current path from charge pump out will skew EXT DIV relative to H-SYNC in, tending to offset or add to the 110 ns internal delay, depending on which way the extra current is flowing. This offset is called static phase error, and is always present in any PLL system. If, when the part stabilizes in a locked mode, lock detect is not low, adding or subtracting from the loop filter series resistor R2 will change this static phase error to allow LDET to go low while in lock. The goal is to put the rising edge of EXT DIV in sync with the falling edge of H-SYNC a 110 ns. (See timing diagrams.) Increasing R2 decreases phase error, while decreasing R2 increases phase error. (Phase error is positive when EXT DIV lags H-SYNC.) The resistance needed will depend on VCO design or VCXO module selection. Fast Lock Mode Fast Lock mode is enabled by either allowing coast to float, or pulling it to mid supply (between (/3 and )/3*VCC). In this mode, lock is achieved much faster than in normal mode, but the clock divisor is modified on the fly to achieve this. If the phase detector detects an error of enough magnitude, the clock is either inhibited or reset to attempt a ‘‘fast’’ lock of the signals. 8 EL4584C Horizontal Genlock, 4 FSC Typical LC VCO Applications Information Choosing External Components 1. To choose LC VCO components, first pick the desired operating frequency. For our example we will use 14.31818 MHz, with an H-sync frequency of 15.734 kHz. 2. Choose a reasonable inductor value (10–20mH works well). We choose 15 mH. 3. Calculate CT needed to produce FOSC. FOSC e 4584 – 10 Figure 10 1 2q 0LCT LC VCO Component Values (Approximate) 1 1 e e 8.2 pF 4q2F2L 4q2(14.318e6)2(15e b 6) 4. From the varactor data sheet find CV @ 2.5V, the desired lock voltage. CV e 23 pF for our SMV1204-12, for example. 5. C2 should be about 10CV, so we choose C2 e 220 pF for our example. 6. Calculate C1. Since CT e CT e C1C2CV , (C1C2) a (C1CV) a (C2CV) L1 (mH) C1 (pF) C2 (pF) 13.301 15 18 220 13.5 15 17 220 14.75 12 18 220 17.734 12 10 220 10.738 22 20 220 12.273 18 17 220 14.318 15 14 220 Note: Use shielded inductors for optimum performance. Typical Xtal VCO then C1 e Frequency (MHz) C2CTCV . (C2CV) b (C2CT) b (CTCV) For our example, C1 e 14 pF. (A trim cap may be used for fine tuning.) Examples for each frequency using the internal divider follow. Typical Application Horizontal genlock provides clock for an analog to digital converter, digitizing analog video. 4584 – 11 Figure 11 4584 – 18 9 EL4584C Horizontal Genlock, 4 FSC Xtal VCO Component Values (Approximate) Frequency (MHz) R1 (kX) C1 (pF) C2 (uF) 13.301 300 15 .001 13.5 300 15 .001 14.75 300 15 .001 17.734 300 15 .001 10.738 300 15 .001 12.273 300 15 .001 14.318 300 15 .001 Choosing Loop Filter Components The PLL, VCO, and loop filter can be described as: 4584 – 13 Where: Kd e phase detector gain in A/rad F(s) e loop filter impedance in V/A The above oscillators are arranged as Colpitts oscillators, and the structure is redrawn here to emphasize the split capacitance used in a Colpitts oscillator. It should be noted that this oscillator configuration is just one of literally hundreds possible, and the configuration shown here does not necessarily represent the best solution for all applications. Crystal manufacturers are very informative sources on the design and use of oscillators in a wide variety of applications, and the reader is encouraged to become familiar with them. KVCO e VCO gain in rad/s/V N e internal or external divisor It can be shown that for the loop filter shown below: C3 e Colpitts Oscillator KdKVCO C 2Ng0n e 3, R3 e 2 , C4 10 KdKVCO N0n Where 0n e loop filter bandwidth, and g e loop filter damping factor. 1. Kd e 300 mA/2qrad e 4.77e-5A/rad for the EL4584C. 2. The loop bandwidth should be about H-sync frequency/20, and the damping ratio should be 1 for optimum performance. For our example, 0n e 15.734 kHz/20 e 787 Hz & 5000 rad/S. 3. N e 910 from table 1. 4584 – 12 C1 is to adjust the center frequency, C2 DC isolates the control from the oscillator, and V1 is the primary control device. C2 should be much larger than CV so that V1 has maximum modulation capability. The frequency of oscillation is given by: Fe Ne 4. KVCO represents how much the VCO frequency changes for each volt applied at the control pin. It is assumed (but probably isn’t) linear about the lock point (2.5V). Its value depends on the VCO configuration and the varactor 1 2q0LCT CT e VCOfrequency 14.31818M e e 910 H-SYNCfrequency 15.73426k C1C2CV (C1C2) a (C1CV) a (C2CV) 10 EL4584C Horizontal Genlock, 4 FSC transfer function Cv e F(VC), where VC is the reverse bias control voltage, and CV is varactor capacitance. Since F(VC) is nonlinear, it is probably best to build the VCO and measure KVCO about 2.5V. The results of one such measurement are shown below. The slope of the curve is determined by linear regression techniques and equals KVCO. For our example, KVCO e 6.05 Mrad/S/V. Lock Time Let S e R3C3. As T increases, damping increases, but so does lock time. Decreasing T decreases damping and speeds up loop response, but increases overshoot and thus increases the number of hunting oscillations before lock. Critical damping (g e 1) occurs at minimum lock time. Because decreased damping also decreases loop stability, it is sometimes desirable to design slightly overdamped (g l 1), trading lock time for increased stability. FOSC vs VC, LC VCO Typical Loop Filter 4584 – 16 LC Loop Filter Components (Approximate) 4584 – 14 Frequency (MHz) 5. Now we can solve for C3, C4, and R3. C3 e KdKVCO (4.77e b 5)(6.05e6) e e 0.01 mF N02n (910)(5000)2 C4 e C3 e 0.001 mF 10 2Ng0n (2)(910)(1)(5000) e e 31.5 kX R3 e KdKVCO (4.77e b 5)(6.05e6) We choose R3 e 30 kX for convenience. 6. Notice R2 has little effect on the loop filter design. R2 should be large, around 100k, and can be adjusted to compensate for any static phase error Ti at lock, but if made too large, will slow loop response. If R2 is made smaller, Ti (see timing diagrams) increases, and if R2 increases, Ti decreases. For LDET to be low at lock, l Ti l k 50 ns. C4 is used mainly to attenuate high frequency noise from the charge pump. R2 (kX) R3 (kX) C3 (mF) C4 (mF) 13.301 100 30 0.01 0.001 13.5 100 30 0.01 0.001 14.75 100 33 0.01 0.001 17.734 100 39 0.01 0.001 10.738 100 22 0.01 0.001 12.273 100 27 0.01 0.001 14.318 100 30 0.01 0.001 Xtal Loop Filter Components (Approximate) 11 Frequency (MHz) R2 (kX) R3 (MX) C3 (pF) C4 (pF) 13.301 100 4.3 68 6.8 13.5 100 4.3 68 6.8 14.75 100 4.3 68 6.8 17.734 100 4.3 68 6.8 10.738 100 4.3 68 6.8 12.273 100 4.3 68 6.8 14.318 100 4.3 68 6.8 EL4584C Horizontal Genlock, 4 FSC care must be taken to avoid parasitic capacitance at the OSC pins 3 and 5, and FILTER out (pin 7). Remove ground and power plane copper above and below these traces to avoid making a capacitive connection to them. It is also recommended to enclose the oscillator section within a shielded cage to reduce external influences on the VCO, as they tend to be very sensitive to ‘‘handwaving’’ influences, the LC variety being more sensitive than crystal controlled oscillators. In general, the higher the operating frequency, the more important these considerations are. Self contained VCXO or VCO modules are already mounted in a shielding cage and therefore do not require as much consideration in layout. Many crystal manufacturers publish informative literature regarding use and layout of oscillators which should be helpful. PCB Layout Considerations It is highly recommended that power and ground planes be used in layout. The oscillator and filter sections constitute a feedback loop and thus care must be taken to avoid any feedback signal influencing the oscillator except at the control input. The entire oscillator/filter section should be surrounded by copper ground to prevent unwanted influences from nearby signals. Use separate paths for analog and digital supplies, keeping the analog (oscillator section) as short and free from spurious signals as possible. Careful attention must be paid to correct bypassing. Keep lead lengths short and place bypass caps as close to the supply pins as possible. If laying out a PCB to use discrete components for the VCO section, 12 EL4584C 4584–19 Horizontal Genlock, 4 FSC Demo Board 13 EL4584C Horizontal Genlock, 4 FSC The VCO and loop filter section of the EL4583/4/5 demo board can be implemented in the following configurations: (1) VCXO 4584 – 20 (2) XTAL 4584 – 21 (3) LC Tank 4584 – 22 14 15 BLANK EL4584C EL4584C Horizontal Genlock, 4 FSC Component Sources # SaRonix Inductors 151 Laura Lane Palo Alto, CA 94043 (415) 856-6900 # Dale Electronics E. Highway 50 PO Box 180 Yankton, SD 57078-0180 (605) 665-9301 # Standard Crystal 9940 Baldwin Place El Monte, CA 91731 (818) 443-2121 Crystals, VCXO, VCO Modules # Connor-Winfield 2111 Comprehensive Drive Aurora, IL 60606 (708) 851-4722 Varactors # Alpha Industries 20 Sylvan Road Woburn, MA 01801 (617) 935-5150 # Piezo Systems 100 K Street PO Box 619 Carlisle, PA 17013 (717) 249-2151 # Motorola Semiconductor Products 2100 E. Elliot Tempe, AZ 85284 (602) 244-6900 # Reeves-Hoffman 400 West North Street Carlisle, PA 17013 (717) 243-5929 Note: These sources are provided for information purposes only. No endorsement of these companies is implied by this listing. General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. February 1995 Rev B WARNING Ð Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Elantec, Inc. 1996 Tarob Court Milpitas, CA 95035 Telephone: (408) 945-1323 (800) 333-6314 Fax: (408) 945-9305 European Office: 44-71-482-4596 16 Printed in U.S.A.