TI TAS5424ATDKDMQ1

TAS5414A, TAS5424A
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SLOS535 – JUNE 2007
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS
FEATURES
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TAS5414A – Single-Ended Input
TAS5424A – Differential Input
Four-Channel Digital Power Amplifier
Four Analog Inputs, Four BTL Power Outputs
Typical Output Power per Channel at 10%
THD+N
– 28 W/Ch Into 4 Ω at 14.4 Vdc
– 45 W/Ch Into 2 Ω at 14.4 Vdc
– 58 W/Ch Into 4 Ω at 21 Vdc
– 116 W/Ch Into 2 Ω at 21 Vdc PBTL
Channels Can Be Paralleled (PBTL) for 1-Ω
Applications
THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
Patented Pop- and Click-Reduction
Technology
– Soft Muting With Gain Ramp Control
– Common-Mode Ramping
Patented AM Interference Avoidance
Patented Cycle-by-Cycle Current Limit
75-dB PSRR
Four-Address I2C Serial Interface for Device
Configuration and Control
Configurable Channel Gains: 12-dB, 20-dB,
26-dB, 32-dB
Load Diagnostic Functions:
– Output Open and Shorted Load
– Output-to-Power and -to-Ground Shorts
– Patented Tweeter Detection
Protection and Monitoring Functions:
– Short-Circuit Protection
– Load-Dump Protection to 50 V
– Fortuitous Open Ground and Power
Tolerant
– Patented Output DC Level Detection While
Music Playing
– Overtemperature Protection
– Over- and Undervoltage Conditions
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– Clip Detection
36-Pin PSOP3 (DKD) Power SOP Package
With Heat Slug Up for the TAS5414A
44-Pin PSOP3 (DKD) Power SOP Package
With Heat Slug Up for the TAS5424A
Designed for Automotive EMC Requirements
Pb-Free Soldering Supported
ISO9000:2002 TS16949 Certified
–40°C to 105°C Ambient Temperature Range
APPLICATIONS
•
High-power OEM/retail head units and
amplifier modules where feature densities and
system configurations require reduction in
heat from the audio power amplifier
DESCRIPTION
The TAS5414A and TAS5424A are four-channel
digital audio amplifiers designed for use in
automotive head units and external amplifier
modules. The TAS5414A and TAS5424A provide
four channels at 23 W continuously into 4 Ω at less
than 1% THD+N from a 14.4-V supply. Each channel
can also deliver 38 W into 2 Ω at 1% THD+N. The
TAS5414A uses single-ended analog inputs, while
the TAS5424A employs differential inputs for
increased immunity to common-mode system noise.
The digital PWM topology of the TAS5414A and
TAS5424A provides dramatic improvements in
efficiency over traditional linear amplifier solutions.
This reduces the power dissipated by the amplifier
by a factor of ten under typical music playback
conditions. High efficiency is accomplished without
the need for complicated power-supply schemes.
Multiple TAS5414As or TAS5424As can be
synchronized
to
meet
high-channel-count
applications.
The TAS5414A and TAS5424A incorporate all the
functionality needed to perform in the demanding
OEM applications area. They have built-in load
diagnostic functions for detecting and diagnosing
misconnected outputs to help to reduce test time
during the manufacturing process.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TAS5414A, TAS5424A
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SLOS535 – JUNE 2007
TAS5414A FUNCTIONAL BLOCK DIAGRAM
3.3 V – 5 V
TAS5414A-36 Pins
Pull-Up Resistors
System
mP
AVDD (6.5 V)
SDA
SCL
STANDBY
Supplies
and
References
D_BYP
A_BYP
DVDD (3.3 V)
2
I C
SGND
OverTemp
Warn/SD
FAULT
CLIP_OTW
REXT
VREF and IREF
I2C ADDR
“0” – “3”
Fault
and
Timing
Logic
Channel
Utilities
GND
CP
AVDD
Over/Under
Voltage
CPC_TOP
PVDD
Load Dump
OSC_SYNC
Charge
Pump
Osc
and
Clock
GND/SGND PGND
CPC_BOT
CP
Battery
8 VDC – 22 VDC
Channel 1 of 4
MUTE
Load Diagnostics and Fault Monitors
Optional
DC Detect
Open/Short Diagnostic
OC Timer
AVSS
Clip Detect
FLV
RLV
FRV
RRV
Radio DSP
Signal Path
PVDD
Current
Limit
IN1_P
IN3_P
IN2_P
IN4_P
IN_M
OUT1_P
PreAmp
Tweeter
Detect
PWM
Gate
Driver
Feedback
OUT1_M
PGND
Channels 2, 3, 4: Same as Ch 1
B0198-03
2
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SLOS535 – JUNE 2007
TAS5424A FUNCTIONAL BLOCK DIAGRAM
3.3 V – 5 V
TAS5424A-44 Pins
Pull-Up Resistors
System
mP
AVDD (6.5 V)
SDA
SCL
STANDBY
Supplies
and
References
D_BYP
A_BYP
DVDD (3.3 V)
2
I C
SGND
OverTemp
Warn/SD
FAULT
CLIP_OTW
REXT
VREF and IREF
I2C ADDR
“0” – “3”
Fault
and
Timing
Logic
Channel
Utilities
GND
CP
AVDD
Over/Under
Voltage
CPC_TOP
PVDD
Load Dump
OSC_SYNC
Charge
Pump
Osc
and
Clock
GND/SGND PGND
CPC_BOT
CP
Battery
8 VDC – 22 VDC
Channel 1 of 4
MUTE
Load Diagnostics and Fault Monitors
Optional
DC Detect
Clip Detect
Open/Short Diagnostic
OC Timer
Signal Path
PVDD
Current
Limit
IN1_P
Audio
Input
IN1_M
OUT1_P
PreAmp
Tweeter
Detect
PWM
Gate
Driver
Feedback
OUT1_M
PGND
Channels 2, 3, 4: Same as Ch 1
B0198-04
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PIN ASSIGNMENTS AND FUNCTIONS
The pin assignments for the TAS5414A and TAS5424A are shown as follows.
TAS5414A
DKD PACKAGE
(TOP VIEW)
OSC_SYNC
I2C_ADDR
SDA
SCL
FAULT
MUTE
STANDBY
D_BYP
CLIP_OTW
GND
SGND
REXT
A_BYP
IN1_P
IN2_P
IN_M
IN3_P
IN4_P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TAS5424A
DKD PACKAGE
(TOP VIEW)
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PVDD
PVDD
OUT1_M
OUT1_P
PGND
OUT2_M
OUT2_P
CPC_TOP
CP
CPC_BOT
PGND
OUT3_M
OUT3_P
PGND
OUT4_M
OUT4_P
PVDD
PVDD
P0018-04
OSC_SYNC
I2C_ADDR
SDA
SCL
FAULT
MUTE
GND
STANDBY
D_BYP
CLIP_OTW
GND
SGND
REXT
A_BYP
IN1_P
IN1_M
IN2_P
IN2_M
IN3_P
IN3_M
IN4_P
IN4_M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PVDD
PVDD
PVDD
OUT1_M
OUT1_P
PGND
PGND
OUT2_M
OUT2_P
CPC_TOP
CP
CP_BOT
PGND
OUT3_M
OUT3_P
PGND
PGND
OUT4_M
OUT4_P
PVDD
PVDD
PVDD
P0055-02
4
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Table 1. TERMINAL FUNCTIONS
TERMINAL
DKD Package
NAME
TAS5414 TAS5424
A
A
NO.
NO.
TYPE (1)
DESCRIPTION
A_BYP
13
14
PBY
Bypass capacitor for the AVDD analog regulator
CLIP_OTW
9
10
DO
Open-drain CLIP, OTW, or logical OR of the CLIP and OTW outputs. It also reports
tweeter detection during tweeter mode.
CP
28
34
CP
Top of main storage capacitor for charge pump (bottom goes to PVDD)
CPC_BOT
27
33
CP
Bottom of flying capacitor for charge pump
CPC_TOP
29
35
CP
Top of flying capacitor for charge pump
D_BYP
8
9
PBY
Bypass pin for DVDD regulator output
FAULT
5
5
DO
Global fault output (open drain): UV, OV, OTSD, OCSD, DC
GND
10
7, 11
DG
Ground
I2C_ADDR
2
2
AI
I2C address bit
IN1_M
N/A
16
AI
Inverting analog input for channel 1 (TAS5424A only)
IN1_P
14
15
AI
Non-inverting analog input for channel 1
IN2_M
N/A
18
AI
Inverting analog input for channel 2 (TAS5424A only)
IN2_P
15
17
AI
Non-inverting analog input for channel 2
IN3_M
N/A
20
AI
Inverting analog input for channel 3 (TAS5424A only)
IN3_P
17
19
AI
Non-inverting analog input for channel 3
IN4_M
N/A
22
AI
Inverting analog input for channel 4 (TAS5424A only)
IN4_P
18
21
AI
Non-inverting analog input for channel 4
IN_M
16
N/A
ARTN
MUTE
6
6
AI
OSC_SYNC
1
1
DI/DO
OUT1_M
34
41
PO
– polarity output for bridge 1
OUT1_P
33
40
PO
+ polarity output for bridge 1
OUT2_M
31
37
PO
– polarity output for bridge 2
OUT2_P
30
36
PO
+ polarity output for bridge 2
OUT3_M
25
31
PO
– polarity output for bridge 3
OUT3_P
24
30
PO
+ polarity output for bridge 3
OUT4_M
22
27
PO
– polarity output for bridge 4
OUT4_P
21
26
PO
+ polarity output for bridge 4
PGND
23, 26,
32
28, 29,
32, 38,
39
PGND
Power GND
PVDD
19, 20,
35, 36
23, 24,
25, 42,
43, 44
PWR
PVDD supply
REXT
12
13
AI
Precision resistor pin to set clock frequency
SCL
4
4
DI
I2C clock input from system I2C master
SDA
3
3
DI/DO
I2C data I/O for communication with system I2C master
SGND
11
12
AG/DG
Signal ground (analog and digital signal ground)
STANDBY
7
8
DI
(1)
Signal return for the 4 analog channel inputs (TAS5414A only)
Gain ramp control: mute (low), play (high)
Oscillator sync input from master or output to slave amplifiers (20 MHz divided by 5,
6, or 7)
Active-low STANDBY pin. Standby (low), power up (high)
DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PGND = power ground,
PBY = power bypass, PO = power output, AG = analog ground, DG = digital ground, CP = charge pump.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.3 to 30
V
–1 to 50
V
PVDD
DC supply voltage range
Relative to PGND
PVDDMAX
Pulsed supply voltage range
t ≤ 100 ms exposure
PVDDRAMP
Supply voltage ramp rate
Voltage rising up to PVDDMAX
IPVDD
Externally imposed dc supply current per PVDD or PGND pin
IPVDD_MAX
Pulsed supply current per PVDD pin (one shot)
IO
Maximum allowed dc current per output pin
IO_MAX (1)
Pulsed output current per output pin (single pulse)
t < 100 ms
±17
A
IIN_MAX
Maximum current, all digital and analog input pins (2)
DC or pulsed
±1
mA
IMUTE_MAX
Maximum current on MUTE pin
DC or pulsed
±20
mA
IIN_ODMAX
Maximum sinking current for open-drain pins
7
mA
VLOGIC
Input voltage range for logic pin relative to SGND (SCL and
SDA pins)
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 7
V
VI2C_ADDR
Input voltage range for I2C_ADDR pin relative to SGND
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 7
V
VSTANDBY
Input voltage range for STANDBY pin
Supply voltage range:
6.5 V < PVDD < 24V
–0.3 to 5.8
V
VOSC_SYNC
Input voltage range for OSC_SYNC pin relative to SGND
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 3.6
V
VAIN_MAX
Maximum instantaneous input voltage (per pin), analog input
pins
Supply voltage range:
6.5 V < PVDD < 24 V
6.5
V
VAIN_AC_MAX_5414
Maximum ac coupled input voltage for TAS5414A (2), analog
input pins
Supply voltage range:
6.5 V < PVDD < 24 V
1.9
Vrms
VAIN_AC_MAX_5424
Maximum ac coupled differential input voltage for
TAS5424A (2), analog input pins
Supply voltage range:
6.5 V < PVDD < 24 V
3.8
(1.9 per
pin)
Vrms
VAIN_DC
Input voltage range for analog pin relative to AGND (INx pins)
Supply voltage range:
6.5 V < PVDD < 24 V
–0.3 to 6.5
V
TJ
Maximum operating junction temperature range
–55 to 150
°C
Tstg
Storage temperature range
–55 to 150
°C
TSOLDER
Lead temperature during soldering 1,6 mm (1/16 inch) from
case for 10 seconds
260
°C
Power dissipation
Continuous power dissipation
80
W
(1)
(2)
t < 100 ms
Tcase = 70°C
25
V/ms
±12
A
17
A
±13.5
A
Pulsed current ratings are maximum survivable currents externally applied to the TAS5414A and TAS5424A. High currents may be
encountered during reverse battery, fortuitous open ground, and fortuitous open supply fault conditions.
See Application Information section for information on analog input voltage and ac coupling.
THERMAL CHARACTERISTICS
6
PARAMETER
VALUE
UNIT
RθJC
Junction-to-case (heat slug) thermal
resistance
1
°C/W
RθJA
Junction-to-ambient thermal resistance
This device is not intended to be used without a heatsink. Therefore, RθJA
is not specified. See the Thermal Information section.
°C/W
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RECOMMENDED OPERATING CONDITIONS
PVDDOP
(1)
DC supply voltage range relative to PGND
2
PVDDI2C
DC supply voltage range for I C reporting
MIN
TYP
MAX
8
14.4
22
V
6
14.4
26.5
V
(2)
Analog audio input signal level (TAS5414A)
AC-coupled input voltage
0
VAIN_5424 (2)
Analog audio input signal level (TAS5424A)
AC-coupled input voltage
0
fAUDIO_TW
Audio frequency for tweeter detect
TA
Ambient temperature
VAIN_5414
(3)
Vrms
0.5–2(3)
Vrms
25
kHz
–40
105
°C
–40
115
°C
10
An adequate heat sink is required
to keep TJ within specified range
UNIT
0.25–1
20
TJ
Junction temperature
RL
Nominal speaker load impedance
2
4
VPU
Pullup voltage supply (for open-drain logic outputs)
3
3.3 or 5
5.5
V
10
50
100
kΩ
1
5
10
kΩ
100
kΩ
RPU_EXT
External pullup resistor on open-drain logic outputs
RPU_I2C
I2C pullup resistance on SDA and SCL pins
Resistor connected between
open-drain logic output and VPU
supply
Ω
2
RI2C_ADD
Total resistance of voltage divider for I C address
slave 1 or slave 2, connected between D_BYP and
SGND pins
RREXT
External resistance on REXT pin
20.2
kΩ
CD_BYP
External capacitance on D_BYP pin
10
120
nF
CA_BYP
External capacitance on A_BYP pin
10
120
nF
CIN
External capacitance to analog input pin in series
with input signal
CFLY
Flying capacitor on charge pump
0.47
1
1.5
μF
CP
Charge pump capacitor
0.47
1
1.5
μF
CMUTE
Capacitance on MUTE pin
3.3
330
nF
COSCSYNC_MAX
Allowed loading capacitance on OSC_SYNC pin
5
pF
(1)
(2)
(3)
10
1% tolerance required
19.8
20
μF
1
The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical
Characteristics table for specified performance limits.
Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
Maximum recommended input voltage is determined by the gain setting.
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ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode
operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
240
300
UNIT
OPERATING CURRENT
IPVDD_IDLE
IPVDD_Hi-Z
IPVDD_STBY
All four channels running in MUTE mode
PVDD idle current
All four channels in Hi-Z mode
80
STANDBY mode, TJ ≤ 85°C
PVDD standby current
2
20
mA
μA
OUTPUT POWER
4 Ω, PVDD = 14.4V, THD+N ≤ 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, Tc = 75°C
23
25
4 Ω, PVDD = 14.4V, square wave, 1 kHz, Tc = 75°C
43
4 Ω, PVDD = 21 V, THD+N = 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 21 V, THD+N = 10%, 1 kHz, Tc = 75°C
POUT
47
50
2 Ω, PVDD = 14.4V, THD+N = 1%, 1 kHz, Tc = 75°C
Output power per channel
2 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, Tc = 75°C
W
45
2 Ω, PVDD = 14.4 V, square wave 1 kHz, Tc = 75°C
70
PBTL 2-Ω operation, PVDD = 21 V, THD+N = 10%,
1 kHz, Tc = 75°C
116
90
4 channels operating, 23W output power/ch, L = 10 μH,
TJ ≤ 85°C
Power efficiency
58
38
40
PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%,
1 kHz, Tc = 75°C
EFFP
28
90%
AUDIO PERFORMANCE
Noise voltage at output
G = 26 dB, zero input, AES17 filter, and A-weighting
Crosstalk
Channel crosstalk
1W, G = 26 dB, 1 kHz
60
75
dB
CMRR5424
Common-mode rejection ratio (TAS5424A)
1 kHz, 1 Vrms referenced to SGND, G = 26 dB
60
75
dB
PSRR
Power supply rejection ratio
G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
60
75
THD+N
Total harmonic distortion + noise
P = 1 W, G = 26 dB, f = 1 kHz, 0°C ≤ TJ ≤ 75°C
Switching frequency
Switching frequency selectable for AM interference
avoidance
fS
RAIN
Analog input resistance
Internal shunt resistance on each input pin
VIN_CM
Common-mode input voltage (non-clipping)
AC-coupled common-mode input voltage (zero
differential input)
VCM_INT
Internal common-mode input bias voltage
Internal bias applied to IN_M pin
G
Voltage gain (VO/VIN)
Source impedance = 0 Ω
GCH
Channel-to-channel variation
Any gain commanded
tCM
Output-voltage common-mode ramping time
tGAIN
Gain ramping time
60
100
μV
VNOISE
dB
0.02%
0.1%
336
357
378
392
417
442
470
500
530
60
80
100
kΩ
1.3
Vrms
3.25
V
11
12
13
19
20
21
25
26
27
31
32
33
–1
0
1
External CMUTE = 330 nF
kHz
dB
dB
35
ms
30
ms
PWM OUTPUT STAGE
RDSon
FET Drain-to-source resistance
Not including bond wire resistance, TJ = 25°C
VO_OFFSET
Output offset voltage
Zero input signal and G = 26 dB
75
95
mΩ
±10
±25
mV
23.7
26.3
V
PVDD OVER VOLTAGE (OV) PROTECTION
VOV
PVDD over voltage shutdown
22.1
LOAD DUMP (LD) PROTECTION
VLD_SD_SET
Load-dump shutdown voltage
26.6
29
32
V
VLD_SD_CLEAR
Recovery voltage for load-dump shutdown
23.5
26.4
28.4
V
PVDD UNDER VOLTAGE (UV) PROTECTION
8
VUV_SET
PVDD under voltage shutdown
6.5
7
7.5
V
VUV_CLEAR
Recovery voltage for PVDD UV
7
7.5
8
V
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ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode
operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD
VA_BYP
A_BYP pin voltage
6.5
V
VA_BYP_UV_SET
A_BYP UV voltage
4.8
V
VA_BYP_UV_CLEAR
Recovery voltage A_BYP UV
5.3
V
D_BYP pin voltage
3.3
V
DVDD
VD_BYP
POWER-ON RESET (POR)
VPOR
Maximum PVDD voltage for POR; I2C
active above this voltage
VPOR_HY
PVDD recovery hysteresis voltage for POR
6
V
0.1
V
1.24
V
REXT
VREXT
Rext pin voltage
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
4.8
V
VCPUV_CLEAR
Recovery voltage for CP UV
5.2
V
OVERTEMPERATURE (OV) PROTECTION
TOTW1_CLEAR
TOTW1_SET /
TOTW2_CLEAR
TOTW2_SET /
TOTW3_CLEAR
Junction temperature for overtemperature
warning
TOTW3_SET /
TOTWD_CLEAR
TOTSD
Junction temperature for overtemperature
shutdown
102
115
128
112
125
138
122
135
148
132
145
158
142
155
168
°C
CURRENT LIMITING PROTECTION
ILIM1
Current limit 1 (load current)
Load < 4 Ω
5.5
7.3
9
A
ILIM2
Current limit 2 (load current), I2C setting
current limit level 2
Load < 2 Ω
8.5
11
13.5
A
9.5
11.3
13
A
11.5
14.3
17
A
325
540
750
mA
OVERCURRENT (OC) SHUTDOWN PROTECTION
IMAX1
Maximum current 1 (peak output current)
IMAX2
Maximum current 2 (peak output current)
Any short to supply, ground, or other channels
TWEETER DETECT
ITH_TW
Load current threshold for tweeter detect
ILIM_TW
Load current limit for tweeter detect
2
A
STANDBY MODE
VIH_STBY
STANDBY input voltage for logic-level high
2
5.5
VIL_STBY
STANDBY input voltage for logic-level low
0
0.7
V
ISTBY_PIN
STANDBY pin current
0.2
μA
0.1
V
MUTE MODE
Output attenuation
MUTE pin ≤ 0.9Vdc, VIN = 1 Vrms on all inputs
VTH_DCD_POS
DC detect positive threshold default value
VTH_DCD_NEG
DC detect negative threshold default value
tDCD
DC detect step response time for four
channels
GMUTE
85
dB
PVDD = 14.4 Vdc, register 0x0E = 8EH
6.5
V
PVDD = 14.4 Vdc, register 0x0F = 3DH
–6.5
V
DC DETECT
4.3
s
CLIP_OTW REPORT
VOH_CLIPOTW
VOL_CLIPOTW
CLIP_OTW pin output voltage for logic level
high (open-drain logic output)
CLIP_OTW pin output voltage for logic level
low (open-drain logic output)
2.4
V
External 47-kΩ pullup resistor to 3 V–5.5 V
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ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode
operation (see application diagram)
PARAMETER
tDELAY_CLIPDET
TEST CONDITIONS
MIN
TYP
CLIP_OTW signal delay when output
clipping detected
MAX
20
UNIT
μs
FAULT REPORT
VOH_FAULT
VOL_FAULT
FAULT pin output voltage for logic-level
high (open-drain logic output)
2.4
FAULT pin output voltage for logic-level low
(open-drain logic output)
External 47-kΩ pullup resistor to 3 V–5.5 V
V
0.5
OPEN/SHORT DIAGNOSTICS
RS2P, RS2G
Maximum resistance to detect a short from
OUT pin(s) to PVDD or ground
ROPEN_LOAD
Minimum load resistance to detect open
circuit
Including speaker wires
300
RSHORTED_LOAD
Maximum load resistance to detect short
circuit
Including speaker wires
0.5
Voltage on I2C_ADDR pin for address 0
Connect to SGND
0%
0%
15%
Voltage on I2C_ADDR pin for address 1
External resistors in series between D_BYP and SGND
as a voltage divider
25%
35%
45%
Voltage on I2C_ADDR pin for address 2
55%
65%
75%
Voltage on I2C_ADDR pin for address 3
Connect to D_BYP
85%
100%
100%
tHOLD_I2C
Power-on hold time before I2C
communication
STANDBY high
fSCL
SCL clock frequency
VIH_SCL
SCL pin input voltage for logic-level high
VIL_SCL
SCL pin input voltage for logic-level low
200
Ω
800
1300
Ω
1
1.5
Ω
I2C ADDRESS DECODER
tLATCH_I2CADDR
VI2C_ADDR
Time delay to latch I2C address after POR
μs
300
VD_BYP
I2C
RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V
VOH_SDA
SDA pin output voltage for logic-level high
I2C read, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VOL_SDA
SDA pin output voltage for logic-level low
I2C read, 3-mA sink current
1
ms
100
kHz
2.1
5.5
V
–0.5
1.1
V
2.4
V
0
0.4
V
2
VIH_SDA
SDA pin input voltage for logic-level high
I C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
2.1
5.5
V
VIL_SDA
SDA pin input voltage for logic-level low
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
–0.5
1.1
V
Ci
Capacitance for SCL and SDA pins
10
pF
3.6
V
0.5
V
3.6
V
0.8
V
OSCILLATOR
VOH_OSCSYNC
OSC_SYNC pin output voltage for
logic-level high
2.4
I2C_ADDR pin set to MASTER mode
VOL_OSCSYNC
OSC_SYNC pin output voltage for
logic-level low
VIH_OSCSYNC
OSC_SYNC pin input voltage for logic-level
high
VIL_OSCSYNC
fOSC_SYNC
10
OSC_SYNC pin input voltage for logic-level
low
OSC_SYNC pin clock frequency
2
I2C_ADDR pin set to SLAVE mode
I2C_ADDR pin set to MASTER mode, fS = 500 kHz,
maximum capacitive loading = 5 pF
3.76
4.0
4.24
I2C_ADDR pin set to MASTER mode, fS = 417 kHz,
maximum capacitive loading = 5 pF
3.13
3.33
3.63
I2C_ADDR pin set to MASTER mode, fS = 357 kHz,
maximum capacitive loading = 5 pF
2.68
2.85
3.0
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2
TIMING REQUIREMENTS FOR I C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
tr
Rise time for both SDA and SCL signals
PARAMETER
1000
ns
tf
Fall time for both SDA and SCL signals
300
ns
tw(H)
SCL pulse duration, high
4
μs
tw(L)
SCL pulse duration, low
4.7
μs
tsu2
Setup time for START condition
4.7
μs
th2
START condition hold time after which first clock pulse is generated
4
μs
tsu1
Data setup time
250
ns
th1
Data hold time
0 (1)
ns
tsu3
Setup time for STOP condition
CB
Load capacitance for each bus line
(1)
MIN
TYP
μs
4
400
pF
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Timing for Start and Stop Conditions
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TYPICAL CHARACTERISTICS
THD+N vs POWER at 1kHz
THD+N vs FREQUENCY at 1 Watt
10
10
21 VDC, 4 Ω
14.4 VDC, 4 Ω
1
0.1
THD+N − Total Harmonic Distrotion + Noise − %
THD+N − Total Harmonic Distrotion + Noise − %
100
14.4 VDC, 2 Ω
21 VDC, 2 Ω, PBTL
0.01
0.1
1
10
14.4 VDC, 2 Ω
14.4 VDC, 4 Ω
0.1
0.01
0.001
10
100 200
PO − Output Power − W
1
21 VDC, 4 Ω
100
Figure 4.
COMMON-MODE REJECTION RATIO
(TAS5424A)vsFREQUENCY
CROSSTALKvsFREQUENCY
0
−30
−20
−40
−40
Crosstalk − dBV
−50
−60
−70
−60
−80
−100
−80
−90
10
−120
100
1k
10k 20k
−140
10
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G004
G003
Figure 5.
12
10k 20k
G002
G001
Figure 3.
CMRR − Common−Mode Rejection Ratio − dBV
1k
f − Frequency − Hz
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
IMD SMPTE 19 kHz, 20 kHz 1:1
NOISE FFT
−60
−70
−20
−80
−40
Voltage − dBV
IMD SMPTE 19 kHz, 20 kHz 1:1 − dBV
0
−60
−90
−80
−100
−100
−110
−120
10
100
1k
10k
−120
10
30k
100
f − Frequency − Hz
1k
10k
30k
f − Frequency − Hz
G005
G006
Figure 7.
Figure 8.
EFFICIENCY,
FOUR CHANNELS AT 4 Ω EACH
DEVICE POWER DISSIPATION
FOUR CHANNELS INTO 4 Ω
100
12
90
10
80
Power Dissipation − W
Efficiency − %
70
60
50
40
30
20
8
6
4
2
10
0
0
0
4
8
12
16
20
24
28
32
0
P − Power Per Channel − W
G007
Figure 9.
5
10
15
20
P − Power Per Channel − W
G008
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
DC DETECT VOLTAGE
vs
REGISTER 0E VALUES
20
18
16
DC Detect − V
14
PVDD = 20 V
PVDD = 14.4 V
12
10
8
PVDD = 8 V
6
4
2
0
65
6a
6f
74 79
7e
83
88 8d 92 97 9c a1
Register 0E − Hex
a6
ab b0 b5
ba
bf
c4
c9
G009
Figure 11.
DC DETECT VOLTAGE
vs
REGISTER 0F VALUES
0
−2
−4
PVDD = 8 V
DC Detect − V
−6
−8
PVDD = 14.4 V
−10
−12
−14
PVDD = 20 V
−16
−18
−20
00
05 0a
0f
14
19
1e
23 28 2d 32 37 3c
Register 0F − Hex
41
46 4b 50
55
5a
5f
64
G010
Figure 12.
14
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DESCRIPTION OF OPERATION
OVERVIEW
The TAS5414A and TAS5424A are single-chip, four-channel, analog-input audio amplifiers for use in the
automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments,
but with changes needed by the automotive industry. This technology allows for reduced power consumption,
reduced heat, and reduced peak currents in the electrical system. The TAS5414A and TAS5424A realize an
audio sound system design with smaller size and lower weight than traditional class-AB solutions.
The TAS5414A and TAS5424A are composed of eight elements:
• Preamplifier
• PWM
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
Preamplifier
The preamplifier of the TAS5414A and TAS5424A is a high-input-impedance, low-noise, low-offset-voltage input
stage with adjustable gain. The high input impedance of the TAS5414A and TAS5424A allows the use of
low-cost 1-μF input capacitors while still achieving extended low-frequency response. The preamplifier is
powered by a dedicated, internally regulated supply, which gives it excellent noise immunity and channel
separation. Also included in the preamp are:
1. Mute Pop-and-Click Control—An audio input signal is reshaped and amplified as a step when a mute is
applied at the crest or trough of the signal. Such a step is perceived as a loud click. This is avoided in the
TAS5414A and TAS5424A by ramping the gain gradually when a mute or play command is received.
Another form of click and pop can be caused by the start or stopping of switching in a class-D amplifier.
The TAS5414A and TAS5424A incorporate a patented method to reduce the pop energy during the
switching startup and shutdown sequence. Fault conditions require rapid protection response by the
TAS5414A and the TAS5424A, which do not have time to ramp the gain down in a pop-free manner. The
device transitions into Hi-Z mode when an OV, UV, OC, OT, or DC fault is encountered. Also, activation
of the STANDBY pin may not be pop-free.
2. Gain Control—The four gain settings are set in the preamplifier via I2C control registers. The gain is set
outside of the global feedback resistors of the TAS5414A and the TAS5424A, thus allowing for stability in
the system under all load conditions and gain settings.
3. DC Offset Reduction Circuitry—Circuitry has been incorporated to reduce the dc offset. DC offset in
high-gain amplifiers can produce audible clicks and pops when the amplifier is started or stopped. The
offset reduction circuitry can be disabled or enabled via I2C.
Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5414A and TAS5424A, the modulator is an
advanced design with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation
capability. The patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of
PWMs when the input signal exceeds the modulator waveform.
Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power
FET stage. The TAS5414A and TAS5424A use patent-pending techniques to avoid shoot-through and are
optimized for EMI and audio performance.
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DESCRIPTION OF OPERATION (continued)
Power FETs
The BTL output for each channel comprises four rugged N-channel 30-V FETs, each of which has an RDSon of
75 mΩ for high efficiency and maximum power transfer to the load. These FETs are designed to handle large
voltage transients during load dump.
Load Diagnostics
The TAS5414A and TAS5424A incorporate load diagnostic circuitry designed to help pinpoint the nature of
output misconnections during installation. The TAS5414A and the TAS5424A include functions for detecting and
determining the status of output connections. The following diagnostics are supported:
• Short to GND
• Short to PVDD
• Short across load (R < 1 Ω, typical)
• Open load (R > 800 Ω, typical)
• Tweeter detection
The presence of any of the short or open conditions is reported to the system via I2C register read. The tweeter
detect status can be read from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics—The TAS5414A and TAS5424A contain circuitry designed to
detect shorts and open conditions on the outputs. The load diagnostic function can only be invoked when
the output is in the Hi-Z mode. There are four phases of test during load diagnostics and two levels of
test. In the full level, all channels must be in the Hi-Z state. All four phases are tested on each channel, all
four channels at the same time. When fewer than four channels are in Hi-Z, the reduced level of test is
the only available option. In the reduced level, only short to PVDD and short to GND can be tested. Load
diagnostics can occur at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is
already in play mode, it must Mute and then Hi-Z before the load diagnostic can be performed. By
performing the mute function, the normal pop- and click-free transitions occur before the diagnostics
begin. The diagnostics are performed as shown in Figure 13. Figure 14 shows the impedance ranges for
the open-load and shorted-load diagnostics. The results of the diagnostic are read from the diagnostic
register for each channel via I2C. Note: Do not send a command via I2C to register 0x0C during the load
diagnostic test.
Hi-Z
Channel Synchronization
Playback
/
Mute
OUT1_M
Phase1
Phase2
Phase3
Phase4
S2G
S2P
OL
SL
OUT1_P
VSpeaker
(OUT1_P – OUT1_M)
100 ms
~50 ms
~50 ms
~50 ms
~50 ms
100 ms
150 ms
~50 ms
~50 ms
~50 ms
~50 ms
150 ms
<100 ms
T0188-01
Figure 13. Load Diagnostics Sequence of Events
16
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DESCRIPTION OF OPERATION (continued)
Short Detection
Range
Short Detected
Open Detection
Range
Normal Load Detected
Open Detected
RLoad
(Including Wires)
1.5
0.5
300
1 (Typ)
1300
800 (Typ)
M0067-01
Figure 14. Open and Shorted Load Detection
2. Tweeter Detection—The tweeter detection function is an ac diagnostic used to determine proper
connection of the tweeter when a passive crossover is used. The proper implementation of this diagnostic
function is dependent on the amplitude of a user-supplied test signal and on the impedance vs frequency
curve of the acoustic package. The tweeter function is invoked via I2C, and all four channels should be
tested individually. The tweeter detection uses the average cycle-by-cycle current limit circuit (see CBC
section) to measure the current to the load. The current level for the tweeter detection threshold is
typically 550 mA. The system (external to the TAS5414A and TAS5424A) must generate a tone burst in
the 10-kHz to 25-kHz range. If the tone burst employs a frequency higher than 20 kHz, and if a sufficiently
smooth amplitude ramp is used, the tweeter detection signal is silent. The frequency and amplitude of this
tone burst must be calibrated by the user to result in a current draw greater than the selected threshold
level when the tweeter is present. The tweeter detection results are monitored on the CLIP_OTW pin
during the application of the test tone. If the current threshold is attained during measurement, the tweeter
is present; then the CLIP_OTW pin is asserted. When the tweeter detector is activated, pulses on the
CLIP_OTW pin begin to toggle at 250 kHz to 500 kHz. As the detection signal gets stronger due to higher
load current, the density (or duty cycle) of the pulses increases.
Protection and Monitoring
1. Cycle-By-Cycle Current Limit (CBC)—The CBC current-limiting circuit terminates each PWM pulse to
limit the output current flow when the average current limit (ILIM) threshold is exceeded. The overall effect
on the audio in the case of a current overload is quite similar to a voltage-clipping event, where power is
temporarily limited at the peaks of the musical signal and normal operation continues without disruption
when the overload is removed. The TAS5414A and TAS5424A do not prematurely shut down in this
condition. All four channels continue in play mode and pass signal.
2. Overcurrent Shutdown (OCSD)—Under severe short-circuit events, such as a short to PVDD or ground,
a peak-current detector is used, and the affected channel shuts down in 200 μs to 390 μs if the conditions
are severe enough. The shutdown speed depends on a number of factors, such as the impedance of the
short circuit, supply voltage, and switching frequency. Only the shorted channels are shut down in such a
scenario. The user may restart the affected channel via I2C. An OCSD event activates the fault pin, and
the affected channel(s) are recorded in the I2C fault register. If the supply or ground short is strong
enough to exceed the peak current threshold but not severe enough to trigger the OCSD, the peak
current limiter prevents excess current from damaging the output FETs, and operation returns to normal
after the short is removed.
3. DC Detect—This circuit detects a dc offset continously during normal operation at the output of the
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DESCRIPTION OF OPERATION (continued)
4.
5.
6.
7.
18
amplifier. If the dc offset reaches the level defined in the I2C registers for the specified time period, the
circuit triggers. By default a dc detection event does not shut the output down. The shutdown function can
be enabled or disabled via I2C. If enabled, the triggered channel shuts down, but the others remain
playing and the FAULT pin is asserted. The positive dc level and negative dc level are defined in I2C
registers and can have separate thresholds.
Clip Detect—The clip detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a
clipped waveform. When this occurs, a signal is passed to the CLIP_OTW pin and it is asserted until the
100% duty-cycle PWM signal is no longer present. All four channels are connected to the same
CLIP_OTW pin. Through I2C, the CLIP_OTW signal can be changed to clip-only, OTW-only, or both. A
fourth mode, used only during diagnostics, is the option to report tweeter detection events on this pin (see
the Tweeter Detection section). The microcontroller in the system can monitor the signal at the
CLIP_OTW pin and may be configured to reduce the volume to all four channels in an active
clipping-prevention circuit.
Overtemperature Warning (OTW) and Overtemperature Shutdown (OTSD)—By default, the
CLIP_OTW pin is set to indicate an OTW. This can be changed via I2C commands. If selected to indicate
a temperature warning, the CLIP_OTW pin is asserted when the die temperature reaches 125°C. The
OTW has three temperature thresholds with a 10°C hysteresis. Each threshold is indicated in I2C register
0x04 bits 5, 6, and 7. The TAS5414A and TAS5424A still function until the temperature reaches the
OTSD threshold. 155°C, at which time the outputs are placed into Hi-Z mode and the FAULT pin is
asserted. I2C is still active in the event of an OTSD and the registers can be read for faults, but all audio
ceases abruptly. The OTSD resets at 145°C, to allow the TAS5414A/5424 to be turned back on through
I2C. The OTW is still indicated until the temperature drops below 115°C. All temperatures are nominal
values.
Undervoltage (UV) and Power-on-Reset (POR)—The undervoltage (UV) protection detects low voltages
on PVDD, AVDD, and CP. In the event of an undervoltage, the FAULT pin is asserted and the I2C
register is updated, depending on which voltage caused the event. Power-on-reset (POR) occurs when
PVDD drops low enough. A POR event causes the I2C to go into a high-impedance state. After the device
recovers from the POR event, the device must be re-initialized via I2C.
Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD
reaches the overvoltage threshold, the FAULT pin is asserted and the I2C register is updated. If the
voltage increases beyond the load dump threshold of 29 Vdc, the device shuts down and must be
restarted once the voltage returns to a safe value. After the device recovers from the ≈ load dump event,
the device must be re-initialized via I2C. The TAS5414A and TAS5424A can withstand 50-V load-dump
voltage spikes (see Figure 15). Also depicted in this graph are the voltage thresholds for normal operation
region, overvoltage operation region, and load-dump protection region. Figure 13 shows the regions of
operating voltage and the profile of the load dump event. Battery charger voltages from 25 V to 35 V can
be withstood for up to 1 hour.
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DESCRIPTION OF OPERATION (continued)
PVDD
50 V
100 ms
Max
50 V
Max Ramp Rate
25 V/ms
Load Dump Protection
29 V–50 V
2
I C Stop
Standby Mode
POR
2
I C Start
29 V
Overvoltage Protection Region
23 V–29 V
26 V
23 V
22 V
Hi-Z All Ch’s
14.4 V
Normal Operating Region
8 V–22 V
Ready to Get
Off Hi-Z State
Time
T0189-01
Figure 15. Voltage Operating Regions With Load Dump Transition Defined
Power Supply
The power for the device is most commonly provided by a car battery that can have a large voltage swing, 8 Vdc
to 18 Vdc. PVDD is a filtered battery voltage, and it is the supply for the output FETS and the low-side FET gate
driver. The high-side FET gate driver is supplied by a charge pump (CP) supply. The charge pump supplies the
gate drive voltage for all four channels. The analog circuitry is powered by AVDD, which is a provided by an
internal linear regulator. A 0.1μF/10V external bypass capacitor is needed at the A_BYP pin for this supply. It is
recommended that no external components except the bypass capacitor be attached to this pin. The digital
circuitry is powered by DVDD, which is provided by an internal linear regulator. A 0.1μF/10V external bypass
capacitor is needed at the D_BYP pin. It is recommended that no external components except the bypass
capacitor be attached to this pin.
The TAS5414A and TAS5424A can withstand fortuitous open ground and power conditions. Fortuitous open
ground usually occurs when a speaker wire is shorted to ground, allowing for a second ground path through the
body diode in the output FETs. The uniqueness of the diagnostic capabilities allows the speakers and speaker
wires to be debugged, eliminating the need to remove the amplifier to diagnose the problem.
I2C Serial Communication Bus
The TAS5414A and TAS5424A communicate with the system processor via the I2C serial communication bus.
The TAS5414A and TAS5424A are I2C slave-only devices. The processor can poll the TAS5414A and the
TAS5424A via I2C to determine the operating status of the device. All fault conditions and detections are
reported via I2C. There are also numerous features and operating conditions that can be set via I2C.
The I2C bus allows control of the following configurations:
• Independent gain control of each channel. The gain can be set to 12 dB, 20 dB, 26 dB, and 32 dB.
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DESCRIPTION OF OPERATION (continued)
•
•
•
•
•
•
•
•
Select current limit (for 2-Ω and for 4-Ω loads). This allows optimal design of the filter inductor, and the use of
smaller gauge speaker wires for 4-Ω applications.
Select AM non-interference switching frequency
Select the function of OTW_CLIP pin
Enable or disable dc detect function with selectable threshold
Place channel in Hi-Z (switching stopped) mode (mute)
Select tweeter detect, set detect threshold and initiate function
Initiate open/short load diagnostic
Reset faults and return to normal switching operation from Hi-Z mode (unmute)
In addition to the standard SDA and SCL pins for the I2C bus, the TAS5414A and the TAS5424A include a
single pin that allows up to four devices to work together in a system with no additional hardware required for
communication or synchronization. The I2C_ADDR pin sets the device in master or slave mode and selects the
I2C address for that device. Tie I2C_ADDR to DGND for master, to 1.2 Vdc for slave 1, to 2.4 Vdc for slave 2,
and to D_BYP for slave 3. The OSC_SYNC pin is used to synchronize the internal clock oscillators and thereby
avoid beat frequencies. An external oscillator can also be applied to this pin for external control of the switching
frequency.
Table 2. Table 7. I2C_ADDR Pin Connection
DESCRIPTION
TAS5414A/5424 0 (OSC
MASTER)
I2C_ADDR PIN CONNECTION
To SGND pin
I2C ADDRESS
0xD8/D9
TAS5414A/5424 1 (OSC SLAVE1) 35% DVDD (resistive voltage divider between D_BYP pin and SGND pin) (1)
0xDA/DB
TAS5414A/5424 2 (OSC SLAVE2) 65% DVDD (resistive voltage divider between D_BYP pin and SGND pin) (1)
0xDC/DD
TAS5414A/5424 3 (OSC SLAVE3) To D_BYP pin
0xDE/DF
(1)
RI2C_ADDR with 5% or better tolerance is recommended.
I2C Bus Protocol
The TAS5414A and TAS5424A have a bidirectional serial control interface that is compatible with the Inter IC
(I2C) bus protocol and supports 100-kbps data transfer rates for random and sequential write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte
(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop
conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 16. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication
with another device and then wait for an acknowledge condition. The TAS5414A and TAS5424A hold SDA LOW
during the acknowledge-clock period to indicate an acknowledgement. When this occurs, the master transmits
the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte).
All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external
pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. There is no limit on
the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the
master generates a stop condition to release the bus.
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SDA
R/
A
W
7-Bit Slave Address
7
5
6
4
3
2
1
8-Bit Register Address (N)
7
0
5
6
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
7
0
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
Figure 16. Typical I2C Sequence
Use the I2C_ADDR pin (pin 2) to program the device for one of four addresses. These four addresses are
licensed I2C addresses and do not conflict with other licensed I2C audio devices. To communicate with the
TAS5414A and the TAS5424A, the I2C master uses addresses shown in Figure 16. Read and write data can be
transmitted using single-byte or multiple-byte data transfers.
Random Write
As shown in Figure 17, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the TAS5414A or TAS5424A device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the internal memory address being accessed. After
receiving the address byte, the TAS5414A or TAS5424A again responds with an acknowledge bit. Next, the
master device transmits the data byte to be written to the memory address being accessed. After receiving the
data byte, the TAS5414A or TAS5424A again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 17. Random Write Transfer
Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master device to TAS5414A or TAS5424A as shown in Figure 17. After receiving each data
byte, the TAS5414A or TAS5424A responds with an acknowledge bit and the I2C subaddress is automatically
incremented by one.
Start
Condition
Acknowledge
A6
A5
2
A1
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
A6
A5
A4
A3
Subaddress
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 18. Sequential Write Transfer
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Random Read
As shown in Figure 19, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write
bit, the TAS5414A or TAS5424A responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5414A or
TAS5424A address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer.
After receiving the address and the read/write bit, the TAS5414A or TAS5424A again responds with an
acknowledge bit. Next, the TAS5414A or TAS5424A transmits the data byte from the memory address being
read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition
to complete the single-byte data-read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
2
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
I C Device Address and
Read/Write Bit
T0036-03
Figure 19. Random Read Transfer
Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the TAS5414A or TAS5424A to the master device as shown in Figure 20. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte and automatically
increments the I2C subaddress by one. Note: The fault registers do not have sequential read capabilities.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Subaddress
A0 ACK
A6
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 20. Sequential Read Transfer
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2
Table 3. TAS5414A/5424 I C Addresses
TAS5414A/5424 0
(OSC MASTER)
SELECTABLE WITH
ADDRESS PIN
FIXED ADDRESS
DESCRIPTION
READ/WRITE
BIT
I2C
ADDRESS
MSB
6
5
4
3
2
1
LSB
I2C WRITE
1
1
0
1
1
0
0
0
0xD8
I2C READ
1
1
0
1
1
0
0
1
0xD9
0xDA
2
TAS5414A/5424 1
(OSC SLAVE1)
I C WRITE
1
1
0
1
1
0
1
0
I2C READ
1
1
0
1
1
0
1
1
0xDB
TAS5414A/5424 2
(OSC SLAVE2)
I2C WRITE
1
1
0
1
1
1
0
0
0xDC
I2C READ
1
1
0
1
1
1
0
1
0xDD
TAS5414A/5424 3
(OSC SLAVE3)
I2C WRITE
1
1
0
1
1
1
1
0
0xDE
I2C READ
1
1
0
1
1
1
1
1
0xDF
Table 4. I2C Address Register Definitions
ADDRESS
R/W
REGISTER DESCRIPTION
0x00
R
Latched fault register 1, global and channel fault
0x01
R
Latched fault register 2, dc offset and overcurrent detect
0x02
R
Latched fault register 3, load diagnostics
0x03
R
Latched fault register 4, load diagnostics
0x04
R
External status register 1, temperature and voltage detect
0x05
R
External status register 2, Hi-Z and low-low state
0x06
R
External status register 3, mute and play modes
0x07
R
External status register 4, load diagnostics
0x08
R/W
External control register 1, channel gain select
0x09
R/W
External control register 2, dc offset reduction and current-limit select
0x0A
R/W
External control register 3, switching frequency and clip pin select
0x0B
R/W
External control register 4, load diagnostic, master mode select
0x0C
R/W
External control register 5, output state control
0x0D
R/W
External control register 6, output state control
0x0E
R/W
External control register 7, dc detect level select
0x0F
R/W
External control register 8, dc detect level select
Table 5. Fault Register 1 (0x00) Protection
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No protection-created faults, default value
FUNCTION
–
–
–
–
–
–
–
1
Overtemperature warning has occurred
–
–
–
–
–
–
1
–
DC offset has occurred in any channel
–
–
–
–
–
1
–
–
Overcurrent shutdown has occurred in any channel
–
–
–
–
1
–
–
–
Overtemperature shutdown has occurred
–
–
–
1
–
–
–
–
Charge pump undervoltage has occurred
–
–
1
–
–
–
–
–
AVDD, analog voltage, undervoltage has occurred
–
1
–
–
–
–
–
–
PVDD undervoltage has occurred
1
–
–
–
–
–
–
–
PVDD overvoltage has occurred
Table 6. Fault Register 2 (0x01) Protection
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No protection-created faults, default value
FUNCTION
–
–
–
–
–
–
–
1
Ovecurrent shutdown channel 1 has occurred
–
–
–
–
–
–
1
–
Overcurrent shutdown channel 2 has occurred
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Table 6. Fault Register 2 (0x01) Protection (continued)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
–
–
–
–
–
1
–
–
Overcurrent shutdown channel 3 has occurred
–
–
–
–
1
–
–
–
Overcurrent shutdown channel 4 has occurred
–
–
–
1
–
–
–
–
DC offset channel 1 has occurred
–
–
1
–
–
–
–
–
DC offset channel 2 has occurred
–
1
–
–
–
–
–
–
DC offset channel 3 has occurred
1
–
–
–
–
–
–
–
DC offset channel 4 has occurred
Table 7. Fault Register 3 (0x02) Load Diagnostics
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No load-diagnostic-created faults, default value
FUNCTION
–
–
–
–
–
–
–
1
Output short to ground channel 1 has occurred
–
–
–
–
–
–
1
–
Output short to PVDD channel 1 has occurred
–
–
–
–
–
1
–
–
Shorted load channel 1 has occurred
–
–
–
–
1
–
–
–
Open load channel 1 has occurred
–
–
–
1
–
–
–
–
Output short to ground channel 2 has occurred
–
–
1
–
–
–
–
–
Output short to PVDD channel 2 has occurred
–
1
–
–
–
–
–
–
Shorted load channel 2 has occurred
1
–
–
–
–
–
–
–
Open load channel 2 has occurred
Table 8. Fault Register 4 (0x03) Load Diagnostics
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No load-diagnostic-created faults, default value
FUNCTION
–
–
–
–
–
–
–
1
Output short to ground channel 3 has occurred
–
–
–
–
–
–
1
–
Output short to PVDD channel 3 has occurred
–
–
–
–
–
1
–
–
Shorted load channel 3 has occurred
–
–
–
–
1
–
–
–
Open load channel 3 has occurred
–
–
–
1
–
–
–
–
Output short to ground channel 4 has occurred
–
–
1
–
–
–
–
–
Output short to PVDD channel 4 has occurred
–
1
–
–
–
–
–
–
Shorted load channel 4 has occurred
1
–
–
–
–
–
–
–
Open load channel 4 has occurred
Table 9. External Status Register 1 (0x04) Fault Detection
24
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No protection-created faults are present, default value
FUNCTION
–
–
–
–
–
–
–
1
PVDD overvoltage fault is present
–
–
–
–
–
–
1
–
PVDD undervoltage fault is present
–
–
–
–
–
1
–
–
AVDD, analog voltage fault is present
–
–
–
–
1
–
–
–
Charge-pump voltage fault is present
–
–
–
1
–
–
–
–
Overtemperature shutdown is present
–
–
1
–
–
–
–
–
Overtemperature warning
–
1
1
–
–
–
–
–
Overtemperature warning level 1
1
0
1
–
–
–
–
–
Overtemperature warning level 2
1
1
1
–
–
–
–
–
Overtemperature warning level 3
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Table 10. External Status Register 2 (0x05) Output State of Individual Channels
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
1
Output is in Hi-Z mode, not in low-low mode(1), default value
–
–
–
–
–
–
–
0
Channel 1 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
–
–
0
–
Channel 2 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
–
0
–
–
Channel 3 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
0
–
–
–
Channel 4 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
1
–
–
–
–
Channel 1 low-low mode (0 = not low-low, 1 = low-low) (1)
–
–
1
–
–
–
–
–
Channel 2 low-low mode (0 = not low-low, 1 = low-low)(1)
–
1
–
–
–
–
–
–
Channel 3 low-low mode (0 = not low-low, 1 = low-low)(1)
1
–
–
–
–
–
–
–
Channel 4 low-low mode (0 = not low-low, 1 = low-low)(1)
(1)
FUNCTION
Low-low is defined as both outputs actively pulled to ground.
Table 11. External Status Register 3 (0x06) Play and Mute Modes
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
Mute mode is enabled, play mode disabled, default value
–
–
–
–
–
–
–
1
Channel 1 play mode is enabled
–
–
–
–
–
–
1
–
Channel 2 play mode is enabled
–
–
–
–
–
1
–
–
Channel 3 play mode is enabled
–
–
–
–
1
–
–
–
Channel 4 play mode is enabled
–
–
–
1
–
–
–
–
Channel 1 mute mode is disabled
–
–
1
–
–
–
–
–
Channel 2 mute mode is disabled
–
1
–
–
–
–
–
–
Channel 3 mute mode is disabled
1
–
–
–
–
–
–
–
Channel 4 mute mode is disabled
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No channels are set in load diagnostics mode, default value
–
–
–
–
–
–
–
1
Channel 1 is in load diagnostics mode
–
–
–
–
–
–
1
–
Channel 2 is in load diagnostics mode
–
–
–
–
–
1
–
–
Channel 3 is in load diagnostics mode
–
–
–
–
1
–
–
–
Channel 4 is in load diagnostics mode
X
X
X
X
–
–
–
–
Reserved
Table 12. External Status Register 4 (0x07) Load Diagnostics
FUNCTION
Table 13. External Control Register 1 (0x08) Gain Select
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
1
0
Set gain for all channels to 26 dB, default value
FUNCTION
–
–
–
–
–
–
0
0
Set channel 1 gain to 12 dB
–
–
–
–
–
–
0
1
Set channel 1 gain to 20 dB
–
–
–
–
–
–
1
1
Set channel 1 gain to 32 dB
–
–
–
–
0
0
–
–
Set channel 2 gain to 12 dB
–
–
–
–
0
1
–
–
Set channel 2 gain to 20 dB
–
–
–
–
1
1
–
–
Set channel 2 gain to 32 dB
–
–
0
0
–
–
–
–
Set channel 3 gain to 12 dB
–
–
0
1
–
–
–
–
Set channel 3 gain to 20 dB
–
–
1
1
–
–
–
–
Set channel 3 gain to 32 dB
0
0
–
–
–
–
–
–
Set channel 4 gain to 12 dB
0
1
–
–
–
–
–
–
Set channel 4 gain to 20 dB
1
1
–
–
–
–
–
–
Set channel 4 gain to 32 dB
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Table 14. External Control Register 2 (0x09) DC Offset Reduction and Current Limit
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
Enable dc offset reduction, set current limit to level 1
–
–
–
–
–
–
–
1
Disable channel 1 dc offset reduction
–
–
–
–
–
–
1
–
Disable channel 2 dc offset reduction
–
–
–
–
–
1
–
–
Disable channel 3 dc offset reduction
–
–
–
–
1
–
–
–
Disable channel 4 dc offset reduction
–
–
–
1
–
–
–
–
Set channel 1 current limit (0 = level 1, 1 = level 2)
–
–
1
–
–
–
–
–
Set channel 2 current limit (0 = level 1, 1 = level 2)
–
1
–
–
–
–
–
–
Set channel 3 current limit (0 = level 1, 1 = level 2)
1
–
–
–
–
–
–
–
Set channel 4 current limit (0 = level 1, 1 = level 2)
Table 15. External Control Register 3 (0x0A) Switching Frequency Select and Clip_OTW Configuration
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
1
1
0
1
Set fS = 417 kHz, configure clip and OTW, 45° phase, disable hard stop
–
–
–
–
–
–
0
0
Set fS = 500 kHz
–
–
–
–
–
–
1
0
Set fS = 357 kHz
–
–
–
–
–
–
1
1
Invalid frequency selection (do not set)
–
–
–
–
0
0
–
–
Configure CLIP_OTW pin for tweeter detect only
–
–
–
–
0
1
–
–
Configure CLIP_OTW pin for clip detect only
–
–
–
–
1
0
–
–
Configure CLIP_OTW pin for overtemperature warning only
–
–
–
1
–
–
–
–
Enable hard-stop mode
–
–
1
–
–
–
–
–
Set fS to a 180° phase difference between adjacent channels
X
X
–
–
–
–
–
–
Reserved
Table 16. External Control Register 4 (0x0B) Load Diagnostics and Master/Slave Control
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
0
Disable load diagnostics and dc detect SD, master mode
FUNCTION
–
–
–
–
–
–
–
1
Enable channel 1, load diagnostics
–
–
–
–
–
–
1
–
Enable channel 2, load diagnostics
–
–
–
–
–
1
–
–
Enable channel 3, load diagnostics
–
–
–
–
1
–
–
–
Enable channel 4, load diagnostics
–
–
–
1
–
–
–
–
Enable dc detect shutdown on all channels
–
–
1
–
–
–
–
–
Enable tweeter-detect mode
–
0
–
–
–
–
–
–
Enable slave mode (external oscillator must be provided)
X
–
–
–
–
–
–
–
Reserved
Table 17. External Control Register 5 (0x0C) Output Control
26
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
1
1
1
All channels, Hi-Z, mute, reset disabled
FUNCTION
–
–
–
–
–
–
–
0
Set channel 1 to mute mode, non-Hi-Z
–
–
–
–
–
–
0
–
Set channel 2 to mute mode, non-Hi-Z
–
–
–
–
–
0
–
–
Set channel 3 to mute mode, non-Hi-Z
–
–
–
–
0
–
–
–
Set channel 4 to mute mode, non-Hi-Z
–
–
–
0
–
–
–
–
Set non-Hi-Z channels to play mode, (unmute)
–
1
1
–
–
–
–
–
Reserved
1
–
–
–
–
–
–
–
Reset device (I2C does not respond with an ACK)
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Table 18. External Control Register 6 (0x0D) Output Control
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
Low-low state disabled all channels
–
–
–
–
–
–
–
1
Set channel 1 to low-low state
–
–
–
–
–
–
1
–
Set channel 2 to low-low state
–
–
–
–
–
1
–
–
Set channel 3 to low-low state
–
–
–
–
1
–
–
–
Set channel 4 to low-low state
X
X
X
X
–
–
–
–
Reserved
Table 19. External Control Register 7 (0x0E) Positive DC Detect Threshold Selection
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
0
0
0
1
1
1
0
Default positive dc detect value
0
1
1
0
0
1
0
1
Minimum positive dc detect value
X
X
X
X
X
X
X
X
See Figure 11 to set positive dc detect value
1
1
0
0
1
0
1
1
Maximum positive dc detect value
Table 20. External Control Register 8 (0x0F) Negative DC Detect Threshold Selection
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
1
1
0
1
Default negative dc detect value
FUNCTION
0
1
1
0
0
1
0
1
Minimum negative dc detect value
X
X
X
X
X
X
X
X
See Figure 12 to set negative dc detect value
0
0
0
0
0
0
0
0
Maximum negative dc detect value
Hardware Control Pins
The TAS5414A and TAS5424A incorporate four discrete hardware pins for real-time control and indication of
device status.
FAULT pin: This active-low, open-drain output pin indicates the presence of a fault condition that requires
the TAS5414A and TAS5424A to go automatically into the Hi-Z mode or standby mode. When this pin is
asserted high, the device has acted to protect itself and the system from potential damage. The exact nature
of the fault can be read via I2C with the exception of faults that are the result of PVDD voltage excursions
above 25 Vdc or below 5.5 Vdc. In these instances, the device goes into standby mode and the I2C bus is
no longer operational. However, the fault is still indicated due to the fact that the FAULT pin is open-drain
and active-high.
CLIP_OTW pin: The function of this active-high pin is configured by the user to indicate one of the following
conditions: overtemperature warning, the detection of clipping, or the logical OR of both of these conditions.
The configuration is selected via I2C. During tweeter detect diagnostics, this pin also is asserted when a
tweeter is present.
MUTE pin: This active-low pin is used for hardware control of the mute/unmute function for all four channels.
Capacitor CMUTE is used to control the time constant for the gain ramp needed to produce a pop- and
click-free mute function. For pop- and click-free operation, the mute function should be implemented through
I2C commands. The use of a hard mute with an external transistor does not ensure pop- and click-free
operation, and is not recommended unless an emergency hard mute function is required in case of a loss of
I2C control. The value of CMUTE must be 330 nF for proper pop- and click-free operation.
STANDBY pin: When this active-low pin is asserted, the device goes into a complete shutdown, and current
draw is limited to 2 μA, typical. This is pin typically asserted when the car ignition is in the off position. It can
also be used to shut down the device rapidly when certain operating conditions are violated. All I2C register
content is lost when this pin is asserted. The I2C bus goes into the high-impedance state when the
STANDBY pin is asserted.
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EMI Considerations
Automotive level EMI performance depends on both careful integrated circuit design and good system level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
TAS5414A and TAS5424A design.
The TAS5414A and TAS5424A have minimal parasitic inductances due to the short leads on the PSOP3
package. This dramatically reduces the EMI that results from current passing from the die to the system PCB.
Each channel of the TAS5414A and TAS5424A also operates at a different phase. The phase between channels
is I2C selectable to either 45° or 180°, to reduce EMI caused by high-current switching. The TAS5414A and
TAS5424A incorporate patent-pending circuitry that optimizes output transitions that cause EMI.
AM Radio EMI Reduction
To reduce interference in the AM radio band, the TAS5414A and TAS5424A have the ability to change the
switching frequency via I2C commands. The recommended frequencies are listed in Table 21. The fundamental
frequency and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be
present due to the switching frequency being demodulated by the AM radio. To function properly, AM avoidance
requires the use of a 20-kΩ, 1% tolerance Rext resistor.
Table 21. Recommended Switching Frequencies for AM Mode Operation
US
EUROPEAN
AM FREQUENCY
(kHz)
SWITCHING
FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
SWITCHING
FREQUENCY
(kHz)
522-540
417
540–917
500
540–914
500
917–1125
417
914–1122
417
1125–1375
500
1122–1373
500
1375–1547
417
1373–1548
417
1547–1700
357
1548–1701
357
Operating States
The operating regions, or states, of the TAS5414A and TAS5424A are depicted in the following tables.
Table 22. Operating States and Supplies
OUTPUT FETS
CHARGE PUMP
OSCILLATOR
I2C
AVDD and DVDD
STANDBY
Hi-Z, floating
Stopped
Stopped
Stopped
OFF
Hi-Z
Hi-Z, weak pulldown
Active
Active
Active
ON
Mute
Switching at 50%
Active
Active
Active
ON
Normal operation
Switching with audio
Active
Active
Active
ON
STATE NAME
Table 23. Global Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
POR
Voltage fault
UV
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
LATCHED/
SELFCLEARING
All
FAULT pin
Hard mute (no ramp)
Standby
Self-clearing
Hi-Z, mute, normal
I2C + FAULT pin
MONITORING
MODES
Hi-Z
CP UV
Hi-Z
OV
Hi-Z
Load dump
OTW
OT
28
Thermal warning
Thermal fault
All
FAULT pin
Hi-Z, mute, normal
I2C + CLIP_OTW pin
Hi-Z, mute, normal
2
I C + FAULT pin
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Standby
None
None
Self-clearing
Hard mute
Standby
Self-clearing
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Table 24. Channel Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
LATCHED/
SELFCLEARING
Open/short
diagnostic
Diagnostic
Hi-Z (I2C activated)
I2C
None
None
Latched
Clipping online
Warning
Normal
CLIP_OTW pin
None
None
Self-clearing
CBC load current
limit
Online protection
Mute, normal
CLIP_OTW pin
Current limit
Start OC
timer
Self-clearing
OC fault
Output channel fault
Mute, normal
I2C + FAULT pin
Hard mute
Hi-Z
Latched
Hard mute
Hi-Z
Latched
DC detect
Normal
2
I C + FAULT pin
Min Rise Time
29 V to 50 V: 1 ms
50 V
LD
Detect
Load Dump
Protection
29 V–50 V
29 V
23 V
OV
Detect
OV Protection Region 23 V–29 V
22 V
Normal Operating Region 8 V–22 V
PVDD
FAULT
2
I C
CLK
Hard Stop
15 V
15 V
Time
OUTx_M (Filtered)
t0
t1
t2
Outputs
OV
Deglitch Pulled
Down
Time
T0190-01
Figure 21. Sequence of Events for Supply Transition Out of Normal Operating Region
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50 V
Load Dump
Protection
29 V–50 V
LD
Reset
26 V
OV Protection Region 23 V–29 V
OV
Reset
23 V
PVDD
Fault Does Not Reset Until Fault
Register 1 Is Read
FAULT
2
IC
CLK
Ready to Get
Out of Hi-Z
State
15-V OUTx_P or
OUTx_M (Filtered)
Time
t0 t1
Oscillator
Start-Up Time
Outputs
Pulled
Down
t2 t3
OV
Deglitch Time
T0191-01
Figure 22. Sequence of Events for Supply Transition Back Into Normal Operating Region
30
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Power Shutdown and Restart Sequence Control
tGAIN
tCM
tCM
tGAIN
HIZ_CTLx
(All Channels)
2
LOW_LOW_CTLx
(All Channels)
Internal I C Reset
When HIZ_CTLx = 1
MUTE_CTLx
(All Channels)
MUTE Pin
OUTx_P (Filtered)
(All Channels)
OUTx_M (Filtered)
(All Channels)
HIZ_MODx
LOW_LOW_MODx
PLAY_MODx
MUTE_MODx
T0192-01
Figure 23. Click- and Pop-Free Shutdown and Restart Sequence Timing Diagram
With Four Channels Sharing the Mute Pin
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tGAIN
tCM
tCM
tGAIN
HIZ_CTL1
HIZ_CTL2,3,4
2
Internal I C Reset
When HIZ_CTL1 = 1
LOW_LOW_CTL1
2
Internal I C Reset When
When HIZ_CTL2,3,4 = 1
LOW_LOW_CTL2,3,4
MUTE_CTL
MUTE Pin
OUT1_P
(Filtered)
"Pop"
"Pop"
OUT2,3,4_P
(Filtered)
T0193-01
Figure 24. Individual Channel Shutdown and Restart Sequence Timing Diagram
32
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Latched Fault Shutdown and Restart Sequence Control
tI2C_CL
tDEGLITCH
tDEGLITCH
PVDD
VUV + VUV_HY
UV
Detect
tGAIN
UV
Reset
tCM
PVDD Normal Operating Region
PVDD UV Hysteresis Region
VUV
VPOR
HIZ_CTLx
2
Internal I C Write
MUTE_CTL
UV_DET
Cleared by
2
UV_LATCH
External I C Read
to Fault Register 1
2
External I C Read
FAULT Pin
MUTE Pin
OUTx_P (Filtered)
“Pop”
T0194-01
Figure 25. Latched Global Fault Shutdown and Restart Timing Diagram
(UV Shutdown and Recovery)
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tI2C_CL
tDEGLITCH
tDEGLITCH
PVDD
VUV + VUV_HY
UV
Detect
tCM
UV
Reset
tGAIN
PVDD Normal Operating Region
PVDD UV Hysteresis Region
VUV
VPOR
2
HIZ_CTL1
Internal I C Write
HIZ_CTL2,3,4
MUTE_CTL
UV_DET
Cleared by
2
UV_LATCH
External I C Read
to Fault Register 1
2
External I C Read
FAULT Pin
MUTE Pin
OUT1_P (Filtered)
OUT2,3,4_P (Filtered)
“Pop”
“Pop”
“Pop”
T0195-01
Figure 26. Latched Global Fault Shutdown and Individual Channel Restart Timing Diagram
(UV Shutdown and Recovery)
34
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GND
System
Microprocessor
9
6
RLV
RRV
VSSA2 10
FRV 13
FLV 16
VREFDA
Optional
4.7uF
RC Filter
RC Filter
12
11
10
9
8
7
1uF
1uF
1uF
1uF
1uF
18
17
16
15
14
100nF 13
20kW
1%
100nF
RC Filter
RC Filter
330nF
6
5
4
3
2
1
IN4_P
IN3_P
IN_M
IN2_P
IN1_P
A_BYP
REXT
SGND
GND
CLIP_OTW
D_ BYP
STANDBY
MUTE
FAULT
SCL
SDA
I2C_ ADDR
Reverse
Battery
Protection
PVDD
PVDD
OUT4_P
OUT4_M
PGND
OUT3_P
OUT3_M
PGND
CPC_ BOT
CP
CPC_ TOP
OUT2_P
OUT2_M
PGND
OUT1_P
OUT1_M
PVDD
PVDD
19
20
21
22
23
24
25
26
27
28
29
5.6W
5.6W
5.6W
5.6W
30 5.6W
31 5.6W
32
33 5.6W
34 5.6W
35
36
Vehicle Negative
Lead (Gnd)
OSC_ SYNC
VBATT
8V–22V
"0": V0 (to SGND) (OSC Master Default)
"1": V1 (OSC Slave 1)
"2": V2 (OSC Slave 2)
"3": V3 (to D_BYP) (OSC Slave 3)
3.3V–5V
FAST MUTE
PGND
Radio DSP
SGND
Pull-up
Resistors
Ground Plane
Additional
TAS5414A Sync
Additional
TAS5414A Sync
Additional
TAS5414A Sync
+
1nF
1nF
1nF
1nF
A
1nF
1nF
1nF
1nF
1uF
A
1uF
10uH
10uH
10uH
10uH
A
10uH
10uH
10uH
10uH
4.7uF 4.7uF 82nF 2.2nF
Vehicle Positive
Lead
0.47uF
0.47uF
0.47uF
0.47uF
10uH
150 nF
150nF
150 nF
150nF
150nF
150nF
150nF
150nF
1W
1W
1W
1W
1W
1W
1W
1W
1000uF 1000uF 100nF
1nF
1nF
1nF
1nF
1nF
1nF
1nF
1nF
100nF
A
S0235-02
4W
4W
4W
4W
TAS5414A, TAS5424A
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APPLICATION INFORMATION
Figure 27. TAS5414A Application Schematic
35
Figure 28. TAS5424A Typical Application Schematic
GND
System
Microprocessor
SGND
Ground Plane
FAST MUTE
PGND
Optional
330nF
9
12
11
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15
17
21
1uF 22
1uF
IN4_M
IN4_P
PVDD
PVDD
PVDD
1uF 20 IN3_M
OUT4_M
PGND
PGND
OUT3_P
OUT3_M
PGND
CPC_ BOT
CP
CPC_ TOP
OUT2_P
OUT2_M
PGND
PGND
OUT1_P
OUT1_M
PVDD
PVDD
PVDD
OUT4_P
IN2_M
IN2_P
IN1_M
IN1_P
A_ BYP
REXT
SGND
GND
CLIP_OTW
D_ BYP
STANDBY
GND
MUTE
FAULT
SCL
SDA
I2C_ ADDR
OSC_ SYNC
Vehicle Negative
Lead (GND)
Reverse
Battery
Protection
IN3_P
1uF
19
1uF 18
1uF
1uF 16
1uF
100nF14
20kW, 1% 13
100nF
8
7
6
5
4
3
2
1
10
VBATT
8V–22V
"0": V0 (to SGND) (OSC Master Default)
"1": V1 (OSC Slave 1)
"2": V2 (OSC Slave 2)
"3": V3 (to D_BYP) (OSC Slave 3)
Additional
TAS5424A Sync
Additional
TAS5424A Sync
Additional
TAS5424A Sync
Pull-up
Resistors
36
Audio Inputs
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Vehicle Positive
Lead
5.6W
A
5.6W
5.6W
5.6W
5.6W
5.6W
5.6W
5.6W
A
1nF
1nF
1nF
1nF
1uF
1nF
1nF
1nF
1nF
1uF
10uH
10uH
10uH
10uH
A
10uH
10uH
10uH
10uH
4.7uF 4.7uF 82nF 2.2nF
0.47uF
0.47uF
0.47uF
0.47uF
10uH
150nF
150nF
150nF
150nF
150nF
150nF
150nF
150nF
1W
1W
1W
1W
1W
1W
1W
1W
1000uF 1000uF 100nF
1nF
1nF
1nF
1nF
1nF
1nF
1nF
1nF
100nF
A
S0236-02
4W
4W
4W
4W
TAS5414A, TAS5424A
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APPLICATION INFORMATION (continued)
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SLOS535 – JUNE 2007
APPLICATION INFORMATION (continued)
Parallel Operation (PBTL)
TAS5414A and TAS5424A can be used to drive four 4Ω loads, two 2Ω loads, or even one 1Ω load by paralleling
BTL channels on the load side of the LC output filter. For parallel operation, identical I2C settings are required
for any two paralleled channels (especially gain and current-limit settings) in order to have reliable system
performance and evenly dissipated power on multiple channels. Having identical gain and current-limit settings
can also prevent energy feeding back from one channel to the other. For smooth power up, power down, and
mute operation, the same control commands (such as mute, play, Hi-Z, etc.) should be sent to the paralleled
channels at the same time. Load diagnostic is also supported for parallel connection. Paralleling on the
TAS5414A and TAS5424A side of the LC output filter is not supported, and can result in device failure.
DEMODULATION FILTER DESIGN
The TAS5414A and TAS5424A amplifier outputs are driven by high-current LDMOS transistors in an H-bridge
configuration. These transistors are either off or fully on. The result is a square-wave output signal with a duty
cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be
used to recover the audio signal. The main purpose of the demodulation filter is to attenuate the high-frequency
components of the output signals that are out of the audio band. Design of the demodulation filter significantly
affects the audio performance of the power amplifier. Therefore, to meet the device THD+N specification, the
selection of the inductors used in the output filter should be carefully considered. The rule is that the inductance
should remain stable within the range of peak current seen at maximum output power and deliver approximately
5 μH of inductance at 16 A. If this rule is observed, the TAS5414A and TAS5424A should not have distortion
issues due to the output inductors. Another parameter to be considered is the idle-current loss in the inductor.
This can be measured or specified as inductor dissipation (D). The target specification for dissipation is less than
0.05. If the dissipation factor is above this value, idle current increases. In general, 10-μH inductors suffice for
most applications. The frequency response of the amplifier is slightly altered by the change in output load
resistance; however, unless tight control of frequency response is necessary (better than 0.5 dB), it is not
necessary to deviate from 10 μH.
THERMAL INFORMATION
The thermally augmented package provided with the TAS5414A and TAS5424A is designed to interface directly
to heat sinks using a thermal interface compound (for example, Artic Silver, Ceramique thermal compound.) The
heat sink then absorbs heat from the ICs and couples it to the local air. If louvers or fans are supplied, this
process can reach equilibrium and heat can be continually removed from the ICs. Because of the efficiency of
the TAS5414A and TAS5424A, heat sinks can be smaller than those required for linear amplifiers of equivalent
performance.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
• RθJC (the thermal resistance from junction to case, or in this case the heat slug)
• Thermal grease thermal resistance
• Heat sink thermal resistance
The thermal grease thermal resistance can be calculated from the exposed heat slug area and the thermal
grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The area thermal
resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about 0.007°C-in2/W
(4.52°C-mm2/W). The approximate exposed heat slug size is as follows:
TAS5424A, 44-pin PSOP3 …………………. 0.124 in2 (80 mm2)
TAS5414A, 36-pin PSOP3 …………………. 0.124 in2 (80 mm2)
Dividing the example thermal grease area resistance by the area of the heat slug gives the actual resistance
through the thermal grease for both parts:
TAS5424A, 44-pin PSOP3 ………………… 0.40°C/W
TAS5414A, 36-pin PSOP3 ………………… 0.40°C/W
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APPLICATION INFORMATION (continued)
The thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink thermal resistance
generally is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or
measured.
Thus, for a single monaural channel in the IC, the system RθJA = RθJC + thermal grease resistance + heat sink
resistance.
The following table indicates modeled parameters for one TAS5414A or TAS5424A IC on a heat sink. The
junction temperature is set at 115°C in both cases while delivering 20 Wrms per channel into 4-Ω loads with no
clipping. It is assumed that the thermal grease is about 0.001 inches (0.0254 mm) thick (this is critical).
Device
TAS5414A, 36-Pin PSOP3
Ambient temperature
25°C
Power to load
20 W × 4
Power dissipation
1.90 W × 4
∆T inside package
7.6°C
∆T through thermal grease
3°C
Required heatsink thermal resistance
10.45°C/W
Junction temperature
115°C
System RθJA
11.85°C/W
RθJA × power dissipation
90°C
As an indication of the importance of keeping the thermal grease layer thin, if the thermal grease layer increases
to 0.002 inches (0.0508 mm) thick, the required heat sink thermal resistance changes to 6°C/W for the PSOP3.
38
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TAS5414ATDKDMQ1
ACTIVE
SSOP
DKD
36
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5414ATDKDMQ1G4
ACTIVE
SSOP
DKD
36
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5414ATDKDQ1
ACTIVE
SSOP
DKD
36
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5414ATDKDQ1G4
ACTIVE
SSOP
DKD
36
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5414ATDKDRMQ1
ACTIVE
SSOP
DKD
36
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5414ATDKDRMQ1G4
ACTIVE
SSOP
DKD
36
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5414ATDKDRQ1
ACTIVE
SSOP
DKD
36
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5414ATDKDRQ1G4
ACTIVE
SSOP
DKD
36
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDMQ1
ACTIVE
SSOP
DKD
44
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDMQ1G4
ACTIVE
SSOP
DKD
44
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDQ1
ACTIVE
SSOP
DKD
44
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDQ1G4
ACTIVE
SSOP
DKD
44
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDRMQ1
ACTIVE
SSOP
DKD
44
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDRMQ1G4
ACTIVE
SSOP
DKD
44
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDRQ1
ACTIVE
SSOP
DKD
44
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
TAS5424ATDKDRQ1G4
ACTIVE
SSOP
DKD
44
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TAS5414ATDKDRMQ1
DKD
36
SITE 60
330
24
14.7
16.4
4.0
20
24
Q1
TAS5414ATDKDRQ1
DKD
36
SITE 60
330
24
14.7
16.4
4.0
20
24
Q1
TAS5424ATDKDRMQ1
DKD
44
SITE 60
330
24
14.7
16.4
4.0
20
24
Q1
TAS5424ATDKDRQ1
DKD
44
SITE 60
330
24
14.7
16.4
4.0
20
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TAS5414ATDKDRMQ1
DKD
36
SITE 60
367.0
367.0
45.0
TAS5414ATDKDRQ1
DKD
36
SITE 60
367.0
367.0
45.0
TAS5424ATDKDRMQ1
DKD
44
SITE 60
367.0
367.0
45.0
TAS5424ATDKDRQ1
DKD
44
SITE 60
367.0
367.0
45.0
Pack Materials-Page 2
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