Preliminary 2004.01.09 FUJITSU SEMICONDUCTOR DATA SHEET 16-bit Proprietary Microcontroller CMOS R MB90335 Series MB90337/F337/V330A ■ DESCRIPTION The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also MiniHost operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the AT architecture of the F2MC* family, the instruction set supports the C language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator. * : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. ■ FEATURES • Clock • Built-in oscillation circuit and PLL clock frequency multiplication circuit • Oscillation clock The machine clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz) Clock for USB is 48 MHz Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable • Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock 24 MHz and at operating VCC = 3.3 V) • The maximum memory space:16 MB • 24-bit addressing • Bank addressing (Continued) ■ PACKAGE 64-pin plastic LQFP (FPT-64P-M09) MB90335 Series (Continued) • Instruction system Data types: Bit, Byte, Word, Long word Addressing mode (23 types) Enhanced high-precision computing with 32-bit accumulator Enhance Multiply/Divide instructions with sign and the RETI instruction • Instruction system compatible with high-level language (C language) and multitask • Employing system stack pointer • Instruction set symmetry and barrel shift instructions • Program Patch Function (2 address pointer) • 4-byte instruction queue • Interrupt function • Priority levels are programmable • 20 interrupts • Data transfer function • Expanded intelligent I/O service function (EI2OS) : Maximum of 16 channels • µDMAC : Maximum 16 channels • Low Power Consumption Mode • Sleep mode (with the CPU operating clock stopped) • Time - base timer mode (with the oscillator clock and time - base timer operating) • Stop mode (with the oscillator clock stopped) • CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles) • Package • LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch) • Process : CMOS technology • Operation guaranteed temperature: −40 °C to +85 °C (0 °C to +70 °C when USB is in use) 2 Preliminary 2004.01.09 Preliminary 2004.01.09 MB90335 Series ■ INTERNAL PERIPHERAL FUNCTION (RESOURCE) • I/O port: Max 45 ports • Time-base timer : 1channel • Watchdog timer : 1 channel • 16-bit reload timer : 1 channel • Multi-functional timer • 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse can be set by the program. • 16-bit PWC timer : 1 channel Timer function and pulse width measurement function • UART : 2 channels • Equipped with Full duplex double buffer with 8-bit lenghth • Asynchronous transfer or clock-synchronous serial (I/O extended serial) transfer can be set. • Extended I/O serial interface: 1 channel • DTP/External interrupt circuit (8 channels) • Activate the extended intelligent I/O service by external interrupt input • Interrupt output by external interrupt input • Delayed interrupt output module • Output an interrupt request for task switching • USB : 1 channel • USB function (conform to USB 2.0 Full Speed) • Supports for Full Speed/Endpoint are specifiable up to six. • Dual port RAM (The FIFO mode is supported). • Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible • USB Mini Host function • I2C Interface : 1 channel • Supports Intel SM bus standards and Phillips I2C bus standards • Two-wire data transfer protocol specification • Master and slave transmission/reception Note : I2C licenae : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Phillips. 3 Preliminary 2004.01.09 MB90335 Series ■ PRODUCT LINEUP 1. MB90335 Series Part number Type MB90V330A MB90F337 MB90337 For evaluation Built-in FLASH MEMORY Built-in Mask ROM ROM capacity No 64 Kbyte RAM capacity 28 Kbyte 4 Kbyte Emulator-specific power supply * Used bit CPU functions Number of basic instructions Minimum instruction execution time Addressing type Program Patch Function maximum memory space : 351 instructions : 41.6 ns / at oscillation of 6 MHz (When 4 times is used : Machine clock of 24 MHz) : 23 types : For two address pointers : 16 Mbyte Ports I/O Ports(CMOS) 45 ports UART Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable. It can also be used for I/O serial. Built-in special baud-rate generator Built-in 2 channels 16-bit reload timer 16-bit reload timer operation Built-in 1 channel Multi-functional timer 8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels) 16-bit PWC timer × 1 channel DTP/External interrupt 8 channels Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable I2C 1 channel Extended I/O serial interface 1 channel USB 1 channel USB function (conform to USB 2.0 Full Speed) USB Mini-HOST function Withstand voltage of 5 V 6 ports (Excluding VBUS and I/O for I2C) Low Power Consumption Mode Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode Process CMOS Operating voltage VCC 3.3 V ± 0.3 V (at maximum machine clock 24 MHz) * : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB214701 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. ■ PACKAGES AND PRODUCT MODELS Package MB90337 MB90F337 × FPT-64P-M09 (LQFP-0.65 mm) PGA-299C-A01 (PGA) : Yes × × × : No Note : For detailed information on each package, see “■ PACKAGE DIMENSIONS”. 4 MB90V330A Preliminary 2004.01.09 MB90335 Series ■ PIN ASSIGNMENT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P51 P41/TOT0 P40/TIN0 P67/INT7/SDA0 P66/INT6/SCL0 P65/INT5/PWC P64/INT4/SCK P63/INT3/SOT P62/INT2/SIN P61/INT1 P60/INT0 P27/PPG3 P26/PPG2 P25/PPG1 P50 Vcc (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vss X1 X0 P24/PPG0 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P52 P53 Vss MD2 MD1 MD0 RST P54 P00 P01 P02 P03 P04 P05 P06 P07 VBUS Vss DVM DVP Vcc Vss HVM HVP Vcc HCONX P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 (FPT-64P-M09) 5 Preliminary 2004.01.09 MB90335 Series ■ PIN DESCRIPTION Pin no. Status at reset/ function Pin name Circuit type* 46 , 47 X0, X1 A It is a terminal which connects the oscillator. Oscillation When connecting an external clock, leave the X1 pin side unconstatus nected. 23 RST F Reset input External reset input pin. QFPM09 25 to 32 P00 to P07 Function I General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1) by the pull-up resistor setting register (RDR0). (When the power output is set, it is invalid.) 33 to 40 P10 to P17 I General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD10 to RD17 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.) 41 to 44 P20 to P23 D General purpose input/output port. 45 P24 PPG0 D P25 to P27 51 to 53 62 63 11 12 13 14 15 16 PPG1 to PPG3 P40 TIN0 P41 TOT0 P42 SIN0 P43 SOT0 P44 SCK0 P45 SIN1 P46 SOT1 P47 SCK1 General purpose input/output port. Functions as output pins of PPG timers ch0. General purpose input/output port. D H H H H H H H H Functions as output pins of PPG timers ch1 to ch3. General purpose input/output port. Function as event input pin of 16-bit reload timer. General purpose input/output port. Port input Function as output pin of 16-bit reload timer. (High-Z) General purpose input/output port. Functions as a data input pin for UART ch0. General purpose input/output port. Functions as a data output pin for UART ch0. General purpose input/output port. Functions as a clock I/O pin for UART ch0. General purpose input/output port. Functions as a data input pin for UART ch1. General purpose input/output port. Functions as a data output pin for UART ch1. General purpose input/output port. Functions as a clock I/O pin for UART ch1. 50 P50 K General purpose input/output port. 64 P51 K General purpose input/output port. 17, 18 P52, P53 K General purpose input/output port. 24 P54 K General purpose input/output port. * : For circuit information, see “■ I/O CIRCUIT TYPE”. (Continued) 6 Preliminary 2004.01.09 MB90335 Series (Continued) Pin no. QFPM09 54, 55 Pin name P60, P61 INT0, INT1 Circuit type* Status at reset/ function General purpose input/output port. (withstand voltage of 5 V) C Functions as the input pin for external interrupt ch0 and ch1. P62 56 57 58 INT2 General purpose input/output port. (withstand voltage of 5 V) C Functions as the input pin for external interrupt ch2. SIN Data input pin for simple serial IO. P63 General purpose input/output port. (withstand voltage of 5 V) INT3 C Functions as the input pin for external interrupt ch3. SOT Data output pin for simple serial IO P64 General purpose input/output port. (withstand voltage of 5 V) INT4 C SCK INT5 Functions as the input pin for external interrupt ch4. Port input (High-Z) P65 59 C Clock I/O pin for simple serial IO. General purpose input/output port. (withstand voltage of 5 V) Functions as the input pin for external interrupt ch5. PWC Functions as the PWC input pin. P66 General purpose input/output port. INT6 60 Functions as the input pin for external interrupt ch6. C Functions as the input/output pin for I2C interface clock. The port output must be placed in High-Z state during I2C interface operation. SCL0 P67 61 Function INT7 General purpose input/output port. Functions as the input pin for external interrupt ch7. C Functions as the I2C interface data input/output pin. The port output must be placed in High-Z state during I2C interface operation. SDA0 1 VBUS C VBUS input Status detection pin of USB cable. 3 DVM J USB function D − pin. 4 DVP J 7 HVM J USB input USB function D + pin. (SUSPEND) USB Mini Host D − pin. 8 HVP J USB Mini Host D + pin. 10 HCONX E High output External pull-up resistor connection pin. 21, 22 MD1, MD0 B 20 MD2 G Mode input Input pin for selecting operation mode. Pin 5 Vcc Power supply pin. 9 Vcc Power supply pin. 49 Vcc Power supply pin. Power supply 2 Vss 6 Vss 19 Vss Power supply pin (GND). 48 Vss Power supply pin (GND). Power supply pin (GND). Power supply pin (GND). * : For circuit information, see “■ I/O CIRCUIT TYPE”. 7 Preliminary 2004.01.09 MB90335 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks X1 Clock input A • Oscillation feedback resistance : approx. 1 MΩ • With standby control X0 Standby control signal • CMOS hysteresis input B Hysteresis input • Hysteresis input • Nch open drain output Nch Nout C Hysteresis input Standby control signal Pch Pout Nch Nout D Hysteresis input Standby control signal • CMOS output • CMOS hysteresis input (With input interception function at standby) Note : • The I/O ports and internal resources share one output buffer for their outputs. • The I/O port and internal resources share one input buffer for their input. • CMOS output Pch Pout Nch Nout E • CMOS hysteresis input with pull-up • Resistor approx. 50 kΩ F G Hysteresis input Hysteresis input • CMOS hysteresis input with pull-down • Resistor approx. 50 kΩ • FLASH product is not provided with pull-down resistor. (Continued) 8 Preliminary 2004.01.09 MB90335 Series (Continued) Type Circuit H Remarks Pch Pout Nch Nout Open drain control signal • CMOS output • CMOS hysteresis input (With input interception function at standby) With open drain control signal Hysteresis input Standby control signal • CMOS output • CMOS input (With input interception function at standby) Programmable pull-up Resistor approx. 50 kΩ CTL I Pch Pout Nch Nout CMOS input Standby control signal • USB I/O pin D + input D-input D+ Differential input D− Full D + output J Full D-output Low D + output Low D-output Direction Speed K Pch Pout Nch Nout • CMOS output • CMOS input (With input interception function at standby) CMOS input Standby control signal 9 Preliminary 2004.01.09 MB90335 Series ■ HANDLING DEVICES 1. Preventing latchup and turning on power supply Latchup may occur on CMOS IC under the following conditions: 1. If a voltage higher than VCC or lower than VSS is applied to input and output pins. 2. A voltage higher than the rated voltage is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using CMOSICs, take great care to prevent the occurrence of latchup. 2. Treatment of unused pins Leaving unused input pins open may cause a malfunction. These pins must therefore be set to a pull-up or pulldown state. 3. About the attention when the external clock is used • Using external clock X0 OPEN X1 4. Treatment of power supply pins (VCC/VSS) When the device is provided with multiple VCC and VSS pins, be sure to connect all of the power pins to the power supply and ground outside the device to reduce latch-up and unwanted radiation, prevent the strobe signal from malfunctioning due to a rise of grand level, and to follow the standards of total output current for device design reasons. The power supply source should be connected to the VCC and VSS of this device at the lowest possible impedance. It is also advisable to connect a bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. 5. About crystal oscillator circuit Noise near the X0/X1 pin may cause the device to malfunction. When designing the artwork for a PC board using the microcontroller, it is strongly advisable to place the X0/X1 and crystal (ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible and prevent their writing patterns from crossing other patterns as possible be cause stable operation can be expected with such a layout. 6. Caution on Operations during PLL Clock Mode Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the PLL internal automatic oscillator circuit.Performance of this operation, however, cannot be guaranteed. 10 Preliminary 2004.01.09 MB90335 Series 7. Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. For stabilization reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply switching. 8. Writing to flash memory For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V. 11 Preliminary 2004.01.09 MB90335 Series ■ BLOCK DIAGRAM X0, X1 RST MD0 to MD2 Clock control circuit F2MC-16LX CPU Interrupt controller RAM 8/16-bit PPG timer ch0 to ch3* PPG0 to PPG3 16-bit PWC PWC SIO SIN SOT SCK ROM SIN0, SIN1 SOT0, SOT1 SCK0, SCK1 SCL0 SDA0 TOT0 TIN0 DVP DVM HVP HVM HCONX VBUS INT0 to INT7 Internal data bus UART/SIO ch0, ch1 I2C 16-bit reload timer µDMAC USB (Function) (Mini-HOST) External interrupt I/O port (port 0, 1, 2, 4, 5, 6) P00 P10 P20 P40 P50 P60 P07 P17 P27 P47 P54 P67 * : Channel for use in 8-bit mode. Two channels (ch1, ch3) are used in 16-bit mode. Note : I/O ports share pins with peripheral resources. For details, see “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”. Note also that pins used for peripheral resources cannot serve as I/O ports. 12 Preliminary 2004.01.09 MB90335 Series ■ MEMORY MAP Single chip mode (ROM mirror function) MB90V330A FFFFFFH MB90F337 FFFFFFH ROM (FF bank) FF0000H 00FFFFH 008000H 007FFFH 007900H ROM (FF bank) FF0000H 00FFFFH ROM area (image of FF bank) 008000H 007FFFH Peripheral area 007900H MB90337 FFFFFFH ROM (FF bank) FF0000H ROM area (image of FF bank) Peripheral area 00FFFFH 008000H 007FFFH 007900H ROM area (image of FF bank) Peripheral area 007100H RAM area (28 Kbytes) 000100H 001100H Register 0000FBH 000100H Register 0000FBH 001100H 000100H RAM area (4 Kbytes) Register 0000FBH Peripheral area Peripheral area 000000H RAM area (4 Kbytes) 000000H Peripheral area 000000H Memory Map of MB90335 Series Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H to FFFFFFH” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00. • For setting the ROM mirror function, see “16. ROM mirror function select module” in “■ PERIPHERAL RESOURCES”. Reference : • The ROM mirror function is for using the C compiler small model. • The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. • When the C compiler small model is used, the data table mirror image can be shown at “008000H to 00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area can be referenced without declaring the far addressing with the pointer. 13 Preliminary 2004.01.09 MB90335 Series ■ F2MC-16L CPU PROGRAMMING MODEL • Dedicated register AH Accumulator AL USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bit 16 bit 32 bit • General purpose registers MSB LSB 16 bit 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 • Processor status 13 12 15 PS 14 ILM 8 7 RP 0 CCR Preliminary 2004.01.09 MB90335 Series ■ I/O MAP Address Register abbreviation Read/ Write Resource name Initial Value 000000H PDR0 Port 0 Data Register R/W Port 0 XXXXXXXXB 000001H PDR1 Port 1 Data Register R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 Data Register R/W Port 2 XXXXXXXXB Register 000003H Prohibited 000004H PDR4 Port 4 Data Register R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 Data Register R/W Port 5 - - - XXXXXB 000006H PDR6 Port 6 Data Register R/W Port 6 XXXXXXXXB 000007H to 00000FH Prohibited 000010H DDR0 Port 0 Direction Register R/W Port 0 0 0 0 0 0 0 0 0B 000011H DDR1 Port 1 Direction Register R/W Port 1 0 0 0 0 0 0 0 0B 000012H DDR2 Port 2 Direction Register R/W Port 2 0 0 0 0 0 0 0 0B 000013H Prohibited 000014H DDR4 Port 4 Direction Register R/W Port 4 0 0 0 0 0 0 0 0B 000015H DDR5 Port 5 Direction Register R/W Port 5 - - - 0 0 0 0 0B 000016H DDR6 Port 6 Direction Register R/W Port 6 0 0 0 0 0 0 0 0B Port 4 (OD control) 0 0 0 0 0 0 0 0B 000017H to 00001AH Prohibited 00001BH ODR4 Port 4 Output Pin Register R/W 00001CH RDR0 Port 0 Pull-up Resistance Register R/W Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B 00001DH RDR1 Port 0 Pull-up Resistance Register R/W Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B 00001EH Prohibited 00001FH 000020H SMR0 Serial Mode Register ch0 R/W 0 0 1 0 0 0 0 0B 000021H SCR0 Serial Control Register ch0 R/W 0 0 0 0 0 1 0 0B SIDR0 Serial Input Data Register ch0 R SODR0 Serial Output Data Register ch0 W 000022H 000023H SSR0 000024H UART0 XXXXXXXXB Serial Status Register ch0 R/W 0 0 0 0 1 0 0 0B UTRLR0 UART Prescaler Reload Register ch0 R/W 000025H UTCR0 UART Prescaler Control Register ch0 R/W Communication 0 0 0 0 0 0 0 0B Prescaler (UART0) 0 0 0 0 - 0 0 0B 000026H SMR1 Serial Mode Register ch1 R/W 0 0 1 0 0 0 0 0B 000027H SCR1 Serial Control Register ch1 R/W 0 0 0 0 0 1 0 0B SIDR1 Serial Input Data Register ch1 R SODR1 Serial Output Data Register ch1 W 000028H 000029H SSR1 Serial Status Register ch1 R/W UART1 XXXXXXXXB 0 0 0 0 1 0 0 0B (Continued) 15 Preliminary 2004.01.09 MB90335 Series Address Register abbreviation Read/ Write 00002AH UTRLR1 UART Prescaler Reload Register ch1 R/W 00002BH UTCR1 UART Prescaler Control Register ch1 R/W Communication 0 0 0 0 0 0 0 0B Prescaler (UART1) 0 0 0 0 - 0 0 0B 0 0 0 0 0 0 0 0B Register 00002CH to 00003BH 00003CH ENIR Interrupt/DTP Enable Register R/W EIRR Interrupt/DTP source Register R/W Request Level Setting Register Lower R/W Request Level Setting Register Higher R/W 00003FH Initial Value Prohibited 00003DH 00003EH Resource name ELVR 000040H to 000045H DTP/External interrupt 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Prohibited 000046H PPGC0 PPG0 Operation Mode Control Register R/W PPG ch0 0X0 0 0XX1B 000047H PPGC1 PPG1 Operation Mode Control Register R/W PPG ch1 0X0 0 0 0 0 1B 000048H PPGC2 PPG2 Operation Mode Control Register R/W PPG ch2 0X0 0 0XX1B 000049H PPGC3 PPG3 Operation Mode Control Register R/W PPG ch3 0X0 0 0 0 0 1B R/W PPG ch0/1 0 0 0 0 0 0XXB R/W PPG ch2/3 0 0 0 0 0 0 XXB Serial Mode Control Status Register R/W 0 0 0 0 0 0 1 0B Serial Data Register R/W Extended Serial I/O Communication Prescaler Control Register R/W Communication Prescaler 0XXX0 0 0 0B PWC Control Status Register R/W 00004AH Prohibited 00004BH 00004CH PPG01 PPG0 and PPG1 Output Control Register 00004DH 00004EH Prohibited PPG23 PPG2 and PPG3 Output Control Register 00004FH to 000057H 000058H 000059H Prohibited SMCS 00005AH SDR 00005BH SDCR 00005CH 00005DH 00005EH 00005FH 000060H PWCSR PWCR DIVR PWC Data Buffer Register R/W PWC Dividing Ratio Register R/W 000061H 000062H 000063H 000064H 000065H XXXX0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 16-bit PWC Timer 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - 0 0B Prohibited 0 0 0 0 0 0 0 0B TMCSR0 Timer control status Register R/W TMR0 16-bit Timer Register Lower R TMRLR0 16-bit Reload Register Lower W TMR0 16-bit Timer Register Higher R XXXXXXXXB 16-bit Reload Register Higher W XXXXXXXXB TMRLR0 XXXX 0 0 0 0B 16-bit Reload Timer XXXXXXXXB XXXXXXXXB (Continued) 16 Preliminary 2004.01.09 Address MB90335 Series Register abbreviation Register 000066H to 00006EH Read/ Resource name Write Initial Value ROM Mirror Function Selection Module - - - - - - 1 1B Prohibited 00006FH ROMM ROM Mirroring Function Selection Register W 000070H IBSR0 I2C Bus Status Register R 000071H 000072H 000073H 000074H IBCR0 ICCR0 IADR0 IDAR0 2 I C Bus Control Register 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B 2 R/W I C Bus Interface XX 0 XXXXXB 2 R/W XXXXXXXXB 2 R/W XXXXXXXXB 0 0 0 0 0 0 0 0B I C Bus Clock Selection Register I C Bus Address Register I C Bus Data Register 000075H to 00009AH 2 Prohibited 00009BH DCSR DMA Descriptor Channel Specification Register R/W 00009CH DSRL DMA Status Register Lower R/W 00009DH DSRH DMA Status Register Higher R/W 00009EH PACSR Program Address Detection Control Status Register R/W Address Match Detection 0 0 0 0 0 0 0 0B 00009FH DIRR Delayed Interrupt Source generate/ release Register R/W Delayed Interrupt - - - - - - - 0B 0000A0H LPMCR Low Power Consumption Mode Register R/W Low Power Consumption control circuit 0 0 0 1 1 0 0 0B 0000A1H CKSCR Clock Selection Register R/W Clock 1 1 1 1 1 1 0 0B R/W µDMAC 0 0 0 0 0 0 0 0B 0000A2H 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Prohibited 0000A3H 0000A4H µDMAC DSSR DMA Stop Status Register 0000A5H to 0000A7H Prohibited 0000A8H WDTC Watchdog Control Register R/W Watchdog Timer X - XXX 1 1 1B 0000A9H TBTC Time-base Timer Control Register R/W Time-base Timer 1 - - 0 0 1 0 0B 0000AAH Prohibited 0000ABH 0000ACH DERL DMA Enable Register Lower R/W 0000ADH DERH DMA Enable Register Higher R/W 0000AEH FMCR Flash Memory Control Status Register R/W 0000AFH µDMAC FLASH MEMORY I/F 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 X 0 0 0 0B Prohibited (Continued) 17 Preliminary 2004.01.09 MB90335 Series Read/ Write Address Register abbreviation 0000B0H ICR00 Interrupt Control Register 00 R/W 0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt Control Register 01 R/W 0 0 0 0 0 1 1 1B 0000B2H ICR02 Interrupt Control Register 02 R/W 0 0 0 0 0 1 1 1B 0000B3H ICR03 Interrupt Control Register 03 R/W 0 0 0 0 0 1 1 1B 0000B4H ICR04 Interrupt Control Register 04 R/W 0 0 0 0 0 1 1 1B 0000B5H ICR05 Interrupt Control Register 05 R/W 0 0 0 0 0 1 1 1B 0000B6H ICR06 Interrupt Control Register 06 R/W 0 0 0 0 0 1 1 1B 0000B7H ICR07 Interrupt Control Register 07 R/W 0000B8H ICR08 Interrupt Control Register 08 R/W 0000B9H ICR09 Interrupt Control Register 09 R/W 0 0 0 0 0 1 1 1B 0000BAH ICR10 Interrupt Control Register 10 R/W 0 0 0 0 0 1 1 1B 0000BBH ICR11 Interrupt Control Register 11 R/W 0 0 0 0 0 1 1 1B 0000BCH ICR12 Interrupt Control Register 12 R/W 0 0 0 0 0 1 1 1B 0000BDH ICR13 Interrupt Control Register 13 R/W 0 0 0 0 0 1 1 1B 0000BEH ICR14 Interrupt Control Register 14 R/W 0 0 0 0 0 1 1 1B 0000BFH ICR15 Interrupt Control Register 15 R/W 0 0 0 0 0 1 1 1B 0000C0H HCNT0 USB Host Control Register 0 R/W 0 0 0 0 0 0 0 0B 0000C1H HCNT1 USB Host Control Register 1 R/W 0 0 0 0 0 0 0 1B 0000C2H HIRQ USB Host Interruption Register R/W 0 0 0 0 0 0 0 0B 0000C3H HERR USB Host Error Status Register R/W 0 0 0 0 0 0 1 1B 0000C4H HSTATE USB Host State Status Register R/W XX 0 1 0 0 1 0B 0000C5H HFCOMP USB SOF Interrupt FRAME compare Register R/W 0 0 0 0 0 0 0 0B USB Retry Timer Setting Register 0 R/W 0000C6H 0000C7H HRTIMER 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH HADR HEOF HFRAME HTOKEN Register 0000D1H Interrupt Controller Initial Value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 0 0 0B USB Mini HOST USB Retry Timer Setting Register 1 R/W USB Retry Timer Setting Register 2 R/W XXXXXX 0 0B USB Host Address Register R/W X 0 0 0 0 0 0 0B USB EOF Setting Register 0 R/W 0 0 0 0 0 0 0 0B USB EOF Setting Register 1 R/W XX 0 0 0 0 0 0B USB FRAME Setting Register 0 R/W 0 0 0 0 0 0 0 0B USB FRAME Setting Register 1 R/W XXXXX 0 0 0B USB Host Token End Point Register R/W 0 0 0 0 0 0 0 0B 0000CFH 0000D0H Resource name 0 0 0 0 0 0 0 0B Prohibited UDCC UDC Control Register R/W USB function 1 0 1 0 0 0 0 0B Prohibited (Continued) 18 Preliminary 2004.01.09 Address 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH MB90335 Series Register abbreviation Register EP0C EP0 Control Register EP1C EP1 Control Register EP2C EP2 Control Register EP3C EP3 Control Register EP4C EP4 Control Register EP5C EP5 Control Register TMSP Time Stamp Register Read/ Write Resource name Initial Value R/W X 1 0 0 0 0 0 0B R/W XXXX 0 0 0 XB R/W 0 0 0 0 0 0 0 0B R/W 0 1 1 0 0 0 0 1B R/W 0 1 0 0 0 0 0 0B R/W 0 1 1 0 0 0 0 0B R/W 0 1 0 0 0 0 0 0B R/W 0 1 1 0 0 0 0 0B R/W 0 1 0 0 0 0 0 0B R/W 0 1 1 0 0 0 0 0B R/W 0 1 0 0 0 0 0 0B R/W 0 1 1 0 0 0 0 0B R 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B 0000E0H UDCS UDC Status Register R/W 0 0 0 0 0 0 0 0B 0000E1H UDCIE Interrupt Enable Register R/W 0 0 0 0 0 0 0 0B EP0IS EP0I Status Register R/W XXXXXXXXB R/W 1 0 XXX 1 XXB EP0OS EP0O Status Register 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H 0000F6H 0000F7H 0000F8H 0000F9H EP1S EP1 Status Register EP2S EP2 Status Register EP3S EP3 Status Register EP4S EP4 Status Register EP5S EP5 Status Register EP0DT EP0 Data Register EP1DT EP1 Data Register EP2DT EP2 Data Register EP3DT EP3 Data Register EP4DT EP4 Data Register R/W XXXXXXXXB R/W 1 0 0 XX 0 0 XB R R/W USB Function XXXXXXXXB 1 0 0 0 0 0 0 XB R XXXXXXXXB R/W 1 0 0 0 0 0 0 XB R XXXXXXXXB R/W 1 0 0 0 0 0 0 XB R XXXXXXXXB R/W 1 0 0 0 0 0 0 XB R XXXXXXXXB R/W 1 0 0 0 0 0 0 XB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB (Continued) 19 Preliminary 2004.01.09 MB90335 Series Address 0000FAH 0000FBH Register abbreviation EP5DT Read/ Write Register R/W EP5 Data Register R/W 0000FCH to 0000FFH Prohibited 000100H to 001100H RAM Area Resource name USB Function Initial Value XXXXXXXXB XXXXXXXXB Program Address Detection Register ch0 Lower R/W XXXXXXXXB Program Address Detection Register ch0 Middle R/W XXXXXXXXB 001FF2H Program Address Detection Register ch0 Higher R/W 001FF3H Program Address Detection Register ch1 Lower R/W Program Address Detection Register ch1 Middle R/W XXXXXXXXB Program Address Detection Register ch1 Higher R/W XXXXXXXXB 001FF0H 001FF1H 001FF4H PADR0 PADR1 001FF5H 007900H PRLL0 PPG Reload Register Lower ch0 R/W 007901H PRLH0 PPG Reload Register Higher ch0 R/W 007902H PRLL1 PPG Reload Register Lower ch1 R/W 007903H PRLH1 PPG Reload Register Higher ch1 R/W 007904H PRLL2 PPG Reload Register Lower ch2 R/W 007905H PRLH2 PPG Reload Register Higher ch2 R/W 007906H PRLL3 PPG Reload Register Lower ch3 R/W 007907H PRLH3 PPG Reload Register Higher ch3 R/W 007908H to 00790BH Address Match Detection PPG ch0 PPG ch1 PPG ch2 PPG ch3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Prohibited 00790CH FWR0 Flash Program Control Register 0 R/W Flash 0 0 0 0 0 0 0 0B 00790DH FWR1 Flash Program Control Register 1 R/W Flash 0 0 0 0 0 0 0 0B 00790EH SSR0 Sector Conversion Setting Register R/W Flash 0 0 XXXXX0B 00790FH to 00791FH Prohibited (Continued) 20 Preliminary 2004.01.09 MB90335 Series (Continued) Address Register abbreviation Register Read/ Write 007920H DBAPL DMA Buffer Address Pointer Lower 8-bit R/W XXXXXXXXB 007921H DBAPM DMA Buffer Address Pointer Middle 8-bit R/W XXXXXXXXB 007922H DBAPH DMA Buffer Address Pointer Higher 8-bit R/W XXXXXXXXB 007923H DMACS DMA Control Register R/W XXXXXXXXB 007924H DIOAL DMA I/O Register Address Pointer Lower 8-bit R/W 007925H DIOAH DMA I/O Register Address Pointer Higher 8-bit R/W XXXXXXXXB 007926H DDCTL DMA Data Counter Lower 8-bit R/W XXXXXXXXB 007927H DDCTH DMA Data Counter Higher 8-bit R/W XXXXXXXXB 007928H to 007FFFH Resource name µDMAC Initial Value XXXXXXXXB Prohibited • Explanation on read/write R/W Read and write enabled R Read only W Write only • Explanation of initial values 0 : Initial Value is “0”. 1 : Initial Value is “1”. X : Initial Value is undefined. : Initial Value is undefined (None). Note : No IO instruction can be used for registers located between 007900H to 007FFFH. 21 Preliminary 2004.01.09 MB90335 Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt source EI2OS µDMAC support Number* Reset × × #08 08H FFFFDCH INT 9 instruction × × #09 09H FFFFD8H Exceptional treatment × × #10 0AH FFFFD4H USB Function1 × 0, 1 #11 0BH FFFFD0H USB Function2 × 2 to 6 #12 0CH FFFFCCH USB Function3 × × #13 0DH FFFFC8H USB Function4 × × #14 0EH FFFFC4H USB Mini-HOST1 × × #15 0FH FFFFC0H USB Mini-HOST2 × × #16 10H FFFFBCH I2C ch0 × × #17 11H FFFFB8H × #18 12H FFFFB4H #19 13H FFFFB0H × #20 14H FFFFACH #21 15H FFFFA8H × #22 16H FFFFA4H 14 #23 17H FFFFA0H × #24 18H FFFF9CH DTP/External interrupt ch0/1 No DTP/External interrupt ch2/3 No DTP/External interrupt ch4/5 PWC/Reload timer ch0 DTP/External interrupt ch6/7 No #25 19H FFFF98H No #26 1AH FFFF94H No #27 1BH FFFF90H No #28 1CH FFFF8CH No #29 1DH FFFF88H × × #30 1EH FFFF84H #31 1FH FFFF80H × × #32 20H FFFF7CH No #33 21H FFFF78H No #34 22H FFFF74H No #35 23H FFFF70H No #36 24H FFFF6CH 13 #37 25H FFFF68H 9 #38 26H FFFF64H 12 #39 27H FFFF60H PPG ch0/1 No PPG ch2/3 UART (Send completed) ch0/ch1 Extended serial I/O × UART(Reception completed) ch0/ch1 22 Interrupt control Prioriregister ty Address ICR Address Interrupt vector Time-base timer × × #40 28H FFFF5CH Flash memory status × × #41 29H FFFF58H Delayed interrupt output module × × #42 2AH FFFF54H High ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Low Preliminary 2004.01.09 MB90335 Series : Available. EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal. There is a stop demand.) : Available (The interrupt request flag is cleared by the interrupt clear signal). : Available when any interrupt source sharing ICR is not used. × : Unavailable • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS. • The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR). Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the µDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to " 0 " in the appropriate resource, and take measures by software polling. ■ USB INTERRUPT FACTOR CONTENTS USB interrupt factor Details USB function 1 End Point0-IN, EndPoint 0-OUT USB function 2 End Point 1-5 USB function 3 VOFF, VON, SUSP, SOF, BRST, WKOP, COHF USB function 4 SPIT USB Mini-HOST1 DIRQ, CHHIRQ, URIRQ, RWKIRQ USB Mini-HOST2 SOFIRQ, CMPIRQ 23 Preliminary 2004.01.09 MB90335 Series ■ PERIPHERAL RESOURCES 1. I/O port • The I/O ports are used as general-purpose input/output ports (parallel I/O ports). MB90335 series model is provided with 6 ports (45 inputs) . The ports function as input/output pins for peripheral functions also. • An I/O port, using port data register (PDR) , outputs the output data to I/O pin and input a signal input to I/O port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis. • The following table lists the I/O ports and the peripheral functions with which they share pins. Port pin name Pin Name (Peripheral) Peripheral Function that Shares Pin Port 0 P00 to P07 Port 1 P10 to P17 P20 to P23 P24 to P27 PPG0 to PPG3 P40, P41 TIN0, TOT0 P42 to P47 SIN0, SOT0, SCK0, SIN1, SOT1, SCK1 P50 to P54 P60, P61 INT0, INT1 P62 to P64 INT2 to INT4, SIN, SOT, SCK P65 INT5, PWC Port 2 Port 4 Port 5 Port 6 P66, P67 24 8/16 bit PPG timer 0, 1 16-bit reload timer UART0, 1 External interrupt External interrupt, serial IO External interrupt, PWC INT6, INT7, SCL0, SDA0 External interrupt, I2C Preliminary 2004.01.09 MB90335 Series • Register list (port data register) PDR0 7 6 5 4 3 2 1 0 Initial Value Access Address : 000000H P07 P06 P05 P04 P03 P02 P01 P00 XXXXXXXXB R/W* PDR1 15 14 13 12 11 10 9 8 P17 P16 P15 P14 P13 P12 P11 P10 XXXXXXXXB R/W* XXXXXXXXB R/W* XXXXXXXXB R/W* - - - XXXXXB R/W* XXXXXXXXB R/W* Address : 000001H PDR2 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 7 6 5 4 3 2 1 0 Address : 000004H P47 P46 P45 P44 P43 P42 P41 P40 PDR5 15 14 13 12 11 10 9 8 Address : 000005H P54 P53 P52 P51 P50 PDR6 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Address : 000002H PDR4 Address : 000006H * : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows: • Input mode Read : The level at the relevant pin is read. Write : Data is written to the output latch. • Output mode Read : The data register latch value is read. Write : Data is output to the relevant pin. 25 Preliminary 2004.01.09 MB90335 Series • Register list (port direction register) DDR0 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR4 Address : 000014H DDR5 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D 00 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 15 14 13 12 11 10 9 8 Address : 000015H D54 D53 D52 D51 D50 DDR6 7 6 5 4 3 2 1 0 D67 D66 D65 D64 D63 D62 D61 D60 Address : 000016H • Initial Value Access 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W - - - 00000B R/W 00000000B R/W When each pin is serving as a port, the corresponding pin is controlled as follows: 0 : Input mode 1 : Output mode This bit becomes 0 after a reset. Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to the current input values of the pins. When switching a pin from input port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output. • Register list (Port pull-up register) RDR0 Address : 00001CH RDR1 Address : 00001DH 7 6 5 4 3 2 1 0 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 15 14 13 12 11 10 9 8 RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 Initial Value Access 00000000B R/W 00000000B R/W Controls the pull-up resistor in input mode. 0 : Without pull-up resistor in input mode. 1 : With Pull-up resistor in input mode. Meaningless in output mode (without pull-up resistor) ./ The input/output register is decided by the setting of the direction register (DDR) . No pull-up resistor is used in stop mode (SPL = 1). 26 Preliminary 2004.01.09 MB90335 Series • Register list (output pin register) ODR4 Address : 00001BH 7 6 5 4 3 2 1 0 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 Initial Value Access 00000000B R/W Controls open-drain output in output mode. 0 : Serves as a standard output port in output mode. 1 : Serves as an open-drain output port in output mode. Meaningless in input mode. (output High-Z) / The input/output register is decided by the setting of the direction register (DDR) . • Block diagram of port 0 pin and port1 pin Internal data bus Pull-up resistor setting register (RDRx) Built-in pull-up resistor PDRx read PDRx Write Port data register (PDRx) Input buffer I/O decision circuit Port direction register (DDRx) Output buffer Port pin Standby control (LPMCR : SPL = “1”) • Block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin Internal data bus Resource input PDRx read PDRx write Port data register (PDRx) I/O decision circuit Port direction register (DDRx) input buffer Output buffer Port pin Standby control (LPMCR : SPL = “1”) Resource output control signal Release output 27 Preliminary 2004.01.09 MB90335 Series 2. Time-base timer • The time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock HCLK). • Four different time intervals can be selected, for each of which an interrupt request can be generated. • Operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and watchdog timer. • Interval time of time-base timer Internal count clock cycle Interval time 212/HCLK (Approx. 0.68 ms) 214/HCLK (Approx. 2.7 ms) 2/HCLK (0.33 µs) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Notes : • HCLK : Oscillation clock frequency • The parenthesized values assume an oscillator clock frequency of 6 MHz. • Clock cycles supplied from time-base timer Where to supply clock Clock cycle 13 2 /HCLK (Approx. 1.36 ms) Oscillation stabilization wait of main clock 215/HCLK (Approx. 5.46 ms) 217/HCLK (Approx. 21.84 ms) 212/HCLK (Approx. 0.68 ms) 214/HCLK (Approx. 2.7 ms) Watch dog timer 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Notes : • HCLK : Oscillation clock frequency • The parenthesized values assume an oscillator clock frequency of 6 MHz. • Register list Time-base timer control register (TBTC) Address : 0000A9H 15 14 13 12 11 10 9 8 RESV TBIE TBOF TBR TBC1 TBC0 ( R/W ) () () ( R/W ) ( R/W ) (W) ( R/W ) ( R/W ) Initial Value 1--00100B Note : For the conditions for clearing the time-base timer, refer to the chapter for the time-base timer in the hardware manual. 28 Preliminary 2004.01.09 MB90335 Series • Block Diagram To watchdog timer To PPG timer Time-base timer counter Dividing HCLK by 2 × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF Power-on reset Stop mode start To clock controller oscillation stabilizing wait time selector Counter clear control circuit CKSCR : MCS = 1→0*1 Interval timer selector TBOF set TBOF clear Time-base timer control register (TBTC) RESV TBIE TBOF TBR TBC1 TBC0 Time-base timer interrupt signal OF HCLK *1 :Unused :Overflow :Oscillation clock :Switching the machine clock from main clock to PLL clock Actual interrupt request number of time-base timer is as follows: Interrupt request number:#40 (28H) 29 Preliminary 2004.01.09 MB90335 Series 3. Watchdog timer • The watchdog timer is a timer counter prepared in case programs run out of control. • The watchdog timer is a 2-bit counter using the time-base timer as the count clock. • When started, the watchdog timer resets the CPU if it is not cleared before the two-bit counter overflows. • Interval time of watchdog timer HCLK: Oscillation clock (6 MHz) Min Max Clock cycle Approx. 2.39 ms Approx. 3.07 ms 2 ± 211 / HCLK Approx. 9.56 ms Approx. 12.29 ms 216 ± 213 / HCLK Approx. 38.23 ms Approx. 49.15 ms 218 ± 215 / HCLK Approx. 305.83 ms Approx. 393.22 ms 221 ± 218 / HCLK 14 Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing. • The watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer. When the device is operating with HCLK, therefore, clearing the time-base timer lengthens the watchdog reset generation time interval. • Event that stop the watchdog timer 1 : Stop due to a Power-on reset 2 : watchdog reset • Clear factor of watch dog timer 1 : External reset input by RST pin 2 : Writing “0” to the software reset bit 3 : Writing “0” to the watchdog control bit (second and subsequent times) 4 : Transition to sleep mode (Clearing the watchdog timer, and suspend counting) 5 : Transition to time-base timer mode (Clearing the watchdog timer, and suspend counting) 6 : Transition to stop mode (Clearing the watchdog timer, and suspend counting) • Register list Watchdog timer control register (WDTC) Address : 0000A8H 30 7 6 5 4 3 2 1 0 PONR WRST ERST SRST WTE WT1 WT0 (R) () (R) (R) (R) (W) (W) (W) Initial Value X-XXX111B Preliminary 2004.01.09 MB90335 Series • Block Diagram Watchdog timer control register (WDTC) PONR WRST ERST SRST WTE WT1 WT0 2 Timer-base timer mode start Sleep mode start Watchdog timer Stop mode start Counter clear control circuit CLR and start Count clock selector 2-bit counter CLR Clear CLR watchdog timer reset generation circuit To internal reset generation circuit 4 Time-base timer counter Dividing HCLK by 2 × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 HCLK: Oscillation clock 31 Preliminary 2004.01.09 MB90335 Series 4. 16 - bit Reload Timer The 16-bit reload timer has the internal clock mode to be decrement in synchronization with three different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. Either can be selected. This timer defines when the count value changes from 0000H to FFFFH as an underflow. The timer therefore causes an underflow when the count reaches [reload register setting +1]. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC. • Register list • Timer control status register Timer control status register (Higher) (TMCSR0) Address : 000063H 15 14 13 12 11 10 9 8 CSL1 CSL0 MOD2 MOD1 () () () () ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXX0000B Timer control status register (Lower) (TMCSR0) Address : 000062H 7 6 5 4 3 2 1 0 MOD0 OUTE OUTL RELD INTE UF CNTE TRG ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000000B • 16-bit timer register/16-bit reload register TMR0/TMRLR0 (Higher) Address : 000065H 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D09 D08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB TMR0/TMRLR0 (Lower) Address : 000064H 32 Initial Value XXXXXXXXB Preliminary 2004.01.09 MB90335 Series • Block Diagram Internal data bus TMRLR0 16-bit reload register Reload control circuit Reload signal TMR0 ∗2 16-bit timer register UF CLK Count clock generation circuit Machine clock φ 3 Prescaler Clear Trriger Gate input Valid clock decision circuit Internal clock Input control circuit Pin TIN0 CLK Clock selector Wait signal Output control circuit Output signal generation circuit Pin EN TOT0 External clock 3 2 Select signal Operating Control circuit Select function CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE Timer control status register (TMCSR0) *1 : Interrupt number *2 : Underflow UF CNTE TRG Interrupt request output #23 (17H)*1 33 Preliminary 2004.01.09 MB90335 Series 5. Multifunction timer • The multifunction timer can be used for waveform output, input pulse width measurement, and external clock cycle measurement. • Configuration of a multi-functional timer 8/16 bit PPG timer 8 bit × 4 ch (16 bit × 2 ch) 16 bit PWC timer 1 ch • 8/16 bit PPG timer (8 bit : 4 channels, 16 bit : 2 channels) 8/16 bit PPG timer consists of a 8 bit down counter (PCNT) , PPG control register (PPGC0 to PPGC3) , PPG clock control register (PCS01, PCS23) and PPG reload register (PRLL0 to PRLL3, PRLH0 to PRLH3) . When used as an 8/16 bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an arbitrary duty ratio at an arbitrary frequency. • 8 bit PPG mode Each channel operates as an independent 8 bit PPG. • 8 bit prescaler + 8 bit PPG mode Operates as an arbitrary-cycle 8 bit PPG with ch0 (ch2) operating as an 8 bit prescaler and ch2 (ch3) counted by the borrow output of ch0 (ch2). • 16 bit PPG mode Operates as a 16 bit PPG with ch0 (ch2) and ch1 (ch3) connected. • PPG Operation The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of pulse waveform) at an arbitrary frequency. Can also be used as a D/A converter by an external circuit. 34 Preliminary 2004.01.09 MB90335 Series • Register list PPG operation mode control register (PPGC1/PPGC3) 000047H Address : 000049H 15 14 13 12 11 10 9 8 PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved ( R/W ) () ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 PEN0 PE0O PIE0 PUF0 Reserved ( R/W ) () ( R/W ) ( R/W ) ( R/W ) () () ( R/W ) 2 1 0 Initial Value 0X000001B (PPGC0/PPGC2) 000046H Address : 000048H Initial Value 0X000XX1B PPG output control register (PPG01/PPG23) 00004CH Address : 00004EH PPG reload register (PRLH0 to PRLH3) 007901H 007903H Address : 007905H 007907H (PRLL0 to PRLL3) 007900H 007902H Address : 007904H 007906H 7 6 5 4 3 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D09 D08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB ( R/W ) 7 ( R/W ) Initial Value 000000XXB Initial Value XXXXXXXXB ( R/W ) 35 Preliminary 2004.01.09 MB90335 Series • 8 bit PPG ch0/2 block diagram Peripheral clock × 16 PPG 0/2 output enable Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock PPG0/2 A/D converter PPG 0/2 output latch PEN0 S PCNT (down counter) To interrupt IRQ #30 (1EH)* #32 (20H)* R Q Count clock selector ch1/3/5 borrow L/H selector Timebase counter output main clock × 512 PUF0 PIE0 L/H selector PRLL PRLHB PPGC0 (operation mode control) PRLL L data bus H data bus * : Interrupt number 36 Preliminary 2004.01.09 MB90335 Series • 8 bit PPG ch1/3 block diagram Peripheral clock × 16 PPG 1/3 output enable Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock PPG1/3 PPG 1/3 output latch PEN1 PCNT0 (down counter) S R To interrupt IRQ #30 (1EH)* #32 (20H)* Q Count clock selector L/H selector Timebase counter output main clock × 512 PUF1 PIE1 L/H selector PRLL PRLHB PPGC0 (operation mode control) PRLL L data bus H data bus * : Interrupt number 37 Preliminary 2004.01.09 MB90335 Series • PWC timer The PWC timer is a 16 bit multifunction up-count timer capable of measuring the input signal pulse width. • Register list PWC control status register (PWCSR) Address : 00005DH Address : 00005CH 15 14 13 12 11 10 9 8 STRT STOP EDIR EDIE OVIR OVIE ERR Reserved ( R/W ) ( R/W ) (R) ( R/W ) ( R/W ) ( R/W ) (R) ( R/W ) 7 6 5 4 3 2 1 0 CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 0000000XB Initial Value 00000000B PWC data buffer register (PWCR) Address : 00005FH Address : 00005EH Initial Value 00000000B Initial Value 00000000B Ratio of dividing frequency control register (DIVR) Address : 000060H 38 7 6 5 4 3 2 1 0 DIV1 DIV0 () () () () () () ( R/W ) ( R/W ) Initial Value ------00B Preliminary 2004.01.09 MB90335 Series • Block Diagram PWCR read Error detection ERR PWCR 16 Internal clock (Machine clock/4) Reload Data transfer Overflow 16 Clock 16 bit up-count timer 22 F2MC-16 bus 23 Timer clear 15 Control bit output Flag set etc... Control circuit Start edge selection Measurement starting edge Measurement termination edge CKS1/CKS0 Count enable Divider clear end edge selection Divider ON/OFF Edge detection Measurement termination interrupt request Overflow interrupt request Clock devider PWCSR PWC 8-bit divider PIS0/PIS1 ERR Input waveform comparator CKS0/CKS1 Divide ratio select 2 DIVR 39 Preliminary 2004.01.09 MB90335 Series 6. UART Overview of UART • UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop synchronization) communications with external devices. • It supports bi-directional communication (normal mode) and master/slave communication (multi-processor mode: supported on master side only). • An interrupt can be generated upon completion of reception, detection of a reception errror, or upon completion of transmission. EI2OS is supported also. • UART functions UART, or a generic serial data communication interface that sends and receives serial data to and from other CPU and peripherals, has the functions listed in following. Function Data buffer Transmission mode Baud rate Data length Signaling system Reception error detection Interrupt request Master/slave type communication function (multi processor mode) Full-duplex double-buffered • Clock synchronous (without start/stop bit) • Clock asynchronous (start-stop synchronous) • Special-purpose baud-rate generator It is optional from eight kinds. • Baud rate by external clock (clock of SCK0/SCK1 terminal input) • 8 bits or 7 bits (in the asynchronous normal mode only) • 1 to 8 bits (in the synchronous mode only) Non Return to Zero (NRZ) system • Framing error • Overrun error • Parity error (Not supported in operation mode 1) • Receive interrupt (reception completed, reception error detected) • Transmission interrupt (transmission completed) • Both the transmission and reception support EI2OS. Capable of 1 (master) to n (slaves) communication (available just as master) Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added. UART operation modes Operation mode 0 Normal mode 1 Multi processor mode 2 Normal mode : Setting disabled Data length Without parity With parity 7 bits or 8 bits Synchronization Asynchronous 8 + 1 *1 Asynchronous 8 Synchronous *1 : + 1 is an address/data setting bit (A/D) which is used for communication control. *2 : Only one bit can be detected as a stop bit at reception. 40 Stop bit length 1 bit or 2 bits *2 No Preliminary 2004.01.09 MB90335 Series • Register list Serial mode register (SMR0, SMR1) Address : 000020H 000026H 7 6 5 4 3 2 1 0 MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00100000B Serial control register (SCR0, SCR1) Address : 000021H 000027H 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) (W) ( R/W ) ( R/W ) Initial Value 00000100B Serial input/output register (SIDR0, SIDR1 / SODR0, SODR1) Address : 000022H 000028H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 PE ORE FRE RDRF TDRE BDS RIE TIE (R) (R) (R) (R) (R) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB Serial data register (SSR0, SSR1) Address : 000023H 000029H Initial Value 00001000B UART prescaler reload register (UTRLR0, UTRLR1) Address : 000024H 00002AH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000000B UART prescaler control register (UTCR0, UTCR1) Address : 000025H 00002BH 15 14 13 12 11 10 9 8 MD SRST CKS Reserved D10 D9 D8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) () ( R/W ) ( R/W ) ( R/W ) Initial Value 0000-000B 41 Preliminary 2004.01.09 MB90335 Series ・Block Diagram Control bus Special-purpose baud-rate generator (UART prescaler control register UTCR0, 1) Reception interrupt signal #39 (27H)∗ Transmission clock Clock Reception Reception selector control clock Send interrupt signal #37 (25H)∗ Transmission control circuit circuit Pin SCK0, SCK1 Start bit detection circuit Transmission start circuit Reception bit counter Transmission bit counter Reception parity counter Transmission parity counter Pin SOT0, SOT1 Shift register for reception Pin SIN0, SIN1 SIDR0, SIDR1 Shift register for transmission Reception complete SODR0, SODR1 Receive status decision circuit Start transmission Reception error occurrence signal for EI2OS (to CPU) Internal data bus SMR0, SMR1 * : Interrupt number 42 MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE SCR0, SCR1 PEN P SBL CL A/D REC RXE TXE SSR0, SSR1 PE ORE FRE RDRF TDRE BDS RIE TIE Preliminary 2004.01.09 MB90335 Series 7. Extended I/O serial interface The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit × 1 channel configured clock synchronization scheme. LSB-first or MSB-first transfer mode can be selected for data transfer. There are two serial I/O operation modes available: • Internal shift clock mode: Transfer data in synchronization with the internal clock. • External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK). By manipulating the general-purpose port sharing the external pin (SCK) in this mode, data can also be transferred by a CPU instruction. • Register list Serial mode control status register (SMCS) Address : Address : 000059H 000058H 15 14 13 12 11 10 9 8 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 MODE BDS SOE SCOE () () () () ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000010 B Initial Value XXXX0000 B Serial data register (SDR) Address : 00005AH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB Communication prescaler control register (SDCR) Address : 00005BH 15 14 13 12 11 10 9 8 MD DIV3 DIV2 DIV1 DIV0 ( R/W ) () () () ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 0XXX0000B 43 Preliminary 2004.01.09 MB90335 Series • Block Diagram Internal data bus D7 to D0 (LSB first) (MSB first) D0 to D7 Initial Value Transfer direction selection SIN SDR (serial data register) Read Write SOT SCK Control circuit Shift clock counter Internal clock 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS Interrupt request Internal data bus 44 SOE SCOE Preliminary 2004.01.09 MB90335 Series 8. I2C Interface The I2C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I2C bus and has the following features. • Master/slave sending and receiving • Arbitration function • Clock synchronization function • Slave address and general call address detection function • Detecting transmitting direction function • Start condition repeated generation and detection function • Bus error detection function • Register list I2C bus status register (IBSR0) Address : 000070H 7 6 5 4 3 2 1 0 BB RSC AL LRB TRX AAS GCA FBT (R) (R) (R) (R) (R) (R) (R) (R) 15 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000000B I2C bus control register (IBCR0) Address : 000071H Initial Value 00000000B I2C bus clock selection register (ICCR0) Address : 000072H 7 6 5 4 3 2 1 0 EN CS4 CS3 CS2 CS1 CS0 ( ) ( ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXX0XXXXB I2C bus address register (IADR0) Address : 000073H 15 14 13 12 11 10 9 8 A6 A5 A4 A3 A2 A1 A0 ( ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB I2C bus data register (IDAR0) Address : 000074H Initial Value XXXXXXXXB 45 Preliminary 2004.01.09 MB90335 Series • Block Diagram ICCR EN I2C enable Peripheral clock Clock devide 1 5 F2MC-16 bus ICCR 6 7 8 CS4 CS3 Clock selector 1 CS2 CS1 CS0 2 4 8 16 IBSR BB Clock devide 2 32 64 128 256 Sync Generating shift clock Clock selector 2 Shift clock edge change timing Bus busy Repeat start RSC LRB TRX Last Bit Start stop condition detection Error Send/receive First Byte FBT AL Arbitration lost detection IBCR SCL0 BER BEIE Interrupt request INTE INT End IBCR SCC MSS ACK GCAA Start Master ACK enable Start stop condition generation GC-ACK enable IDAR IBSR AAS GCA Slave Global call Slave address compare IADR 46 IRQ SDA0 Preliminary 2004.01.09 MB90335 Series 9. USB Function The USB is an interface supporting the USB (Universal Serial Bus) communications protocol. Feature of USB function • Conform to USB 2.0 Full Speed • FULL speed (12 Mbps) is supported. • The device status is auto-answer. • Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16. • Toggle check by data synchronization bit. • Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these three commands can be processed the same way as the class vendor commands). • The class vendor commands can be received as data and responded via firmware. • Supports up to maximum six EndPoints (EndPoint0 is fixed to control transfer). • Two transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for end point 0). • Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0). • Capable of detection of connection and disconnection by monitoring the USB bus power line. • Register list UDC control register (UDCC) 7 Address : 0000D0H RST 6 5 4 3 2 Reserved Reserved 1 0 RFBK PWC RESUM HCONX USTP ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 Reserved PKS0 PKS0 PKS0 PKS0 PKS0 PKS0 PKS0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 () () () () ( R/W ) 7 6 5 4 PKS1 PKS1 PKS1 ( R/W ) ( R/W ) 15 ( R/W ) Initial Value 10100000B EP0 control register (EP0C) Address : 0000D2H 9 8 STAL Reserved ( R/W ) ( R/W ) ( R/W ) 3 2 1 0 PKS1 PKS1 PKS1 PKS1 PKS1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 14 13 12 11 10 9 8 EPEN TYPE TYPE DIR DMAE NULE STAL PKS1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Address : 0000D3H Reserved Reserved Initial Value X1000000B Initial Value XXXX0000B EP1 control register (EP1C) Address : 0000D4H Address : 0000D5H Initial Value 00000000B Initial Value 01100001B (Continued) 47 Preliminary 2004.01.09 MB90335 Series EP2/3/4/5 control register (EP2C ∼ EP5C) Address : 0000D6H 0000D8H 0000DAH 0000DCH 0000D7H Address : 0000D9H 0000DBH 0000DDH 7 6 5 4 3 2 1 0 Reserved PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 EPEN TYPE TYPE DIR DMAE NULE STAL Reserved ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 TMSP TMSP TMSP TMSP TMSP TMSP TMSP TMSP (R) (R) (R) (R) (R) (R) (R) (R) 15 14 13 12 11 10 9 8 TMSP TMSP TMSP () () () () () (R) (R) (R) 7 6 5 4 3 2 1 0 VOFF VON SUSP SOF BRST WKUP SETP CONF ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 14 13 12 11 10 9 8 Initial Value 01000000B Initial Value 01100000B Time stamp register (TMSP) Address : 0000DEH Address : 0000DFH Initial Value 00000000B Initial Value 00000000B UDC status register (UDCS) Address : 0000E0H Initial Value 00000000B Interrupt enable register (UDCIE) 15 Address : 0000E1H VOFFIE VONIE SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) (R) ( R/W ) Initial Value 00000000B EP0I status register (EP0IS) Address : 0000E2H Address : 0000E3H 7 6 5 4 3 2 1 0 () () () () () () () () 15 14 13 12 11 10 9 8 BFINI DRQIIE DRQI ( R/W ) ( R/W ) () () () ( R/W ) () () Initial Value XXXXXXXXB Initial Value 10XXX1XXB (Continued) 48 Preliminary 2004.01.09 MB90335 Series (Continued) EP0O status register (EP0OS) Address : 0000E4H Address : 0000E5H 7 6 5 4 3 2 1 0 SIZE SIZE SIZE SIZE SIZE SIZE SIZE () (R) (R) (R) (R) (R) (R) (R) 15 14 13 12 11 10 9 8 DRQO SPK BFINI DRQOIE SPKIE ( R/W ) ( R/W ) ( R/W ) () () ( R/W ) ( R/W ) () 7 6 5 4 3 2 1 0 SIZE SIZE SIZE SIZE SIZE SIZE SIZE SIZE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 BFINI DRQIE SPKIE BUSY DRQ SPK SIZE ( R/W ) ( R/W ) ( R/W ) () (R) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB Initial Value 100XX00XB EP1 status register (EP1S) Address : 0000E6H Address : 0000E7H Initial Value XXXXXXXXB Initial Value 1000000XB EP2/3/4/5 status register (EP2S to EP5S) 0000E8H Address : 0000EAH 0000ECH 0000EEH 7 6 5 4 3 2 1 0 SIZE SIZE SIZE SIZE SIZE SIZE SIZE () ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 BUSY DRQ SPK () (R) ( R/W ) ( R/W ) () 0000E9H BFINI DRQIE SPKIE Address : 0000EBH ( R/W ) ( R/W ) ( R/W ) 0000EDH 0000EFH EP0/1/2/3/4/5 data register (EP0DT to EP5DT) 0000F0H 0000F2H 0000F4H Address : 0000F6H 0000F8H 0000FAH 0000F1H 0000F3H 0000F5H Address : 0000F7H 0000F9H 0000FBH Initial Value XXXXXXXXB Initial Value 1000000XB Initial Value 7 6 5 4 3 2 1 0 BFDT BFDT BFDT BFDT BFDT BFDT BFDT BFDT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 BFDT BFDT BFDT BFDT BFDT BFDT BFDT BFDT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) XXXXXXXXB Initial Value XXXXXXXXB 49 Preliminary 2004.01.09 MB90335 Series 10. USB Mini-HOST USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred to and from Device without PC intervention. Feature of USB Mini-HOST • Automatic detection of Low Speed/Full Speed transfer • Low Speed/Full Speed transfer support • Automatic detection of connection and cutting device • Reset sending function support to USB-bus • Support of IN/OUT/SETUP/SOF token • In-token handshake packet automatic transmission (excluding STALL) • Handshake packet automatic detection at out-token • Supports a maximum packet length of 256 bytes • Error (CRC error/toggle error/time-out) various supports • Wake-Up function support Differences between the USB HOST and USB Mini-HOST HOST Mini-HOST × Hub support Bulk transfer Transfer Control transfer Interrupt transfer ISO transfer Transfer speed Low Speed Full Speed × PRE packet support SOF packet support CRC error Toggle error Error Time-out Maximum packet < receive data Detection of connection and cutting of device Transfer speed detection × 50 : Supported : Not supported × Preliminary 2004.01.09 MB90335 Series • Register list USB HOST control register 0 (HCONT0) 7 Address : 0000C0H 6 5 4 RWKIRE URIRE CMPIRE CNNIRE ( R/W ) ( R/W ) 3 DIRE 2 1 0 SOFIRE URST HOST ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 13 12 11 10 9 8 Initial Value 00000000B USB HOST control register 1 (HCONT1) 15 Address : 0000C1H 14 Reserved Reserved Reserved Reserved Reserved SOFSTEP CANCEL RETRY ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 5 4 3 2 ( R/W ) Initial Value 00000001B ( R/W ) USB HOST interruption register (HIRQ) 7 Address : 0000C2H 6 TCAN Reserved RWKIRQ URIRQ CMPIRQ CNNIRQ ( R/W ) ( R/W ) 1 0 DIRQ SOFIRQ ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 13 12 11 10 9 8 TOUT CRC HS HS ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 5 4 3 2 1 0 Initial Value 00000000B USB HOST error status register (HERR) 15 Address : 0000C3H 14 LSTSOF RERR ( R/W ) ( R/W ) TGERR STUFF Initial Value 00000011B USB HOST state status register (HSTATE) Address : 0000C4H 7 6 () () ALIVE CLKSEL SOFBUSY SUSP ( R/W ) ( R/W ) ( R/W ) ( R/W ) TMODE CSTAT (R) Initial Value XX010010B (R) USB SOF interruption FRAME comparison register (HFCOMP) Address : 0000C5H 15 14 13 12 11 10 9 8 FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME COMP COMP COMP COMP COMP COMP COMP COMP ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 4 3 2 1 0 Initial Value 00000000B USB retry timer setting register 0/1/2 (HRTIMER) 7 Address : 0000C6H Address : 0000C7H Address : 0000C8H 6 5 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 () () () () () () Initial Value 00000000B Initial Value 00000000B ( R/W ) ( R/W ) ( R/W ) 1 0 RTIMER2 RTIMER2 ( R/W ) Initial Value XXXXXX00B ( R/W ) (Continued) 51 Preliminary 2004.01.09 MB90335 Series (Continued) USB HOST address register (HADR) 15 Address : 0000C9H () 14 13 12 11 10 9 8 ADDRESS ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value X0000000B USB EOF setting register 0/1 (HEOF) Address : 0000CAH Address : 0000CBH 7 6 5 4 3 2 1 0 EOF0 EOF0 EOF0 EOF0 EOF0 EOF0 EOF0 EOF0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 EOF1 EOF1 EOF1 EOF1 EOF1 EOF1 () () ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 5 4 3 2 1 0 Initial Value 00000000B Initial Value XX000000B USB FRAME setting register (HFRAME) 7 Address : 0000CCH Address : 0000CDH 6 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 () () () () () ( R/W ) ( R/W ) ( R/W ) 5 4 3 2 1 0 FRAME1 FRAME1 FRAME1 Initial Value 00000000B Initial Value XXXXX000B USB token end point register (HTOKEN) 7 Address : 0000CEH 52 6 TGGL TKNEN TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000000B Preliminary 2004.01.09 MB90335 Series 11. DTP/external interrupt circuit Feature of DTP/external interrupt circuit DTP (Data Transfer Peripheral)/external interrupt circuit detects the interrupt request input from the external interrupt input terminal INT7 to INT0, and outputs the interrupt request. • DTP/external interrupt circuit function The DTP/external interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (INT7 to INT0). If CPU accept the interrupt request, and if the extended intelligent I/O service (EI2OS) is enabled, branches to the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI2OS. And if EI2OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer (DTP function) performed by EI2OS. • Feature of DTP/external interrupt circuit External interrupt Input pin Interrupt source DTP function 8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK, P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0) The detection level or the type of the edge for each terminals can be set in the request level setting register (ELVR) Input of “H” level/ “L” level/rising edge/falling edge. Interrupt number #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) Interrupt control Enabling/Prohibit the interrupt request output using the DTP/interrupt enable register (ENIR) Interrupt flag Holding the interrupt source using the DTP/interrupt cause register (EIRR) Process setting Prohibit EI2OS (ICR: ISE=“0”) Enable EI2OS (ICR: ISE=“1”) Process Branched to the interrupt handling routine After an automatic data transfer by EI2OS, Branched to the interrupt handling routine • Register list Interrupt/DTP enable register (ENIR) Address : 00003CH 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 13 12 11 10 9 8 Initial Value 00000000B Interrupt/DTP source register (EIRR) 15 Address : 00003DH 14 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value 00000000B Request level setting register (ELVR) Address : 00003EH Address : 00003FH 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value 00000000B Initial Value 00000000B 53 Preliminary 2004.01.09 MB90335 Series • Block Diagram Request level setting register (ELVR) LB7 LA7 2 Pin LB6 LA6 2 LB5 LA5 2 LB4 LA4 2 LB3 LA3 2 LB2 LA2 LB1 2 LA1 2 DTP/external interrupt input detection circuit Selector LA0 2 Selector Pin P60/INT0 P67/INT7 SDA0 Pin Pin Selector Selector P66/INT6 SCL0 Internal data bus LB0 P61/INT1 Selector Pin Pin Selector P62/INT2 SIN P65/INT5 PWC Pin Selector Selector Pin P63/INT3 SOT P64/INT4 SCK DTP/interrupt source register (EIRR) ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request signal #18(12H)∗ #20(14H)∗ #22(16H)∗ DTP/interrupt enable register (ENIR) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 * : Interrupt number 54 #24(18H)∗ Preliminary 2004.01.09 MB90335 Series 12. Interrupt controller The interrupt control register is located inside the interrupt controller, it exists for every I/O having an interrupt function. This register has the following functions. • Setting of the interrupt levels of relevant peripheral • Register list Interrupt control register Address： ICR01 : 0000B1H ICR03 : 0000B3H ICR05 : 0000B5H ICR07 : 0000B7H ICR09 : 0000B9H ICR11 : 0000BBH ICR13 : 0000BDH ICR15 : 0000BFH Read/Write → Initial Value → ICR00 : 0000B0H Address： ICR02 : 0000B2H ICR04 : 0000B4H ICR06 : 0000B6H ICR08 : 0000B8H ICR10 : 0000BAH ICR12 : 0000BCH ICR14 : 0000BEH Read/Write → Initial Value → 15 14 13 12 11 10 9 8 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 (W) (0) (W) (0) (W) (0) (W) (0) ( R/W ) (0) ( R/W ) (1) ( R/W ) (1) ( R/W ) (1) 7 6 5 4 3 2 1 0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 (W) (0) (W) (0) (W) (0) (W) (0) ( R/W ) (0) ( R/W ) (1) ( R/W ) (1) ( R/W ) (1) ICR01, 03, 05, 07, 09, 11, 13, 15 ICR00, 02, 04, 06, 08, 10, 12, 14 Note : Do not access interrupt control registers using any read modify write instruction because it causes a malfunction. • Block Diagram 3 3 F2MC-16LX bus I L2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 I L1 32 Interrupt request (peripheral resource) 3 (CPU) Interrupt level IL 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Determine priority of interrupt 55 Preliminary 2004.01.09 MB90335 Series 13. µDMAC µDMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the following features. • Performs automatic data transfer between the peripheral resource (I/O) and memory • The program execution of CPU stops in the DMA startup • Capable of selecting whether to increment the transfer source and destination addresses • DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register and descriptor • A STOP request is available for stopping DMA transfer from the resource • Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA status register is set and a termination interrupt is output to the transfer controller. • Register list DMA enable register higher (DERH) Address : 0000ADH 15 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 STP7 STP15 6 STP6 STP14 5 STP5 STP13 4 STP4 STP12 3 STP3 STP11 2 STP2 STP10 1 STP1 STP9 0 STP0 STP8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000000B DMA enable register lower (DERL) Address : 0000ACH Initial Value 00000000B DMA stop status register (DSSR) Address : 0000A4H Initial Value 00000000B * DMA status register higher (DSRH) Address : 00009DH 15 14 13 12 11 10 9 8 DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 7 6 5 4 3 2 1 0 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 3 2 1 0 Initial Value 00000000B DMA status register lower (DSRL) Address : 00009CH Initial Value 00000000B DMA descriptor channel specification register (DCSR) 7 Address : 00009BH STP ( R/W ) 6 5 4 Reserved Reserved Reserved DCSR3 DCSR2 DCSR1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) DCSR0 Initial Value 00000000B ( R/W ) * : The DSSR is lower when the STP bit of DCSR in the DSSR is 0. The DSSR is upper when the STP bit of DCSR in the DSSR is 1. (Continued) 56 Preliminary 2004.01.09 MB90335 Series (Continued) DMA buffer address pointer lower 8 bit (DBAPL) 7 Address : 007920H 6 5 4 3 2 1 0 DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 12 11 10 9 8 Initial Value XXXXXXXXB DMA buffer address pointer middle 8 bit (DBAPM) 15 Address : 007921H 14 13 DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 4 3 2 1 0 Initial Value XXXXXXXXB DMA Buffer address pointer higher 8 bit (DBAPH) DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH Initial Value XXXXXXXXB ( R/W ) 7 Address : 007922H 6 5 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 RDY2 RDY1 BYTEL IF BW BF DIR SE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) DMA control register (DMACS) Address : 007923H Initial Value XXXXXXXXB ( R/W ) ( R/W ) DMA I/O register address pointer lower 8 bit (DIOAL) Address : 007924H 7 6 5 4 3 2 1 0 A07 A06 A05 A04 A03 A02 A01 A00 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB DMA I/O register address pointer higher 8 bit (DIOAH) Address : 007925H 15 14 13 12 11 10 9 8 A15 A14 A13 A12 A11 A10 A09 A08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB DMA data counter lower 8 bit (DDCTL) Address : 007926H 7 6 5 4 3 2 1 0 B07 B06 B05 B04 B03 B02 B01 B00 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB DMA data counter higher 8 bit (DDCTH) Address : 007927H 15 14 13 12 11 10 9 8 B15 B14 B13 B12 B11 B10 B09 B08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value XXXXXXXXB Note : The above register is switched for each channel depending on the DCSR. 57 Preliminary 2004.01.09 MB90335 Series 14. Address matching detection function When the address is equal to the value set in the address detection register, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9 instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the program patch function is enabled. Two address detection registers are provided, for each of which there is an interrupt enable bit. When the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code. • Register list • Program address detect register 0 to 2 (PADR0) PADR0 (lower) 7 6 5 Address : 001FF0H PADR0 (middle) Address : 001FF1H PADR0 (higher) Address : 001FF2H PADR1 (higher) Address : 001FF5H 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 12 11 10 9 8 • Program address detect register 3 to 5 (PADR1) PADR1 (lower) 15 14 13 Address : 001FF3H PADR1 (middle) Address : 001FF4H 4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 2 1 0 Reserved AD0E Reserved (R/W) (R/W) (R/W) • Program address detect control status register (PACSR) PACSR 7 6 5 4 3 Address : 00009EH Reserved Reserved Reserved Reserved AD1E (R/W) R/W : Readable and Writable X : Undefined 58 (R/W) (R/W) (R/W) (R/W) Initial Value XXXXXXXXB Initial Value XXXXXXXXB Initial Value XXXXXXXXB Initial Value XXXXXXXXB Initial Value XXXXXXXXB Initial Value XXXXXXXXB Initial Value 00000000B Preliminary 2004.01.09 MB90335 Series 15. Delay interrupt generator module • The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware interrupt can be generated by software. • Function of delay interrupt generator module Function and control Interrupt source • Setting the R0 bit in the delayed interrupt request generate/cancel register to 1 (DIRR: R0 = 1) generates a interrupt request. • Setting the R0 bit in the delayed interrupt request generate/cancel register to 0 (DIRR: R0 = 0) cancels the interrupt request. Interrupt control • No setting of permission register is provided. • Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0) Interrupt flag • Not ready for expanded intelligent I/O service (EI2OS). EI2OS support • Block Diagram Internal data bus R0 Delayed Interrupt source/release register (DIRR) : Undefined bit S Interrupt request R Latch Interrupt request signal 59 Preliminary 2004.01.09 MB90335 Series 16. ROM mirroring function selection module • The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read by accessing bank 00. • ROM mirroring function selection module Description Mirror setting address Interrupt source 2 EI OS support FFFFFFH to FF8000H in the FF bank can be read through 00FFFFH to 008000H in the 00 bank. • None • Not ready for extended intelligent I/O service (EI2OS). • Block Diagram ROM mirror function selection register (ROMM) Address Internal data bus Address area 00 bank FF bank Data ROM 60 Reserved MI Preliminary 2004.01.09 MB90335 Series 17. Low power consumption (standby) mode • The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode. • CPU operation mode and functional description CPU Operation operating clock mode Normally run The CPU and peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) frequency. Only peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) frequency. Sleep PLL clock Time-base Only the time-base timer operates at the clock frequency obtained by PLL timer multiplication of the oscillator clock (HCLK) frequency. The CPU and peripheral resources are suspended with the oscillator clock stopped. Stop normally run The CPU and peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Sleep Main clock CPU intermittent operation mode Description Time-base Only the time-base timer operates at the clock frequency obtained by dividing the timer oscillator clock (HCLK) frequency by two. Stop The CPU and peripheral resources are suspended with the oscillator clock stopped. Normally run The halved or PLL-multiplied oscillator clock (HCLK) frequency is used for operation while being decimated in a certain period. • Register list Lowe power consumption mode control register (LPMCR) Address : 0000A0H 7 6 5 4 3 2 1 0 STP SLP SPL RST TMD CG1 CG0 Reserved (W) (W) ( R/W ) (W) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00011000B 61 Preliminary 2004.01.09 MB90335 Series 18. Clock The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation as PLL clock. • Register list Clock selection register (CKSCR) Address : 0000A1H 62 15 14 13 12 11 10 9 8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 (R) (R) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 11111100B Preliminary 2004.01.09 MB90335 Series 19. 512 Kbits flash memory The description that follows applies to the flash memory built in the MB90F334; it is not applicable to evaluation ROM or masked ROM. The method of data write/erase to flash memory is following three types. • Parallel writer • Serial dedicated writer • Write/erase by executing program • Description of 512 Kbits flash memory 512 Kbits flash memory is located in FFH bank in the CPU memory map. Function of flash memory interface circuit enables read and program access from CPU. Write/erase to flash interface is executed by instruction from CPU via flash memory interface, so rewrite of program and data is carried on in the mounting state effectively. Data can be reprogrammed not only by program execution in existing RAM but by program execution in flash memory by dual operation. The different banks (the upper and lower banks) can be used to execute an erase/ program and a read concurrently. Also, erase/write and read in the defferent bank (Upper Bank/Lower Bank) is executed simultaneously. • Features of 512 Kbits flash memory • Sector configuration : 64 Kwords × 8 bits/32 words × 16 bits (4K × 4 + 16K × 2 + 4K × 4) • Simultaneous execution of erase/write and read by 2-bank configuration • Automatic program algorithm (Embeded AlgorithmTM*) • Built-in deletion pause/deletion resume function • Detection of programming/erasure completion using data polling and the toggle bit • At least 10,000 times guaranteed • Minimum flash read cycle time : 2 machine cycles * : Embedded AlgorithmTM is a trade mark of Advanced Micro Devices Inc. Note : The read function of manufacture code and device coad is not including. Also, these code is not accessed by the command. • Flash write/erase • Flash memory can not execute write/erase and read by the same bank simultaneously. • Data can be programmed/deleted into and erased from flash memory by executing either the program residing in the flash memory or the one copied to RAM from the flash memory. 63 Preliminary 2004.01.09 MB90335 Series • Sector configuration of flash memoly SA1 (4 Kbyte) SA2 (4 Kbyte) SA3 (4 Kbyte) SA4 (16 Kbyte) SA5 (16 Kbyte) SA6 (4 Kbyte) SA7 (4 Kbyte) SA8 (4 Kbyte) SA9 (4Kbyte) FF0000H 70000H FF0FFFH 70FFFH FF1000H 71000H FF1FFFH 71FFFH FF2000H 72000H FF2FFFH 72FFFH FF3000H 73000H FF3FFFH 73FFFH FF4000H 74000H FF7FFFH 77FFFH FF8000H 78000H FFBFFFH 78FFFH FFC000H 7C000H FFCFFFH 7CFFFH FFD000H 7D000H FFDFFFH 7DFFFH FFE000H 7E000H FFEFFFH 7EFFFH FFF000H 7F000H FFFFFFH 7FFFFH Upper Bank SA0 (4 Kbyte) Lower Bank Flash Memory CPU address Writer address * * : Flash memory writer address indicates the address equivalent to the CPU address when data is written to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses. 64 Preliminary 2004.01.09 MB90335 Series • Register list Flash memory control register (FMCS) Address : 0000AEH 7 6 5 4 3 2 1 INTE RDYINT WE RDY Reserved ( R/W ) ( R/W ) ( R/W ) (R) (W) ( R/W ) (W) ( R/W ) LPM1 Reserved 0 LPM0 Initial Value 000X0000B Flash memory program control register (FWR0) Address : 00790CH 7 6 5 4 3 2 1 0 SA7E SA6E SA5E SA4E SA3E SA2E SA1E SA0E ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000000B Flash memory program control register (FWR1) Address : 00790DH 15 14 13 12 11 10 9 0 SA9E SA8E ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) Initial Value 00000000B Sector conversion setting register (SSR0) Address : 00790EH 7 6 5 4 3 2 1 0 SEN0 ( R/W ) ( R/W ) () () () () () ( R/W ) Initial Value 00XXXXX0B ∗ When writing to SSR0 register, write “0” except for SEN0. 65 Preliminary 2004.01.09 MB90335 Series • Standard configuration for Fujitsu standard serial on-board writing The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corp. is used for Fujitsu standard serial onboard writing. Host interface cable (AZ201) RS232C General-purpose common cable (AZ210) Flash microcontroller programmer + Memory card CLK synchronous serial MB90F337 user system Can operate standalone Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the flash microcontroller programmer (AF220, AF210, AF120 and AF110) , general-purpose common cable for connection (AZ210) and connectors. • Pins Used for Fujitsu Standard Serial On-board Programming Pin 66 Function Description MD2, Mode input pin MD1, MD0 The device enters the serial program mode by setting MD2 = 1, MD1 = 1 and MD0 = 0. X0, X1 Oscillation pin Because the internal CPU operation clock is set to be the 1 multiplication PLL clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. P60, P61 Write program start pins Input a Low level to P60 and a High level to P61. RST Reset input pin SIN0 Serial data input pin SOT0 Serial data output pin SCK0 Serial clock input pin UART0 is used as CLK synchronous mode. In write mode, the pins used for the UART0 CLK synchronous mode are SIN0, SOT0, and SCK0. VCC Power source input pin When supplying the write voltage (MB90F337 : 3.3 V±0.3 V) from the user system, connection with the flash microcontroller programmer is not necessary. When connecting, do not short-circuit with the user power supply. VSS GND Pin Share GND with the flash microcontroller programmer. Preliminary 2004.01.09 MB90335 Series The control circuit shown in the diagram is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash microcontroller programmer. AF220/AF210/AF120/AF110 Write control pin MB90F337 write control pin 10 kΩ AF220/AF210/AF120/AF110 /TICS pin User Control circuit The MB90F337 serial clock frequency that can be input is determined by the following expression • Use the flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock frequency to be used. Imputable serial clock frequency = 0.125 × oscillation clock frequency. • Maximum serial clock frequency Oscillation clock frequency Maximum serial clock frequency acceptable to the microcontroller Maximum serial clock frequency that can be set with the AF220/AF210/ AF120/AF110 Maximum serial clock frequency that can be set with the AF200 At 6 MHz 750 kHz 500 kHz 500 kHz • System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa Digital Computer Corp.) Part number Unit Function AF220/AC4P Model with internal Ethernet interface /100 V to 220 V power adapter AF210/AC4P Standard model /100 V to 220 V power adapter AF120/AC4P Single key internal Ethernet interface mode /100 V to 220 V power adapter AF110/AC4P Single key model /100 V to 220 V power adapter AZ221 PC/AT RS232C cable for writer AZ210 Standard target probe (a) length : 1 m FF201 Control module for Fujitsu F2MC-16LX flash microcontroller control module AZ290 Remote controller /P2 2 MB PC Card (option) FLASH memory capacity to respond to 128 KB /P4 4 MB PC Card (option) FLASH memory capacity to respond to 512 KB Contact to : Yokogawa Digital Computer Corp. TEL : (81)-42-333-6224 Note : The AF200 flash micon programmer is a retired product, but it can be supported using control module FF201. 67 Preliminary 2004.01.09 MB90335 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage Input voltage Symbol VCC VI (VCC = 3.3 V, VSS = 0.0 V) Rating Unit Remarks Min Max VSS − 0.3 VSS + 4.0 V VSS − 0.3 VSS + 4.0 V *1 VSS − 0.3 VSS + 6.0 V Nch0.D (Withstand voltage I/O of 5 V) − 0.5 VSS + 4.5 V USB I/O VSS − 0.3 VSS + 4.0 V *1 − 0.5 VSS + 4.5 V USB I/O Output voltage VO L level maximum output current IOL1 10 mA Other than USB I/O*2 IOL2 43 mA USB I/O*2 L level average output current IOLAV 3 mA *3 L level maximum total output current ΣIOL 60 mA ΣIOLAV 30 mA *4 IOH1 − 10 mA Other than USB I/O*2 IOH2 − 43 mA USB I/O*2 H level average output current IOHAV −3 mA *3 H level maximum total output current ΣIOH − 60 mA H level average total output current ΣIOHAV − 30 mA *4 Power consumption Pd 351 mW Target value Operating temperature TA − 40 + 85 °C − 55 + 150 °C − 55 + 125 °C L level average total output current H level maximum output current Storage temperature Tstg USB I/O *1 : VI and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *2 : A peak value of an applicable one pin is specified as a maximum output current. *3 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *4 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 68 Preliminary 2004.01.09 MB90335 Series 2. Recommended Operating Conditions Parameter Symbol (VSS = 0.0 V) Value Unit Remarks Min Max 3.0 3.6 V At normal operation (At USB is used) 2.7 3.6 V At normal operation (At USB is unused) 1.8 3.6 V Hold state of stop operation VIH 0.7 VCC VCC + 0.3 V CMOS input pin VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VIHM VCC − 0.3 VCC + 0.3 V MD input pin VIHUSB 2.0 VCC + 0.3 V USB input pin VIL VSS − 0.3 0.3 VCC V CMOS input pin VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin VILM VSS − 0.3 VSS + 0.3 V MD input pin VILUSB VSS 0.8 V USB input pin Differential input sensitivity VDI 0.2 V USB input pin Differential common mode input voltage range VCM 0.8 2.5 V USB input pin Series resistance RS 25 30 Ω Recommended value = 27 Ω at using USB Operating temperature TA − 40 + 85 °C At USB is unused 0 + 70 °C At USB is used Power supply voltage Input H level voltage Input L level voltage VCC WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 69 Preliminary 2004.01.09 MB90335 Series 3. DC Characteristics Parameter Output H level voltage Output L level voltage Input leak current Symbol VOH VOL (TA = − 40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Pin name Conditions Typ Max VCC − 0.5 Vcc V HVP, HVM, DVP, DVM RL = 15 kΩ ± 5% 2.8 3.6 V Output pin of other than HVP, HVM, DVP, IOL = 4.0 mA DVM Vss Vss + 0.4 V 0 0.3 V Output pin of other VCC = 3.3 V, than P60 to P67, HVP, Vss < VI < VCC HVM, DVP, DVM − 10 10 µA −5 5 µA 25 50 100 kΩ 0.1 10 µA At USB operating mA Max 90 mA (Target) At nonoperating mA USB (USTP = 0) Output pin of other than P60 to P67, HVP, IOH = −4.0 mA HVM, DVP, DVM HVP, HVM, DVP, DVM P00 to P07, P10 to P17 Pull-up resistor RPULL Open drain output current ILIOD P60 to P67 VCC = 3.3 V, Ta = + 25 °C VCC = 3.3 V, Internal frequency 24 MHz, At normal operating VCC = 3.3 V, Internal frequency 24 MHz, At normal operating ICC Power supply current VCC ICCS ICTS ICCH TBD 70 VCC = 3.3 V, Internal frequency 24 MHz, At normal operating TBD At nonoperating mA USB (USTP = 1) VCC = 3.3 V, Internal frequency 24 MHz, At sleep mode 27 mA VCC = 3.3 V, Internal frequency 24 MHz, At timer mode 3.5 mA VCC = 3.3 V, Internal frequency 3 MHz, At timer mode 1 mA Ta = +25 °C, At Stop mode 1 µA Input capacitance CIN Other than Vcc and Vss 5 15 pF Pull-up resistor Rup RST 25 50 100 kΩ Note : P60 to P67 are N-ch open-drain pins usually used as CMOS. 70 Unit Remarks Min HVP, HVM, DVP, DVM RL = 1.5 kΩ ± 5% IIL Value Preliminary 2004.01.09 MB90335 Series 4. AC Characteristics (1) Clock input timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Symbol Pin name Clock frequency fCH X0, X1 Clock cycle time tHCYL X0, X1 Input clock pulse width PWH PWL Input clock rise time and fall time Parameter Value Unit Remarks Min Typ Max 6 MHz External crystal oscillation 6 24 MHz External clock input 166.7 ns External crystal oscillation 166.7 41.7 ns External clock input X0 10 ns A reference duty ratio is 30% to 70%. tcr tcf X0 5 ns At external clock Internal operating clock frequency fCP 3 24 Internal operating clock cycle time tCP 42 333 MHz At main clock is used ns At main clock is used • Clock timing tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr 71 Preliminary 2004.01.09 MB90335 Series • PLL operation guarantee range Relation between internal operation clock frequency and power supply voltage Power supply voltage VCC (V) PLL operation guarantee range 3.6 3.0 2.7 Normal operation assurance range 3 6 12 24 Internal clock fCP (MHz) * : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V. Relation between oscillation frequency and internal operation clock frequency Multiply by 4 Internal clock fCP (MHz) 24 Multiply by 2 12 External clock Multiply by 1 6 3 24 6 Oscillation clock FC (MHz) The AC standards provide that the following measurement reference voltages. • Output signal waveform • Input signal waveform Hysteresis input pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Hysteresis input/other than MD input pin 0.7 VCC 0.3 VCC 72 Output pin Preliminary 2004.01.09 MB90335 Series (2) Reset Parameter Reset input time (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name tRSTL RST Value Conditions Min Max Unit Remarks 500 ns At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode Oscillation time of oscillator* + 500 ns µs At stop mode * : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a FAR/ceramic oscillator, and 0 milliseconds on an external clock. • During normal operation, in time-base timer mode, in main sleep mode and in PLL sleep mode tRSTL RST 0.2 VCC 0.2 VCC • In stop mode tRSTL RST 0.2 VCC 0.2 VCC 90% of amplitude X0 Internal operation clock Oscillation time of oscillator 500 ns Oscillation stabilization wait time Execute instruction Internal reset 73 Preliminary 2004.01.09 MB90335 Series (3) Power-on reset Parameter Power supply rising time Power supply shutdown time (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Symbol Pin name tR VCC tOFF VCC Conditions Value Unit Min Max 30 ms 1 ms Remarks For repeated operation Notes : • VCC must be lower than 0.2 V before the power supply is turned on. • The above standard is a value for performing a power - on reset. • In the device, there are internal registers which is initialized only by a power-on reset. When the initial ization of these items is expected, turn on the power supply according to the standards. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation. VCC The rising edge should be 50 mV/ms or less. 3.0 V VSS 74 RAM data hold Preliminary 2004.01.09 MB90335 Series (4) UART0, UART1 I/O extended serial timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Symbol Pin name Serial clock cycle time tSCYC SCKx SCK ↓ → SOT delay time tSLOV SCKx SOTx Valid SIN → SCK ↑ tIVSH SCKx SINx SCK ↑ → valid SIN hold time tSHIX Serial clock H pulse width Parameter Value Conditions Unit Remarks Min Max 8 tCP ns − 80 80 ns 100 ns SCKx SINx 60 ns tSHSL SCKx, SINx 4 tCP ns Serial clock L pulse width tSLSH SCKx, SINx 4 tCP ns SCK ↓ → SOT delay time tSLOV SCKx SOTx 150 ns Valid SIN → SCK ↑ tIVSH SCKx SINx 60 ns SCK ↑ → valid SIN hold time tSHIX SCKx SINx 60 ns Internal shiftc lock Mode output pin is CL = 80 pF + 1 TTL External shift clock Mode output pin is CL = 80 pF + 1 TTL Notes : • AC rating in CLK synchronous mode. • CL is a load capacitance value on pins for testing. • tCP is the machine cycle period (unit : ns) . • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 75 Preliminary 2004.01.09 MB90335 Series (5) I2C timing (VCC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Parameter Pin Condiname tions Value Min Max Unit SCL clock frequency fSCL 0 100 kHz Bus-free time between stop and start conditions tBUS 4.7 µs tHDSTA 4.0 µs SCL clock “L” status hold time tLOW 4.7 µs SCL clock “H” status hold time tHIGH 4.0 µs Resend start condition setup time tSUSTA 4.7 µs Data hold time tHDDAT 0 µs Data set-up time tSUDAT 40 ns SDA and SCL signal rise time tR 1000 ns SDA and SCL signal fall time tF 300 ns tSUSTO 4.0 µs Hold time (resend) start Stop condition setup time Remarks The first clock pulse is generated immediately after the period. 0.8 VCC SDA 0.2 VCC tBUS tLOW tR tHIGH tF tHDSTA 0.8 VCC SCL 0.2 VCC tHDSTA tHDDAT fSCL 76 tSUDAT tSUSTA tSUSTO Preliminary 2004.01.09 MB90335 Series (6) Timer Input Timing Parameter (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Value Symbol Pin name Conditions Min Max tTIWH tTIWL PWC 4 tCP Input pulse width 0.8 VCC Unit Remarks ns 0.8 VCC 0.2 VCC 0.2 VCC PWC tTIWH tTIWL (7) Timer output timing (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Value Parameter Symbol Pin name Conditions Min Max CLK ↑ → TOUT change time PPG0 to PPG3 change time tTO PPGx 30 Unit Remarks ns 2.4 V CLK tTO 2.4 V 0.8 V PPGx (8) Trigger Input Timing Parameter Input pulse width (TA = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Symbol Pin name Conditions tTRGH tTRGL INTx 0.8 VCC Value Unit Remarks Min Max 5 tCP ns At normal operating 1 µs At Stop mode 0.8 VCC 0.2 VCC 0.2 VCC INTx tTRGH tTRGL 77 Preliminary 2004.01.09 MB90335 Series 5. USB characteristics Value Sym bol Min Max Input High level voltage VIH 2.0 V Input Low level voltage VIL 0.8 V Differential input sensitivity VDI 0.2 V Differential common mode range VCM 0.8 2.5 V Output High level voltage VOH 2.8 3.6 V IOH = −200 µA Output Low level voltage VOL 0.0 0.3 V IOL = 2 mA Cross over voltage VCRS 1.3 2.0 V tFR 4 20 ns Full Speed tLR 75 300 ns Low Speed tFF 4 20 ns Full Speed tLF 75 300 ns Low Speed tRFM 90 111.11 % (TFR/TFF) tRLM 80 125 % (TLR/TLF) ZDRV 28 44 Ω Including Rs = 27 Ω Parameter Input characteristics (TA = 0 °C to +70 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V) Symbol Rise time Output characteristics Fall time Rising/falling time matching Output registance • Data signal timing (Full Speed) Rise time DVP/HVP 90% Vcrs Fall time 90% 10% 10% DVM/HVM tFF tFR • Data signal timing (Low Speed) Rise time HVP HVM 90% Vcrs 90% 10% 10% tLR 78 Fall time tLF Unit Remarks Preliminary 2004.01.09 MB90335 Series • Load condition (Full Speed) RS = 27 Ω DVP/HVP Testing point CL = 50 pF DVM/HVM RS = 27 Ω Testing point CL = 50 pF • Load condition (Low Speed) HVP RS = 27 Ω Testing point CL = 50 pF ∼ 150 pF HVM RS = 27 Ω Testing point CL = 50 pF ∼ 150 pF 79 Preliminary 2004.01.09 MB90335 Series ■ ORDERING INFORMATION • MB90335 Series Part number MB90F337PFM MB90337PFM 80 Package 64-pin plastic LQFP (FPT-64P-M09) Remarks Preliminary 2004.01.09 MB90335 Series ■ PACKAGE DIMENSION Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 64-pin plastic LQFP (FPT-64P-M09) 14.00±0.20(.551±.008)SQ * 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.0057±.0022) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8˚ 64 17 1 16 0.65(.026) C "A" 0.32±0.05 (.013±.002) 0.13(.005) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) M 2003 FUJITSU LIMITED F64018S-c-3-5 Dimensions in mm (inches) Note : The values in parentheses are reference values. 81 MB90335 Series MEMO 82 Preliminary 2004.01.09 Preliminary 2004.01.09 MB90335 Series MEMO 83 Preliminary 2004.01.09 MB90335 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ F0312 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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