TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 FEATURES APPLICATIONS • • • • • • • • • • Simple Voltage Conversion, Including – Negative Converter – Voltage Doubler Wide Operating Range…1.5 V to 10 V Requires Only Two External (Noncritical) Capacitors No External Diode Over Full Temperature and Voltage Range Typical Open-Circuit Voltage Conversion Efficiency…99.9% Typical Power Efficiency…98% Full Testing at 3 V On-Board Negative Supplies Data-Acquisition Systems Portable Electronics D, DGK, OR P PACKAGE (TOP VIEW) NC CAP+ GND CAP− 1 8 2 7 3 6 4 5 VCC OSC LV VOUT NC − No internal connection DESCRIPTION/ORDERING INFORMATION The TL7660 is a CMOS switched-capacitor voltage converter that perform supply-voltage conversions from positive to negative. With only two noncritical external capacitors needed for the charge pump and charge reservoir functions, an input voltage within the range from 1.5 V to 10 V is converted to a complementary negative output voltage of –1.5 V to –10 V. The device can also be connected as a voltage doubler to generate output voltages up to 18.6 V with a 10-V input. The basic building blocks of the IC include a linear regulator, an RC oscillator, a voltage-level translator, and four power MOS switches. To ensure latch-up-free operation, the circuitry automatically senses the most negative voltage in the device and ensures that the N-channel switch source-substrate junctions are not forward biased. The oscillator frequency runs at a nominal 10 kHz (for VCC = 5 V), but that frequency can be decreased by adding an external capacitor to the oscillator (OSC) terminal or increased by overdriving OSC with an external clock. For low-voltage operation (VIN < 3.5 V), LV should be tied to GND to bypass the internal series regulator. Above 3.5 V, LV should be left floating to prevent device latchup. The TL7660C is characterized for operation over a free-air temperature range of –40°C to 85°C. The TL7660I is characterized for operation over a free-air temperature range of –40°C to 125°C. ORDERING INFORMATION PACKAGE (1) TA MSOP/VSSOP – DGK –40°C to 85°C PDIP – P SOIC – D MSOP/VSSOP – DGK –40°C to 125°C PDIP – P SOIC – D (1) (2) ORDERABLE PART NUMBER Reel of 250 TL7660CDGKT Reel of 2500 TL7660CDGKR Tube of 50 TL7660CP Tube of 75 TL7660CD Reel of 2500 TL7660CDR Reel of 250 TL7660IDGKT Reel of 2500 TL7660IDGKR Tube of 50 TL7660IP Tube of 75 TL7660ID Reel of 2500 TL7660IDR TOP-SIDE MARKING (2) TM_ TL7660CP 7660C TN_ TL7660IP 7660I Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DGK: The actual top-side marking has one additional character that indicates the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 FUNCTIONAL BLOCK DIAGRAM VCC CAP+ RC Oscillator OSC Voltage-Level Translator ¸2 CAP− LV VOUT Voltage Regulator Logic Network Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage TL7660 VI OSC and LV input voltage range (2) ILV Current into LV (2) VCC > 3.5 V tOS Output short-circuit duration VSUPPLY ± 5.5 V θJA Package thermal impedance (3) (4) Junction temperature Storage temperature range (1) (2) (3) (4) V –0.3 VCC + 0.3 VCC > 5.5 V VCC – 5.5 VCC + 0.3 20 V µA Continuous 97 DGK package 172 P package Tstg UNIT 10.5 VCC < 5.5 V D package TJ MAX °C/W 85 –55 150 °C 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Connecting any input terminal to voltages greater than VCC or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to power up of the TL7660. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions VCC TA 2 Supply voltage Operating free-air temperature MIN MAX TL7660 1.5 10 TL7660C –40 85 TL7660I –40 125 Submit Documentation Feedback UNIT V °C TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 Electrical Characteristics VCC = 5 V, COSC = 0, LV = Open, TA = 25°C (unless otherwise noted) (see Figure 1) PARAMETER TEST CONDITIONS TA (1) MIN 25°C TYP MAX 45 110 UNIT ICC Supply current RL = ∞ VCC,LOW Supply voltage range (low) RL = 10 kΩ, LV = GND Full range 1.5 3.5 V VCC,HIGH Supply voltage range (high) RL = 10 kΩ, LV Open Full range 3 10 V –40°C to 85°C 120 –40°C to 125°C 135 25°C IO = 20 mA ROUT Output source resistance VCC = 2 V, IO = 3 mA, LV = GND 45 Oscillator frequency ηPOWER Power efficiency RL = 5 kΩ ηVOUT Voltage conversion efficiency RL = ∞ ZOSC Oscillator impedance 85 –40°C to 125°C 135 25°C 125 –40°C to 85°C 200 (1) 10 25°C 96 –40°C to 125°C 95 25°C 99 –40°C to 125°C 99 25°C VCC = 5 V Ω 250 25°C VCC = 2 V 70 –40°C to 85°C –40°C to 125°C fOSC µA kHz 98 % 99.9 % 1 MΩ 100 kΩ Full range is –40°C to 85°C for the TL7660C and –40°C to 125°C for the TL7660I. Electrical Characteristics VCC = 3 V, COSC = 0, LV = GND, (unless otherwise noted) (see Figure 1) PARAMETER TEST CONDITIONS TA MIN 25°C Supply current (1) ICC RL = ∞ Output source resistance IO = 10 mA fOSC Oscillator frequency COSC = 0 ηPOWER Power efficiency RL = 5 kΩ ηVOUT Voltage conversion efficiency RL = ∞ (1) MAX 24 50 –40°C to 85°C 60 –40°C to 125°C 75 25°C ROUT TYP 60 110 –40°C to 125°C 120 5 –40°C to 125°C 3 25°C 96 –40°C to 125°C 95 25°C 99 –40°C to 125°C 99 9 98 µA 100 –40°C to 85°C 25°C UNIT Ω kHz % % Derate linearly above 50°C by 5.5 mW/°C. Submit Documentation Feedback 3 TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs OSCILLATOR CAPACITANCE OSCILLATOR FREQUENCY vs TEMPERATURE 10 21 VCC = 5 V TA = 25°C f OSC – Oscillator Frequency – kHz f OSC – Oscillator Frequency – kHz 9 8 7 6 5 4 3 2 1 10 100 17 15 VCC = 10 V 13 11 VCC = 5 V 9 7 5 -40 -25 -10 5 0 1 19 1000 20 35 50 65 80 95 110 125 COSC – Oscillator Capacitance – pF TA – Free-Air Temperature – °C 150 140 130 120 110 100 VCC = 2 V 90 IO = 3 mA 80 70 60 50 40 30 20 10 0 -40 -25 -10 5 SUPPLY VOLTAGE vs TEMPERATURE 10 9 8 VCC – Supply Voltage – V ROUT – Output Source Resistance – Ω OUTPUT RESISTANCE vs TEMPERATURE VCC = 5 V IO = 20 mA 7 5 4 3 VCC = 10 V 2 IO = 20 mA 1 20 35 50 65 80 95 11 12 0 5 0 -40 -25 -10 TA – Free-Air Temperature – °C 4 Supply Voltage Range (No Diode Required) 6 Submit Documentation Feedback 5 20 35 50 65 80 TA – Free-Air Temperature – °C 95 110 125 TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 TYPICAL CHARACTERISTICS (continued) OUTPUT RESISTANCE vs SUPPLY VOLTAGE OUTPUT RESISTANCE vs OSCILLATOR FREQUENCY 600 VCC = 5 V 550 150 TA = 25°C 500 125 Output Resistance – W Ω ROUT – Output Source Resistance – Ω 175 TA = 125°C 100 TA = 25°C 75 TA = –40°C 50 25 IO = 10 mA 450 400 350 COSC = 1 µF 300 COSC = 10 µF 250 COSC = 100 µF 200 150 100 50 0 0 1 2 3 4 5 6 7 8 9 0 100 100 10 10k 10000 1k 1000 VCC – Supply Voltage – V 100k 100000 f OSC – Oscillator Frequency – Hz OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 0 0 VCC = 5 V VCC = 2 V -0.25 -0.5 TA = 25°C TA = 25°C VO – Output Voltage – V VO – Output Voltage – V -1 -0.5 -0.75 -1 -1.25 -1.5 -1.5 -2 -2.5 -3 -3.5 -4 -1.75 -4.5 -2 -5 0 1 2 3 4 5 6 7 8 9 0 IL – Load Current – mA 5 10 15 20 25 30 35 40 IL – Load Current – mA Submit Documentation Feedback 5 TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 TYPICAL CHARACTERISTICS (continued) EFFICIENCY AND SUPPLY CURRENT vs LOAD CURRENT EFFICIENCY AND SUPPLY CURRENT vs LOAD CURRENT 18 90 80 16 70 14 60 12 50 10 40 8 ICC 30 6 20 4 VCC = 2 V 10 2 TA = 25°C 0 0 0 1 2 3 4 5 6 7 8 100 80 80 70 70 60 60 50 50 40 30 30 20 20 VCC = 5 V 10 0 9 0 0 5 10 15 100 ηPOWER – Power-Conversion Efficiency – % ePOWER 20 25 30 IL – Load Current – mA 98 96 94 92 VCC = 5 V TA = 25°C IOUT = 1 mA 88 1k 1000 10 TA = 25°C EFFICIENCY vs OSCILLATOR FREQUENCY 10k 10000 f OSC – Oscillator Frequency – Hz 6 40 ICC IL – Load Current – mA 90 90 ηPOWER Submit Documentation Feedback 100k 100000 35 40 45 ICC – Supply Current – mA ηPOWER 100 ePOWER Efficiency – % ηPOWER – Power-Conversion 90 20 ICC – Supply Current – mA ePOWER Efficiency – % ηPOWER – Power-Conversion 100 TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 APPLICATION INFORMATION IS 8 1 7 2 TL7660 C1 + 10 µF - 3 6 4 5 V+ (5 V) IL RL COSC (see Note A) –VOUT C2 10 µF + A. In the circuit, there is no external capacitor applied to terminal 7. However when device is plugged into a test socket,there is usually a very small but finite stray capacitance present on the order of 10 pF. Figure 1. Test Circuit The TL7660 contains all the necessary circuitry to complete a negative voltage converter, with the exception of two external capacitors which may be inexpensive 10 µF polarized electrolytic types. The mode of operation of the device may be best understood by considering Figure 2, which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage, VCC, for the half cycle when switches S1 and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation, switches S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 negatively by VCC volts. Charge is then transferred from C1 to C2 such that the voltage on C2 is exactly VCC, assuming ideal switches and no load on C2. The TL7660 approaches this ideal situation more closely than existing non-mechanical circuits. In the TL7660, the four switches of Figure 2 are MOS power switches: S1 is a p-channel device, and S2, S3, and S4 are n-channel devices. The main difficulty with this design is that in integrating the switches, the substrates of S3 and S4 must always remain reverse biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit start up and under output short circuit conditions (VOUT = VCC), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this results in high power losses and probable device latchup. This problem is eliminated in the TL7660 by a logic network which senses the output voltage (VOUT) together with the level translators and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. The voltage regulator portion of the TL7660 is an integral part of the anti-latchup circuitry; however, its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low-voltage operation, the LV terminal should be connected to GND, disabling the regulator. For supply voltages greater than 3.5 V, the LV terminal must be left open to insure latchup proof operation and prevent device damage. 8 S2 2 S1 VIN C1 3 S3 3 S4 C2 5 VOUT = –VIN 7 Figure 2. Idealized Negative-Voltage Converter Submit Documentation Feedback 7 TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 APPLICATION INFORMATION (continued) Theoretical Power Efficiency Considerations In • • • theory, a voltage converter can approach 100% efficiency if certain conditions are met. The driver circuitry consumes minimal power. The output switches have extremely low ON resistance and virtually no offset. The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The TL7660 approaches these conditions for negative voltage conversion if large values of C1 and C2 are used. Energy is only lost in the transfer of charge between capacitors if a change in voltage occurs. The energy lost is defined by: E = ½ C1(V12 – V22) Where V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (see Figure 2) compared to the value of RL, there is a substantial difference in the voltages V1 and V2. Therefore, it is not only desirable to make C2 as large as possible to eliminate output voltage ripple but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. Do's and Don'ts • Do not exceed maximum supply voltages. • Do not connect LV terminal to GND for supply voltages greater than 3.5 V. • Do not short circuit the output to VCC supply for supply voltages above 5.5 V for extended periods, however, transient conditions including start-up are okay. • When using polarized capacitors, the positive terminal of C1 must be connected to terminal 2 of the TL7660, and the positive terminal of C2 must be connected to GND. • If the voltage supply driving the TL7660 has a large source impedance (25 Ω – 30 Ω), then a 2.2-µF capacitor from terminal 8 to ground may be required to limit rate of rise of input voltage to less than 2V/µs. • Ensure that the output (terminal 5) does not go more positive than GND (terminal 3). Device latch up occurs under these conditions. A 1N914 or similar diode placed in parallel with C2 prevents the device from latching up under these conditions (anode to terminal 5, cathode to terminal 3). 8 Submit Documentation Feedback TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 APPLICATION INFORMATION (continued) Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the TL7660 for generation of negative supply voltages. Figure 3 shows typical connections to provide a negative supply negative (GND) for supply voltages below 3.5 V. V+ 8 1 7 2 10 µF + - 3 TL7660 4 6 5 VOUT = –V+ 10 µF + Figure 3. Simple Negative-Voltage Converter The output characteristics of the circuit in Figure 3 can be approximated by an ideal voltage source in series with a resistance. The voltage source has a value of –VCC. The output impedance (RO) is a function of the ON resistance of the internal MOS switches (shown in Figure 2), the switching frequency, the value of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first order approximation for RO is: RO ≈ 2(RSW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 + ESRC1) RO ≈ 2(RSW1 + RSW3 + ESRC1) + 1/fPUMPC1 + ESRC2 Where fPUMP = fOSC/2 , RSWX = MOSFET switch resistance. Combining the four RSWX terms as RSW, we see that: RO ≈ 2 (RSW) + 1/fPUMPC1 + 4 (ESRC1) + ESRC2 RSW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs). Careful selection of C1 and C2 reduces the remaining terms, minimizing the output impedance. High value capacitors reduce the 1/fPUMPC1 component, and low ESR capacitors lower the ESR term. Increasing the oscillator frequency reduces the 1/fPUMPC1 term but may have the side effect of a net increase in output impedance when C1 > 10 µF and there is no longer enough time to fully charge the capacitors every cycle. In a typical application where fOSC = 10 kHz and C = C1 = C2 = 10 µF: RO ≈ 2(23) + 1/(5 × 103)(10–5) + 4(ESRC1) + ESRC2 RO ≈ 46 + 20 + 5 (ESRC) Because the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/fPUMPC1 term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10 Ω. Submit Documentation Feedback 9 TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 APPLICATION INFORMATION (continued) Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by two voltages, A and B, as shown in Figure 4. Segment A is the voltage drop across the ESR of C2 at the instant it goes from being charged by C1 (current flow into C2) to being discharged through the load (current flowing out of C2). The magnitude of this current change is 2 × IOUT, hence the total drop is 2 × IOUT × eSRC2 V. Segment B is the voltage change across C2 during time t2, the half of the cycle when C2 supplies current to the load. The drop at B is IOUT × t2/C2 V. The peak-to-peak ripple voltage is the sum of these voltage drops: VRIPPLE ≈ (1/(2fPUMPC2) + 2(ESRC2)) × IOUT Again, a low ESR capacitor results in a higher performance output. t2 t1 B 0 V A –V+ Figure 4. Output Ripple Paralleling Devices Any number of TL7660 voltage converters may be paralleled to reduce output resistance (see Figure 5). The reservoir capacitor, C2, serves all devices, while each device requires its own pump capacitor, C1. The resultant output resistance would be approximately: ROUT = ROUT (of TL7660)/n (number of devices) V+ 1 2 + C1 - 3 4 8 TL7660 "1" 7 1 6 5 2 C1 + - 3 8 TL7660 "n" 4 RL 7 6 5 C2 + Figure 5. Paralleling Devices 10 Submit Documentation Feedback TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 APPLICATION INFORMATION (continued) Cascading Devices The TL7660 may be cascaded as shown to produced larger negative multiplication of the initial supply voltage (see Figure 6). However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by: VOUT = –n (VIN) Where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual TL7660 ROUT values. V+ 8 1 2 + 10 µF - 3 TL7660 "1" 7 5 4 8 1 6 2 + 10 µF - 3 TL7660 "n" 7 6 5 4 10 µF + VOUT = –nV+ 10 µF + Figure 6. Cascading Devices for Increased Output Voltage Changing the TL7660 Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. This is achieved by overdriving the oscillator from an external clock, as shown in Figure 7. To prevent possible device latchup, a 1-kΩ resistor must be used in series with the clock output. When the external clock frequency is generated using TTL logic, the addition of a 10-kΩ pullup resistor to VCC supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. Output transitions occur on the positive-going edge of the clock. V+ 8 1 CMOS Gate 7 2 + 10 µF – V+ TL7660 3 6 4 5 VOUT –10 µF ++ Figure 7. External Clocking Submit Documentation Feedback 11 TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 APPLICATION INFORMATION (continued) It is also possible to increase the conversion efficiency of the TL7660 at low load levels by lowering the oscillator frequency (see Figure 8). This reduces the switching losses. However, lowering the oscillator frequency causes an undesirable increase in the impedance of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same factor that the frequency has been reduced. For example, the addition of a 100-pF capacitor between terminal 7 (OSC) and VCC lowers the oscillator frequency to 1 kHz from its nominal frequency of 10 kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C1 and C2 (from 10 µF to 100 µF). V+ C1 1 8 2 7 TL7660 ++ -- 3 6 4 5 COSC VOUT -C2 + + Figure 8. Lowering Oscillator Frequency Positive Voltage Doubling The TL7660 may be used to achieve positive voltage doubling using the circuit shown in Figure 9. In this application, the pump inverter switches of the TL7660 are used to charge C1 to a voltage level of VCC – VF (where VCC is the supply voltage and VF is the forward voltage drop of diode D1). On the transfer cycle, the voltage on C1 plus the supply voltage (VCC) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes (2VCC) – (2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D1 and D2. The source impedance of the output (VOUT) depends on the output current. V+ 1 8 7 D1 3 6 D2 4 5 2 TL7660 VOUT = (2V+) – (2VF) C2 C1 Figure 9. Positive-Voltage Doubler 12 Submit Documentation Feedback TL7660 CMOS VOLTAGE CONVERTER www.ti.com SCAS794 – JUNE 2006 APPLICATION INFORMATION (continued) Combined Negative Voltage Conversion and Positive Supply Doubling Figure 10 combines the functions shown in Figure 3 and Figure 9 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating +9 V and –5 V from an existing 5-V supply. In this instance, capacitors C1 and C3 perform the pump and reservoir functions, respectively, for the generation of the negative voltage, while capacitors C2 and C4 are pump and reservoir, respectively, for the doubled positive voltage. There is a penalty in this configuration that combines both functions, however, in that the source impedances of the generated supplies are somewhat higher, due to the finite impedance of the common charge pump driver at terminal 2 of the device. V+ VOUT = –(nVIN – VFDX) 8 1 7 2 + C1 - + C3 TL7660 3 6 4 5 D1 D2 - VOUT = (2V+) – (VFD1) – (VFD2) + C2 + C4 - Figure 10. Combined Negative-Voltage Converter and Positive-Voltage Doubler Voltage Splitting The bidirectional characteristics can also be used to split a higher supply in half (see Figure 11. The combined load is evenly shared between the two sides. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit and then the circuit of Figure 6, 15 V can be converted (via 7.5 V, and –7.5 V) to a nominal –15 V, although with rather high series output resistance (~250 Ω). V+ RL1 + 50 µF VOUT = V+ V 2 8 1 7 2 TL7660 + 50 µF RL2 50 µF + - 3 6 4 5 V– Figure 11. Splitting a Supply in Half Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TL7660CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7660CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7660ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7660IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7660IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2006 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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