HD74HCT137 3-to-8-line Decoder/Demultiplexer with Address Latch Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation of glitchfree decoders in stored-address applications in bus oriented systems. Features • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (C L = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT137 Function Table Inputs Enable Select Outputs GL G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X L X X X X H H H H H H H H L H L L L L L H H H H H H H L H L L L H H L H H H H H H L H L L H L H H L H H H H H L H L L H H H H H L H H H H L H L H L L H H H H L H H H L H L H L H H H H H H L H H L H L H H L H H H H H H L H L H L H H H H H H H H H H L H H L X X X Output Corresponding to stored address L; all others H Pin Arrangement 16 VCC A 1 A Y0 15 Y0 C Y1 14 Y1 GL 4 GL Y2 13 Y2 G2 5 G2 Y3 12 Y3 G1 6 G1 Y4 11 Y4 Y7 7 Y7 Y5 10 Y5 B 2 B C 3 Y6 9 Y6 GND 8 (Top view) 2 HD74HCT137 Logic Diagram CK Y0 A CK CK CK Y1 B Y2 C Y3 CK Y4 CK GL Y5 Y6 Y7 G2 G1 DC Characteristics Ta = –40 to +85°C Ta = 25°C Test Conditions Item Symbol Min Typ Max Min Max Unit VCC (V) Input voltage VIH 2.0 — — — V 4.5 to 5.5 VIL — — 0.8 — 0.8 V 4.5 to 5.5 VOH 4.4 — — 4.4 — V 4.5 Vin = VIH or VIL I OH = –20 µA 4.18 — — 4.13 — 4.5 I OH = –4 mA — — 0.1 — 0.1 — — 0.26 — 0.33 Output voltage VOL 2.0 V 4.5 Vin = VIH or VIL I OL = 20 µA 4.5 I OL = 4 mA Input current Iin — — ±0.1 — ±1.0 µA 5.5 Vin = VCC or GND Quiescent supply current I CC — — 4.0 — 40 µA 5.5 Vin = VCC or GND, Iout = 0 µA 3 HD74HCT137 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Test Conditions Min Typ Max Min Max Unit VCC (V) Propagation delay t PLH — 14 34 — 43 ns 4.5 time t PHL — 22 48 — 60 t PLH — 11 26 — 33 t PHL — 23 39 — 49 t PLH — 13 30 — 38 t PHL — 17 39 — 49 t PLH — 16 35 — 44 t PHL — 23 50 — 63 Pulse width tw 16 6 — 20 — ns 4.5 Setup time t su 20 3 — 25 — ns 4.5 Hold time th 10 0 — 13 — ns 4.5 Output rise/fall time t TLH t THL — 5 15 — 19 ns 4.5 Input capacitance Cin — 5 10 — 10 pF — Item 4 Symbol A, B or C to Y 4.5 ns 4.5 G2 to Y 4.5 ns 4.5 G1 to Y 4.5 ns 4.5 4.5 GL to Y Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Cautions 1. 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