TI SN74AC574N

SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
D
SN54AC574 . . . J OR W PACKAGE
SN74AC574 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3-State Outputs Drive Bus Lines Directly
EPICt (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIP Packages
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
2D
1D
OE
VCC
SN54AC574 . . . FK PACKAGE
(TOP VIEW)
The eight flip-flops of the ′AC574 are D-type
edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set
to the logic levels set up at the data (D) inputs.
3D
4D
5D
6D
7D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
CLK
8Q
7Q
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
1Q
D
D
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54AC574 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74AC574 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
logic symbol†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
logic diagram (positive logic)
EN
OE
C1
1D
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
CLK
1
11
1Q
C1
2Q
3Q
1D
2
19
1Q
1D
4Q
5Q
6Q
7Q
To Seven Other Channels
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . 1.3 W
PW package . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
MIN
MAX
2
6
2
6
2.1
2.1
3.15
3.15
0
0
High-level output current
Low-level output current
∆t /∆v
MAX
VCC = 4.5V
VCC = 5.5 V
Output voltage
IOL
SN74AC574
MIN
3.85
Input voltage
IOH
SN54AC574
3.85
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
0
VCC
VCC
–12
–12
–24
–24
VCC = 5.5 V
VCC = 3 V
–24
–24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
V
V
VCC = 3 V
VCC = 4.5 V
Input transition rise or fall rate
UNIT
V
V
V
mA
mA
0
8
0
8
ns / V
–55
125
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = – 50 µA
VOH
IOH = – 12 mA
IOH = – 24 mA
IOL = 50 µA
VOL
IOL = 12 mA
IOL = 24 mA
II
IOZ
VI = VCC or GND
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
IO = 0
MIN
TA = 25°C
TYP
MAX
SN54AC574
SN74AC574
MIN
MIN
MAX
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.56
2.4
2.46
4.5 V
3.94
3.7
3.76
5.5 V
4.94
4.7
MAX
UNIT
V
4.76
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
± 0.1
±1
±1
µA
5.5 V
± 0.5
±5
± 2.5
µA
5.5 V
4
80
40
µA
5V
POST OFFICE BOX 655303
4.5
• DALLAS, TEXAS 75265
V
pF
3
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54AC574
MIN
SN74AC574
MAX
MIN
UNIT
MAX
tw
tsu
Pulse duration, CLK high or low
6
7.5
7
ns
Setup time, data before CLK↑
2.5
6.5
3
ns
th
Hold time, data after CLK↑
1.5
2.5
1.5
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54AC574
MIN
SN74AC574
MAX
MIN
UNIT
MAX
tw
tsu
Pulse duration, CLK high or low
4
5
5
ns
Setup time, data before CLK↑
1.5
3.5
2
ns
th
Hold time, data after CLK↑
1.5
2.5
1.5
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
TO
(INPUT)
TO
(OUTPUT)
CLK
Q
OE
Q
OE
Q
MIN
TA = 25°C
TYP
MAX
SN54AC574
MIN
MAX
SN74AC574
MIN
55
MAX
75
112
60
3.5
8.5
13.5
1
16.5
3.5
15
3.5
7.5
12
1
15
3.5
13.5
2.5
7
11
1
13
2.5
12
3
6.5
10.5
1
12.5
3
11.5
3.5
7.5
12
1
14
2.5
13
2
5.5
9
1
10.5
1.5
10
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
TO
(INPUT)
TO
(OUTPUT)
CLK
Q
OE
Q
OE
Q
TA = 25°C
MIN
TYP
MAX
SN54AC574
MIN
MAX
85
SN74AC574
MIN
MAX
95
153
2
6
9.5
1.5
11.5
85
2
11
2
5.5
8.5
1.5
10.5
2
9.5
2
5
8.5
1.5
9.5
2
9
2
5
8
1.5
9.5
1.5
9
2
6
9.5
1.5
11.5
1.5
10.5
1
4.5
7.5
1.5
9
1
8.5
UNIT
MHz
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
40
pF
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
S1
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
Open
2 × VCC
Open
500 Ω
CL = 50 pF
(see Note A)
LOAD CIRCUIT
VCC
50% VCC
Timing Input
0V
tw
tsu
3V
Input 50% VCC
50% VCC
Data Input
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
50% VCC
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VCC
50% VCC
VOH
50% VCC
VOL
Output
Waveform 2
S1 at Open
(see Note B)
50% VCC
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
50% VCC
0V
VOLTAGE WAVEFORMS
50% VCC
VCC
50% VCC
0V
Input
th
50% VCC
tPHZ
tPZH
VOLTAGE WAVEFORMS
VOL + 0.3 V
VOL
50% VCC
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
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